Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	13031145	9414	0	0
alert_regwen_rd_A	13031145	5795	0	0
cpu_regwen_rd_A	13031145	5603	0	0
sw_rst_ctrl_n_0_rd_A	13031145	10921	0	0
sw_rst_ctrl_n_1_rd_A	13031145	10865	0	0
sw_rst_ctrl_n_2_rd_A	13031145	10543	0	0
sw_rst_ctrl_n_3_rd_A	13031145	10552	0	0
sw_rst_ctrl_n_4_rd_A	13031145	10607	0	0
sw_rst_ctrl_n_5_rd_A	13031145	10871	0	0
sw_rst_ctrl_n_6_rd_A	13031145	10759	0	0
sw_rst_ctrl_n_7_rd_A	13031145	10583	0	0
sw_rst_regwen_0_rd_A	13031145	6326	0	0
sw_rst_regwen_1_rd_A	13031145	6132	0	0
sw_rst_regwen_2_rd_A	13031145	5979	0	0
sw_rst_regwen_3_rd_A	13031145	6097	0	0
sw_rst_regwen_4_rd_A	13031145	6029	0	0
sw_rst_regwen_5_rd_A	13031145	6148	0	0
sw_rst_regwen_6_rd_A	13031145	5971	0	0
sw_rst_regwen_7_rd_A	13031145	6007	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13031145	9414	0	0
T69	9763	1	0	0
T72	20966	3	0	0
T73	3340	12	0	0
T74	5401	273	0	0
T75	4043	123	0	0
T84	3254	21	0	0
T85	4313	13	0	0
T86	4419	14	0	0
T87	18506	5	0	0
T91	16495	4	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13031145	5795	0	0
T11	42048	66	0	0
T12	2584	0	0	0
T13	2928	0	0	0
T14	2903	0	0	0
T15	2482	0	0	0
T16	123359	180	0	0
T17	3519	0	0	0
T27	3307	0	0	0
T28	26073	0	0	0
T29	1499	0	0	0
T64	0	48	0	0
T97	0	41	0	0
T100	0	82	0	0
T102	0	358	0	0
T122	0	19	0	0
T123	0	52	0	0
T124	0	37	0	0
T125	0	81	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13031145	5603	0	0
T11	42048	40	0	0
T12	2584	0	0	0
T13	2928	0	0	0
T14	2903	0	0	0
T15	2482	0	0	0
T16	123359	171	0	0
T17	3519	0	0	0
T27	3307	0	0	0
T28	26073	0	0	0
T29	1499	0	0	0
T64	0	56	0	0
T97	0	52	0	0
T100	0	83	0	0
T102	0	328	0	0
T122	0	33	0	0
T123	0	96	0	0
T124	0	39	0	0
T125	0	70	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13031145	10921	0	0
T11	42048	59	0	0
T12	2584	0	0	0
T13	2928	0	0	0
T14	2903	13	0	0
T15	2482	0	0	0
T16	123359	327	0	0
T17	3519	0	0	0
T27	3307	0	0	0
T28	26073	0	0	0
T29	1499	0	0	0
T46	0	41	0	0
T54	0	114	0	0
T57	0	16	0	0
T64	0	60	0	0
T97	0	50	0	0
T126	0	32	0	0
T127	0	209	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13031145	10865	0	0
T11	42048	51	0	0
T12	2584	0	0	0
T13	2928	0	0	0
T14	2903	21	0	0
T15	2482	0	0	0
T16	123359	243	0	0
T17	3519	0	0	0
T27	3307	0	0	0
T28	26073	0	0	0
T29	1499	0	0	0
T46	0	40	0	0
T54	0	139	0	0
T57	0	21	0	0
T64	0	41	0	0
T97	0	65	0	0
T126	0	35	0	0
T127	0	181	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13031145	10543	0	0
T11	42048	64	0	0
T12	2584	0	0	0
T13	2928	0	0	0
T14	2903	21	0	0
T15	2482	0	0	0
T16	123359	260	0	0
T17	3519	0	0	0
T27	3307	0	0	0
T28	26073	0	0	0
T29	1499	0	0	0
T46	0	52	0	0
T54	0	126	0	0
T57	0	14	0	0
T64	0	34	0	0
T97	0	37	0	0
T126	0	30	0	0
T127	0	180	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13031145	10552	0	0
T11	42048	54	0	0
T12	2584	0	0	0
T13	2928	0	0	0
T14	2903	15	0	0
T15	2482	0	0	0
T16	123359	216	0	0
T17	3519	0	0	0
T27	3307	0	0	0
T28	26073	0	0	0
T29	1499	0	0	0
T46	0	50	0	0
T54	0	122	0	0
T57	0	18	0	0
T64	0	58	0	0
T97	0	45	0	0
T126	0	34	0	0
T127	0	180	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13031145	10607	0	0
T11	42048	45	0	0
T12	2584	0	0	0
T13	2928	0	0	0
T14	2903	27	0	0
T15	2482	0	0	0
T16	123359	282	0	0
T17	3519	0	0	0
T27	3307	0	0	0
T28	26073	0	0	0
T29	1499	0	0	0
T46	0	56	0	0
T54	0	128	0	0
T57	0	26	0	0
T64	0	72	0	0
T97	0	47	0	0
T126	0	30	0	0
T127	0	176	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13031145	10871	0	0
T11	42048	30	0	0
T12	2584	0	0	0
T13	2928	0	0	0
T14	2903	21	0	0
T15	2482	0	0	0
T16	123359	285	0	0
T17	3519	0	0	0
T27	3307	0	0	0
T28	26073	0	0	0
T29	1499	0	0	0
T46	0	54	0	0
T54	0	101	0	0
T57	0	31	0	0
T64	0	55	0	0
T97	0	53	0	0
T126	0	41	0	0
T127	0	206	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13031145	10759	0	0
T11	42048	48	0	0
T12	2584	0	0	0
T13	2928	0	0	0
T14	2903	34	0	0
T15	2482	0	0	0
T16	123359	268	0	0
T17	3519	0	0	0
T27	3307	0	0	0
T28	26073	0	0	0
T29	1499	0	0	0
T46	0	50	0	0
T54	0	137	0	0
T57	0	13	0	0
T64	0	55	0	0
T97	0	57	0	0
T126	0	24	0	0
T127	0	161	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13031145	10583	0	0
T11	42048	64	0	0
T12	2584	0	0	0
T13	2928	0	0	0
T14	2903	24	0	0
T15	2482	0	0	0
T16	123359	239	0	0
T17	3519	0	0	0
T27	3307	0	0	0
T28	26073	0	0	0
T29	1499	0	0	0
T46	0	31	0	0
T54	0	137	0	0
T57	0	16	0	0
T64	0	26	0	0
T97	0	27	0	0
T126	0	18	0	0
T127	0	168	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13031145	6326	0	0
T11	42048	59	0	0
T12	2584	0	0	0
T13	2928	0	0	0
T14	2903	0	0	0
T15	2482	0	0	0
T16	123359	183	0	0
T17	3519	0	0	0
T27	3307	0	0	0
T28	26073	0	0	0
T29	1499	0	0	0
T54	0	34	0	0
T64	0	64	0	0
T97	0	42	0	0
T122	0	41	0	0
T127	0	38	0	0
T128	0	27	0	0
T129	0	3	0	0
T130	0	2	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13031145	6132	0	0
T11	42048	40	0	0
T12	2584	0	0	0
T13	2928	0	0	0
T14	2903	0	0	0
T15	2482	0	0	0
T16	123359	115	0	0
T17	3519	0	0	0
T27	3307	0	0	0
T28	26073	0	0	0
T29	1499	0	0	0
T54	0	34	0	0
T64	0	43	0	0
T97	0	43	0	0
T122	0	42	0	0
T127	0	20	0	0
T128	0	41	0	0
T129	0	10	0	0
T131	0	11	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13031145	5979	0	0
T11	42048	43	0	0
T12	2584	0	0	0
T13	2928	0	0	0
T14	2903	0	0	0
T15	2482	0	0	0
T16	123359	158	0	0
T17	3519	0	0	0
T27	3307	0	0	0
T28	26073	0	0	0
T29	1499	0	0	0
T54	0	31	0	0
T64	0	59	0	0
T97	0	16	0	0
T122	0	31	0	0
T127	0	24	0	0
T128	0	33	0	0
T129	0	1	0	0
T131	0	7	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13031145	6097	0	0
T11	42048	49	0	0
T12	2584	0	0	0
T13	2928	0	0	0
T14	2903	0	0	0
T15	2482	0	0	0
T16	123359	166	0	0
T17	3519	0	0	0
T27	3307	0	0	0
T28	26073	0	0	0
T29	1499	0	0	0
T54	0	51	0	0
T64	0	59	0	0
T97	0	53	0	0
T122	0	25	0	0
T127	0	31	0	0
T128	0	31	0	0
T129	0	11	0	0
T130	0	4	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13031145	6029	0	0
T11	42048	46	0	0
T12	2584	0	0	0
T13	2928	0	0	0
T14	2903	0	0	0
T15	2482	0	0	0
T16	123359	150	0	0
T17	3519	0	0	0
T27	3307	0	0	0
T28	26073	0	0	0
T29	1499	0	0	0
T54	0	38	0	0
T64	0	54	0	0
T97	0	63	0	0
T122	0	17	0	0
T127	0	30	0	0
T128	0	42	0	0
T129	0	5	0	0
T131	0	7	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13031145	6148	0	0
T11	42048	48	0	0
T12	2584	0	0	0
T13	2928	0	0	0
T14	2903	0	0	0
T15	2482	0	0	0
T16	123359	150	0	0
T17	3519	0	0	0
T27	3307	0	0	0
T28	26073	0	0	0
T29	1499	0	0	0
T54	0	34	0	0
T64	0	53	0	0
T97	0	34	0	0
T122	0	52	0	0
T127	0	30	0	0
T128	0	19	0	0
T129	0	5	0	0
T131	0	6	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13031145	5971	0	0
T11	42048	64	0	0
T12	2584	0	0	0
T13	2928	0	0	0
T14	2903	0	0	0
T15	2482	0	0	0
T16	123359	161	0	0
T17	3519	0	0	0
T27	3307	0	0	0
T28	26073	0	0	0
T29	1499	0	0	0
T54	0	32	0	0
T64	0	57	0	0
T97	0	34	0	0
T122	0	29	0	0
T127	0	27	0	0
T128	0	18	0	0
T129	0	12	0	0
T130	0	11	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13031145	6007	0	0
T11	42048	53	0	0
T12	2584	0	0	0
T13	2928	0	0	0
T14	2903	0	0	0
T15	2482	0	0	0
T16	123359	153	0	0
T17	3519	0	0	0
T27	3307	0	0	0
T28	26073	0	0	0
T29	1499	0	0	0
T54	0	27	0	0
T64	0	37	0	0
T97	0	37	0	0
T122	0	48	0	0
T127	0	21	0	0
T128	0	42	0	0
T129	0	8	0	0
T130	0	3	0	0