Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	604070	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

363284

1

T1

6

T2

148

T3

1115

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	515057	1			T2	186		T3	1500		T4	186
values[0x0]	226283	1			T1	11		T2	93		T3	842
values[0x1]	226014	1			T1	10		T2	100		T3	858

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	507012	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

460342

1

T1

8

T2

183

T3

1452

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3621	1			T2	2		T4	2		T6	16
valid_sources[0x01]	4927	1			T4	4		T6	2		T10	19
valid_sources[0x02]	3857	1			T2	1		T4	3		T6	9
valid_sources[0x03]	4056	1			T2	2		T4	2		T6	12
valid_sources[0x04]	2454	1			T1	2		T4	1		T6	2
valid_sources[0x05]	3552	1			T2	1		T4	2		T6	7
valid_sources[0x06]	3790	1			T2	3		T6	15		T13	67
valid_sources[0x07]	3485	1			T4	2		T10	33		T13	65
valid_sources[0x08]	3027	1			T4	2		T6	22		T10	25
valid_sources[0x09]	4219	1			T2	1		T4	2		T6	13
valid_sources[0x0a]	2698	1			T6	11		T10	14		T13	56
valid_sources[0x0b]	3921	1			T6	11		T10	3		T13	44
valid_sources[0x0c]	3369	1			T2	3		T4	4		T6	3
valid_sources[0x0d]	3874	1			T2	1		T4	5		T6	15
valid_sources[0x0e]	3476	1			T4	1		T6	13		T10	8
valid_sources[0x0f]	3176	1			T4	2		T6	18		T10	4
valid_sources[0x10]	3593	1			T2	1		T4	5		T6	12
valid_sources[0x11]	4099	1			T2	4		T4	1		T6	30
valid_sources[0x12]	3207	1			T2	3		T4	2		T6	10
valid_sources[0x13]	3341	1			T2	1		T4	3		T6	14
valid_sources[0x14]	6667	1			T2	1		T4	1		T6	16
valid_sources[0x15]	2595	1			T4	2		T6	9		T10	8
valid_sources[0x16]	2892	1			T2	1		T4	2		T6	16
valid_sources[0x17]	2963	1			T4	1		T6	17		T10	21
valid_sources[0x18]	3613	1			T2	2		T6	10		T10	1
valid_sources[0x19]	4612	1			T2	2		T4	2		T6	14
valid_sources[0x1a]	3514	1			T2	1		T4	2		T6	29
valid_sources[0x1b]	3241	1			T2	4		T4	1		T6	6
valid_sources[0x1c]	3777	1			T4	4		T6	22		T13	62
valid_sources[0x1d]	3125	1			T4	2		T6	18		T10	27
valid_sources[0x1e]	3710	1			T2	1		T4	1		T6	13
valid_sources[0x1f]	3835	1			T2	2		T4	2		T6	3
valid_sources[0x20]	3893	1			T2	1		T4	2		T6	13
valid_sources[0x21]	3977	1			T2	2		T4	3		T6	5
valid_sources[0x22]	3366	1			T4	1		T6	17		T10	18
valid_sources[0x23]	3545	1			T4	1		T6	9		T10	26
valid_sources[0x24]	3742	1			T2	1		T6	8		T10	25
valid_sources[0x25]	3024	1			T2	1		T4	2		T6	2
valid_sources[0x26]	4547	1			T4	4		T6	16		T10	27
valid_sources[0x27]	3693	1			T6	1		T12	1		T13	54
valid_sources[0x28]	2889	1			T2	3		T4	1		T6	18
valid_sources[0x29]	5485	1			T2	1		T4	4		T6	27
valid_sources[0x2a]	4727	1			T2	1		T4	1		T6	13
valid_sources[0x2b]	3635	1			T2	2		T6	14		T10	52
valid_sources[0x2c]	3320	1			T2	4		T4	1		T6	6
valid_sources[0x2d]	2945	1			T2	1		T4	1		T6	9
valid_sources[0x2e]	2847	1			T2	4		T6	27		T10	24
valid_sources[0x2f]	3725	1			T2	1		T4	4		T6	6
valid_sources[0x30]	3162	1			T2	2		T6	22		T10	22
valid_sources[0x31]	3143	1			T2	4		T6	3		T10	2
valid_sources[0x32]	2512	1			T2	2		T6	16		T13	53
valid_sources[0x33]	4020	1			T2	2		T4	1		T6	13
valid_sources[0x34]	4742	1			T2	2		T6	23		T10	18
valid_sources[0x35]	3524	1			T6	7		T10	6		T13	47
valid_sources[0x36]	3673	1			T2	2		T6	17		T10	13
valid_sources[0x37]	3228	1			T2	1		T4	2		T13	53
valid_sources[0x38]	3589	1			T2	5		T4	2		T6	28
valid_sources[0x39]	5735	1			T2	2		T4	2		T6	14
valid_sources[0x3a]	3447	1			T2	1		T6	17		T10	30
valid_sources[0x3b]	3303	1			T6	9		T10	9		T13	50
valid_sources[0x3c]	3415	1			T2	2		T4	1		T6	8
valid_sources[0x3d]	3359	1			T2	2		T4	1		T6	25
valid_sources[0x3e]	3875	1			T4	2		T6	6		T10	5
valid_sources[0x3f]	3985	1			T4	4		T6	11		T10	36
valid_sources[0x40]	3632	1			T2	2		T4	1		T6	23
valid_sources[0x41]	3531	1			T4	2		T6	7		T10	26
valid_sources[0x42]	3383	1			T2	8		T6	4		T10	5
valid_sources[0x43]	3668	1			T4	5		T6	27		T12	8
valid_sources[0x44]	3769	1			T2	2		T4	2		T6	14
valid_sources[0x45]	2973	1			T6	29		T10	4		T13	54
valid_sources[0x46]	5472	1			T2	1		T4	3		T6	13
valid_sources[0x47]	3499	1			T4	2		T6	5		T10	2
valid_sources[0x48]	3693	1			T2	4		T4	1		T6	6
valid_sources[0x49]	3047	1			T4	5		T6	15		T10	12
valid_sources[0x4a]	2551	1			T2	1		T4	3		T6	7
valid_sources[0x4b]	3291	1			T2	3		T4	1		T6	13
valid_sources[0x4c]	3369	1			T4	1		T6	48		T13	62
valid_sources[0x4d]	2911	1			T2	3		T4	2		T6	19
valid_sources[0x4e]	3395	1			T2	2		T6	16		T10	11
valid_sources[0x4f]	2922	1			T2	3		T4	2		T6	5
valid_sources[0x50]	3237	1			T6	2		T10	7		T13	66
valid_sources[0x51]	3767	1			T2	1		T4	1		T6	6
valid_sources[0x52]	4391	1			T2	1		T4	3		T6	12
valid_sources[0x53]	3633	1			T1	1		T2	1		T4	2
valid_sources[0x54]	3775	1			T4	2		T10	45		T13	66
valid_sources[0x55]	4228	1			T2	3		T6	2		T10	1
valid_sources[0x56]	3881	1			T4	1		T6	4		T10	8
valid_sources[0x57]	2908	1			T2	1		T4	1		T6	23
valid_sources[0x58]	3335	1			T2	1		T4	1		T6	21
valid_sources[0x59]	3445	1			T2	2		T4	4		T6	54
valid_sources[0x5a]	6752	1			T4	3		T6	3		T10	2
valid_sources[0x5b]	3924	1			T4	2		T6	6		T10	8
valid_sources[0x5c]	2865	1			T2	5		T4	4		T6	6
valid_sources[0x5d]	3696	1			T2	2		T4	1		T6	35
valid_sources[0x5e]	3905	1			T2	1		T6	23		T10	23
valid_sources[0x5f]	3493	1			T4	4		T6	4		T10	43
valid_sources[0x60]	3083	1			T2	3		T6	2		T10	4
valid_sources[0x61]	2736	1			T6	29		T10	7		T13	61
valid_sources[0x62]	3921	1			T6	4		T10	30		T13	57
valid_sources[0x63]	3374	1			T2	1		T6	8		T10	24
valid_sources[0x64]	2772	1			T2	2		T4	2		T6	8
valid_sources[0x65]	3172	1			T4	2		T6	7		T10	24
valid_sources[0x66]	6162	1			T2	1		T6	11		T13	50
valid_sources[0x67]	3855	1			T2	4		T4	1		T6	23
valid_sources[0x68]	3240	1			T6	3		T10	23		T13	75
valid_sources[0x69]	2942	1			T2	2		T6	6		T10	14
valid_sources[0x6a]	2973	1			T2	1		T6	10		T12	4
valid_sources[0x6b]	2565	1			T2	1		T4	1		T6	10
valid_sources[0x6c]	5811	1			T4	1		T6	10		T10	41
valid_sources[0x6d]	3188	1			T2	2		T6	5		T12	1
valid_sources[0x6e]	4298	1			T2	3		T4	2		T6	31
valid_sources[0x6f]	3229	1			T2	1		T6	26		T10	5
valid_sources[0x70]	4548	1			T2	2		T6	8		T10	9
valid_sources[0x71]	4758	1			T2	2		T6	22		T12	3
valid_sources[0x72]	3559	1			T2	1		T6	33		T13	67
valid_sources[0x73]	3780	1			T2	2		T4	3		T6	11
valid_sources[0x74]	3425	1			T2	1		T4	1		T6	8
valid_sources[0x75]	2881	1			T6	3		T13	69		T15	3
valid_sources[0x76]	4672	1			T2	1		T4	1		T6	27
valid_sources[0x77]	3024	1			T4	2		T6	2		T10	5
valid_sources[0x78]	3467	1			T2	2		T4	1		T6	6
valid_sources[0x79]	3043	1			T4	1		T6	25		T10	4
valid_sources[0x7a]	7822	1			T2	1		T4	1		T6	27
valid_sources[0x7b]	3035	1			T2	3		T4	1		T6	19
valid_sources[0x7c]	3292	1			T4	2		T6	6		T13	82
valid_sources[0x7d]	4059	1			T2	4		T4	2		T6	16
valid_sources[0x7e]	3382	1			T2	5		T4	2		T6	9
valid_sources[0x7f]	4025	1			T2	1		T4	1		T6	12
valid_sources[0x80]	3407	1			T2	1		T4	1		T6	8

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

241485

1

T2

86

T3

690

T4

85

values[0x0]

all_enables

biggest_size

79336

1

T1

4

T2

44

T3

281

values[0x1]

all_enables

biggest_size

42463

1

T1

2

T2

18

T3

144