Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T2,T3,T4

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11927250	13100	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11927250	120534	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11927250	7174177	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11927250	192826	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11927250	13100	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11927250	120534	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11927250	7174177	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11927250	192826	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11927250	13100	0	0
T2	4471	4	0	0
T3	53523	75	0	0
T4	2621	4	0	0
T5	5687	0	0	0
T6	41938	75	0	0
T7	5680	0	0	0
T8	5472	0	0	0
T9	5734	4	0	0
T10	26101	75	0	0
T11	2186	0	0	0
T12	0	16	0	0
T13	0	191	0	0
T15	0	4	0	0
T27	0	8	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11927250	120534	0	0
T2	4471	37	0	0
T3	53523	725	0	0
T4	2621	37	0	0
T5	5687	0	0	0
T6	41938	700	0	0
T7	5680	0	0	0
T8	5472	0	0	0
T9	5734	37	0	0
T10	26101	704	0	0
T11	2186	0	0	0
T12	0	144	0	0
T13	0	1725	0	0
T15	0	37	0	0
T27	0	72	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11927250	7174177	0	0
T1	1651	1062	0	0
T2	4471	3506	0	0
T3	53523	36008	0	0
T4	2621	1659	0	0
T5	5687	581	0	0
T6	41938	24650	0	0
T7	5680	581	0	0
T8	5472	577	0	0
T9	5734	4794	0	0
T10	26101	8815	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11927250	192826	0	0
T2	4471	58	0	0
T3	53523	1160	0	0
T4	2621	57	0	0
T5	5687	0	0	0
T6	41938	1152	0	0
T7	5680	0	0	0
T8	5472	0	0	0
T9	5734	45	0	0
T10	26101	1075	0	0
T11	2186	0	0	0
T12	0	242	0	0
T13	0	2823	0	0
T15	0	66	0	0
T27	0	116	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11927250	13100	0	0
T2	4471	4	0	0
T3	53523	75	0	0
T4	2621	4	0	0
T5	5687	0	0	0
T6	41938	75	0	0
T7	5680	0	0	0
T8	5472	0	0	0
T9	5734	4	0	0
T10	26101	75	0	0
T11	2186	0	0	0
T12	0	16	0	0
T13	0	191	0	0
T15	0	4	0	0
T27	0	8	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11927250	120534	0	0
T2	4471	37	0	0
T3	53523	725	0	0
T4	2621	37	0	0
T5	5687	0	0	0
T6	41938	700	0	0
T7	5680	0	0	0
T8	5472	0	0	0
T9	5734	37	0	0
T10	26101	704	0	0
T11	2186	0	0	0
T12	0	144	0	0
T13	0	1725	0	0
T15	0	37	0	0
T27	0	72	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11927250	7174177	0	0
T1	1651	1062	0	0
T2	4471	3506	0	0
T3	53523	36008	0	0
T4	2621	1659	0	0
T5	5687	581	0	0
T6	41938	24650	0	0
T7	5680	581	0	0
T8	5472	577	0	0
T9	5734	4794	0	0
T10	26101	8815	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11927250	192826	0	0
T2	4471	58	0	0
T3	53523	1160	0	0
T4	2621	57	0	0
T5	5687	0	0	0
T6	41938	1152	0	0
T7	5680	0	0	0
T8	5472	0	0	0
T9	5734	45	0	0
T10	26101	1075	0	0
T11	2186	0	0	0
T12	0	242	0	0
T13	0	2823	0	0
T15	0	66	0	0
T27	0	116	0	0