Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T2,T4,T9
0	1	Covered	T4,T13,T15
1	0	Covered	T9,T13,T29

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T5,T6
1	0	Covered	T2,T4,T9
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	55934980	8770	0	0
CascadeEffAonToRstPorAboveRise_A	55934980	8770	0	0
CascadeEffAonToRstPorIoAboveFall_A	53695677	8770	0	0
CascadeEffAonToRstPorIoAboveRise_A	53695677	8770	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26849123	8770	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26849123	8770	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13424229	8770	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13424229	8770	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26849032	8770	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26849032	8770	0	0
CascadeLcToLcAboveFall_A	55934980	21870	0	0
CascadeLcToLcAboveRise_A	55934980	21870	0	0
CascadeLcToLcAonAboveFall_A	1694550	21870	0	0
CascadeLcToLcAonAboveRise_A	1694550	21870	0	0
CascadeLcToLcShadowedAboveFall_A	55934980	21870	0	0
CascadeLcToLcShadowedAboveRise_A	55934980	21870	0	0
CascadePorToAonAboveFall_A	1694550	7007	0	0
CascadeSysToSysAboveFall_A	55934980	21870	0	0
CascadeSysToSysAboveRise_A	55934980	21870	0	0
ScanRstToAonRise_A	1694550	221	0	0
StablePorToAonRise_A	1694550	8770	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11927250	21870	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11927250	21870	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11927250	21870	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11927250	21870	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13424229	21870	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13424229	21870	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11927250	21870	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11927250	21870	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11927250	21870	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11927250	21870	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55934980	8770	0	0
T1	7162	1	0	0
T2	19627	2	0	0
T3	235857	27	0	0
T4	11919	2	0	0
T5	24371	8	0	0
T6	187759	27	0	0
T7	24337	8	0	0
T8	24279	8	0	0
T9	24911	2	0	0
T10	121762	27	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55934980	8770	0	0
T1	7162	1	0	0
T2	19627	2	0	0
T3	235857	27	0	0
T4	11919	2	0	0
T5	24371	8	0	0
T6	187759	27	0	0
T7	24337	8	0	0
T8	24279	8	0	0
T9	24911	2	0	0
T10	121762	27	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53695677	8770	0	0
T1	6876	1	0	0
T2	18843	2	0	0
T3	226445	27	0	0
T4	11443	2	0	0
T5	23392	8	0	0
T6	180272	27	0	0
T7	23369	8	0	0
T8	23301	8	0	0
T9	23918	2	0	0
T10	116873	27	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53695677	8770	0	0
T1	6876	1	0	0
T2	18843	2	0	0
T3	226445	27	0	0
T4	11443	2	0	0
T5	23392	8	0	0
T6	180272	27	0	0
T7	23369	8	0	0
T8	23301	8	0	0
T9	23918	2	0	0
T10	116873	27	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26849123	8770	0	0
T1	3436	1	0	0
T2	9423	2	0	0
T3	113214	27	0	0
T4	5720	2	0	0
T5	11696	8	0	0
T6	90124	27	0	0
T7	11682	8	0	0
T8	11650	8	0	0
T9	11956	2	0	0
T10	58463	27	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26849123	8770	0	0
T1	3436	1	0	0
T2	9423	2	0	0
T3	113214	27	0	0
T4	5720	2	0	0
T5	11696	8	0	0
T6	90124	27	0	0
T7	11682	8	0	0
T8	11650	8	0	0
T9	11956	2	0	0
T10	58463	27	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	8770	0	0
T1	1717	1	0	0
T2	4709	2	0	0
T3	56605	27	0	0
T4	2859	2	0	0
T5	5846	8	0	0
T6	45070	27	0	0
T7	5842	8	0	0
T8	5821	8	0	0
T9	5977	2	0	0
T10	29245	27	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	8770	0	0
T1	1717	1	0	0
T2	4709	2	0	0
T3	56605	27	0	0
T4	2859	2	0	0
T5	5846	8	0	0
T6	45070	27	0	0
T7	5842	8	0	0
T8	5821	8	0	0
T9	5977	2	0	0
T10	29245	27	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26849032	8770	0	0
T1	3436	1	0	0
T2	9421	2	0	0
T3	113227	27	0	0
T4	5722	2	0	0
T5	11704	8	0	0
T6	90143	27	0	0
T7	11681	8	0	0
T8	11653	8	0	0
T9	11956	2	0	0
T10	58440	27	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26849032	8770	0	0
T1	3436	1	0	0
T2	9421	2	0	0
T3	113227	27	0	0
T4	5722	2	0	0
T5	11704	8	0	0
T6	90143	27	0	0
T7	11681	8	0	0
T8	11653	8	0	0
T9	11956	2	0	0
T10	58440	27	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55934980	21870	0	0
T1	7162	1	0	0
T2	19627	6	0	0
T3	235857	102	0	0
T4	11919	6	0	0
T5	24371	8	0	0
T6	187759	102	0	0
T7	24337	8	0	0
T8	24279	8	0	0
T9	24911	6	0	0
T10	121762	102	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55934980	21870	0	0
T1	7162	1	0	0
T2	19627	6	0	0
T3	235857	102	0	0
T4	11919	6	0	0
T5	24371	8	0	0
T6	187759	102	0	0
T7	24337	8	0	0
T8	24279	8	0	0
T9	24911	6	0	0
T10	121762	102	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1694550	21870	0	0
T1	214	1	0	0
T2	587	6	0	0
T3	7090	102	0	0
T4	356	6	0	0
T5	733	8	0	0
T6	5647	102	0	0
T7	733	8	0	0
T8	730	8	0	0
T9	747	6	0	0
T10	3668	102	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1694550	21870	0	0
T1	214	1	0	0
T2	587	6	0	0
T3	7090	102	0	0
T4	356	6	0	0
T5	733	8	0	0
T6	5647	102	0	0
T7	733	8	0	0
T8	730	8	0	0
T9	747	6	0	0
T10	3668	102	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55934980	21870	0	0
T1	7162	1	0	0
T2	19627	6	0	0
T3	235857	102	0	0
T4	11919	6	0	0
T5	24371	8	0	0
T6	187759	102	0	0
T7	24337	8	0	0
T8	24279	8	0	0
T9	24911	6	0	0
T10	121762	102	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55934980	21870	0	0
T1	7162	1	0	0
T2	19627	6	0	0
T3	235857	102	0	0
T4	11919	6	0	0
T5	24371	8	0	0
T6	187759	102	0	0
T7	24337	8	0	0
T8	24279	8	0	0
T9	24911	6	0	0
T10	121762	102	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1694550	7007	0	0
T1	214	1	0	0
T2	587	1	0	0
T3	7090	27	0	0
T4	356	1	0	0
T5	733	8	0	0
T6	5647	27	0	0
T7	733	8	0	0
T8	730	8	0	0
T9	747	1	0	0
T10	3668	27	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55934980	21870	0	0
T1	7162	1	0	0
T2	19627	6	0	0
T3	235857	102	0	0
T4	11919	6	0	0
T5	24371	8	0	0
T6	187759	102	0	0
T7	24337	8	0	0
T8	24279	8	0	0
T9	24911	6	0	0
T10	121762	102	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55934980	21870	0	0
T1	7162	1	0	0
T2	19627	6	0	0
T3	235857	102	0	0
T4	11919	6	0	0
T5	24371	8	0	0
T6	187759	102	0	0
T7	24337	8	0	0
T8	24279	8	0	0
T9	24911	6	0	0
T10	121762	102	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1694550	221	0	0
T13	15155	6	0	0
T14	1146	0	0	0
T15	362	0	0	0
T27	405	0	0	0
T28	776	0	0	0
T29	5470	3	0	0
T40	0	1	0	0
T41	0	5	0	0
T44	0	1	0	0
T51	29494	5	0	0
T55	957	0	0	0
T74	0	5	0	0
T75	0	1	0	0
T89	340	0	0	0
T91	3678	0	0	0
T92	0	1	0	0
T95	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1694550	8770	0	0
T1	214	1	0	0
T2	587	2	0	0
T3	7090	27	0	0
T4	356	2	0	0
T5	733	8	0	0
T6	5647	27	0	0
T7	733	8	0	0
T8	730	8	0	0
T9	747	2	0	0
T10	3668	27	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11927250	21870	0	0
T1	1651	1	0	0
T2	4471	6	0	0
T3	53523	102	0	0
T4	2621	6	0	0
T5	5687	8	0	0
T6	41938	102	0	0
T7	5680	8	0	0
T8	5472	8	0	0
T9	5734	6	0	0
T10	26101	102	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11927250	21870	0	0
T1	1651	1	0	0
T2	4471	6	0	0
T3	53523	102	0	0
T4	2621	6	0	0
T5	5687	8	0	0
T6	41938	102	0	0
T7	5680	8	0	0
T8	5472	8	0	0
T9	5734	6	0	0
T10	26101	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11927250	21870	0	0
T1	1651	1	0	0
T2	4471	6	0	0
T3	53523	102	0	0
T4	2621	6	0	0
T5	5687	8	0	0
T6	41938	102	0	0
T7	5680	8	0	0
T8	5472	8	0	0
T9	5734	6	0	0
T10	26101	102	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11927250	21870	0	0
T1	1651	1	0	0
T2	4471	6	0	0
T3	53523	102	0	0
T4	2621	6	0	0
T5	5687	8	0	0
T6	41938	102	0	0
T7	5680	8	0	0
T8	5472	8	0	0
T9	5734	6	0	0
T10	26101	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	21870	0	0
T1	1717	1	0	0
T2	4709	6	0	0
T3	56605	102	0	0
T4	2859	6	0	0
T5	5846	8	0	0
T6	45070	102	0	0
T7	5842	8	0	0
T8	5821	8	0	0
T9	5977	6	0	0
T10	29245	102	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	21870	0	0
T1	1717	1	0	0
T2	4709	6	0	0
T3	56605	102	0	0
T4	2859	6	0	0
T5	5846	8	0	0
T6	45070	102	0	0
T7	5842	8	0	0
T8	5821	8	0	0
T9	5977	6	0	0
T10	29245	102	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11927250	21870	0	0
T1	1651	1	0	0
T2	4471	6	0	0
T3	53523	102	0	0
T4	2621	6	0	0
T5	5687	8	0	0
T6	41938	102	0	0
T7	5680	8	0	0
T8	5472	8	0	0
T9	5734	6	0	0
T10	26101	102	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11927250	21870	0	0
T1	1651	1	0	0
T2	4471	6	0	0
T3	53523	102	0	0
T4	2621	6	0	0
T5	5687	8	0	0
T6	41938	102	0	0
T7	5680	8	0	0
T8	5472	8	0	0
T9	5734	6	0	0
T10	26101	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11927250	21870	0	0
T1	1651	1	0	0
T2	4471	6	0	0
T3	53523	102	0	0
T4	2621	6	0	0
T5	5687	8	0	0
T6	41938	102	0	0
T7	5680	8	0	0
T8	5472	8	0	0
T9	5734	6	0	0
T10	26101	102	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11927250	21870	0	0
T1	1651	1	0	0
T2	4471	6	0	0
T3	53523	102	0	0
T4	2621	6	0	0
T5	5687	8	0	0
T6	41938	102	0	0
T7	5680	8	0	0
T8	5472	8	0	0
T9	5734	6	0	0
T10	26101	102	0	0