Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T12,T13
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T13
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T28
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T4,T9,T13
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T51
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T13,T14
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T13,T14,T51
1	0	Covered	T2,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T4,T13
1	0	Covered	T2,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13424229	13885	0	0
gen_assertions[0].RstEnOn_A	13424229	979	0	0
gen_assertions[0].RstNOff_A	13424229	13885	0	0
gen_assertions[0].RstNOn_A	13424229	979	0	0
gen_assertions[1].RstEnOff_A	53695677	12614	0	0
gen_assertions[1].RstEnOn_A	53695677	945	0	0
gen_assertions[1].RstNOff_A	53695677	12614	0	0
gen_assertions[1].RstNOn_A	53695677	945	0	0
gen_assertions[2].RstEnOff_A	26849123	12631	0	0
gen_assertions[2].RstEnOn_A	26849123	886	0	0
gen_assertions[2].RstNOff_A	26849123	12631	0	0
gen_assertions[2].RstNOn_A	26849123	886	0	0
gen_assertions[3].RstEnOff_A	26849032	12740	0	0
gen_assertions[3].RstEnOn_A	26849032	968	0	0
gen_assertions[3].RstNOff_A	26849032	12740	0	0
gen_assertions[3].RstNOn_A	26849032	968	0	0
gen_assertions[4].RstEnOff_A	1694550	21584	0	0
gen_assertions[4].RstEnOn_A	1694550	990	0	0
gen_assertions[4].RstNOff_A	1694550	21584	0	0
gen_assertions[4].RstNOn_A	1694550	990	0	0
gen_assertions[5].RstEnOff_A	13424229	14125	0	0
gen_assertions[5].RstEnOn_A	13424229	1069	0	0
gen_assertions[5].RstNOff_A	13424229	14125	0	0
gen_assertions[5].RstNOn_A	13424229	1069	0	0
gen_assertions[6].RstEnOff_A	13424229	14154	0	0
gen_assertions[6].RstEnOn_A	13424229	1093	0	0
gen_assertions[6].RstNOff_A	13424229	14154	0	0
gen_assertions[6].RstNOn_A	13424229	1093	0	0
gen_assertions[7].RstEnOff_A	13424229	14200	0	0
gen_assertions[7].RstEnOn_A	13424229	1139	0	0
gen_assertions[7].RstNOff_A	13424229	14200	0	0
gen_assertions[7].RstNOn_A	13424229	1139	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	13885	0	0
T2	4709	5	0	0
T3	56605	75	0	0
T4	2859	4	0	0
T5	5846	0	0	0
T6	45070	75	0	0
T7	5842	0	0	0
T8	5821	0	0	0
T9	5977	4	0	0
T10	29245	75	0	0
T11	2229	0	0	0
T12	0	16	0	0
T13	0	209	0	0
T14	0	5	0	0
T15	0	5	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	979	0	0
T2	4709	1	0	0
T3	56605	0	0	0
T4	2859	0	0	0
T5	5846	0	0	0
T6	45070	0	0	0
T7	5842	0	0	0
T8	5821	0	0	0
T9	5977	0	0	0
T10	29245	0	0	0
T11	2229	0	0	0
T12	0	2	0	0
T13	0	18	0	0
T14	0	5	0	0
T15	0	1	0	0
T27	0	1	0	0
T51	0	8	0	0
T55	0	4	0	0
T56	0	3	0	0
T89	0	6	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	13885	0	0
T2	4709	5	0	0
T3	56605	75	0	0
T4	2859	4	0	0
T5	5846	0	0	0
T6	45070	75	0	0
T7	5842	0	0	0
T8	5821	0	0	0
T9	5977	4	0	0
T10	29245	75	0	0
T11	2229	0	0	0
T12	0	16	0	0
T13	0	209	0	0
T14	0	5	0	0
T15	0	5	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	979	0	0
T2	4709	1	0	0
T3	56605	0	0	0
T4	2859	0	0	0
T5	5846	0	0	0
T6	45070	0	0	0
T7	5842	0	0	0
T8	5821	0	0	0
T9	5977	0	0	0
T10	29245	0	0	0
T11	2229	0	0	0
T12	0	2	0	0
T13	0	18	0	0
T14	0	5	0	0
T15	0	1	0	0
T27	0	1	0	0
T51	0	8	0	0
T55	0	4	0	0
T56	0	3	0	0
T89	0	6	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53695677	12614	0	0
T2	18843	4	0	0
T3	226445	67	0	0
T4	11443	5	0	0
T5	23392	0	0	0
T6	180272	69	0	0
T7	23369	0	0	0
T8	23301	0	0	0
T9	23918	3	0	0
T10	116873	62	0	0
T11	8918	0	0	0
T12	0	14	0	0
T13	0	190	0	0
T14	0	9	0	0
T15	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53695677	945	0	0
T4	11443	1	0	0
T5	23392	0	0	0
T6	180272	0	0	0
T7	23369	0	0	0
T8	23301	0	0	0
T9	23918	1	0	0
T10	116873	0	0	0
T11	8918	0	0	0
T12	20137	0	0	0
T13	0	15	0	0
T14	0	9	0	0
T25	23391	0	0	0
T28	0	1	0	0
T41	0	12	0	0
T51	0	8	0	0
T55	0	6	0	0
T56	0	5	0	0
T89	0	4	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53695677	12614	0	0
T2	18843	4	0	0
T3	226445	67	0	0
T4	11443	5	0	0
T5	23392	0	0	0
T6	180272	69	0	0
T7	23369	0	0	0
T8	23301	0	0	0
T9	23918	3	0	0
T10	116873	62	0	0
T11	8918	0	0	0
T12	0	14	0	0
T13	0	190	0	0
T14	0	9	0	0
T15	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53695677	945	0	0
T4	11443	1	0	0
T5	23392	0	0	0
T6	180272	0	0	0
T7	23369	0	0	0
T8	23301	0	0	0
T9	23918	1	0	0
T10	116873	0	0	0
T11	8918	0	0	0
T12	20137	0	0	0
T13	0	15	0	0
T14	0	9	0	0
T25	23391	0	0	0
T28	0	1	0	0
T41	0	12	0	0
T51	0	8	0	0
T55	0	6	0	0
T56	0	5	0	0
T89	0	4	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26849123	12631	0	0
T2	9423	4	0	0
T3	113214	67	0	0
T4	5720	4	0	0
T5	11696	0	0	0
T6	90124	69	0	0
T7	11682	0	0	0
T8	11650	0	0	0
T9	11956	2	0	0
T10	58463	62	0	0
T11	4459	0	0	0
T12	0	14	0	0
T13	0	192	0	0
T14	0	9	0	0
T15	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26849123	886	0	0
T13	237659	18	0	0
T14	18350	9	0	0
T15	5801	0	0	0
T27	6500	0	0	0
T28	12452	1	0	0
T29	86732	0	0	0
T41	0	11	0	0
T44	0	5	0	0
T45	0	5	0	0
T51	465591	5	0	0
T55	15326	4	0	0
T56	0	5	0	0
T89	5456	0	0	0
T90	0	8	0	0
T91	58625	0	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26849123	12631	0	0
T2	9423	4	0	0
T3	113214	67	0	0
T4	5720	4	0	0
T5	11696	0	0	0
T6	90124	69	0	0
T7	11682	0	0	0
T8	11650	0	0	0
T9	11956	2	0	0
T10	58463	62	0	0
T11	4459	0	0	0
T12	0	14	0	0
T13	0	192	0	0
T14	0	9	0	0
T15	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26849123	886	0	0
T13	237659	18	0	0
T14	18350	9	0	0
T15	5801	0	0	0
T27	6500	0	0	0
T28	12452	1	0	0
T29	86732	0	0	0
T41	0	11	0	0
T44	0	5	0	0
T45	0	5	0	0
T51	465591	5	0	0
T55	15326	4	0	0
T56	0	5	0	0
T89	5456	0	0	0
T90	0	8	0	0
T91	58625	0	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26849032	12740	0	0
T2	9421	4	0	0
T3	113227	67	0	0
T4	5722	5	0	0
T5	11704	0	0	0
T6	90143	69	0	0
T7	11681	0	0	0
T8	11653	0	0	0
T9	11956	3	0	0
T10	58440	62	0	0
T11	4459	0	0	0
T12	0	14	0	0
T13	0	193	0	0
T14	0	11	0	0
T15	0	5	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26849032	968	0	0
T4	5722	1	0	0
T5	11704	0	0	0
T6	90143	0	0	0
T7	11681	0	0	0
T8	11653	0	0	0
T9	11956	1	0	0
T10	58440	0	0	0
T11	4459	0	0	0
T12	10070	0	0	0
T13	0	19	0	0
T14	0	11	0	0
T15	0	1	0	0
T25	11690	0	0	0
T28	0	1	0	0
T41	0	13	0	0
T51	0	7	0	0
T55	0	8	0	0
T56	0	6	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26849032	12740	0	0
T2	9421	4	0	0
T3	113227	67	0	0
T4	5722	5	0	0
T5	11704	0	0	0
T6	90143	69	0	0
T7	11681	0	0	0
T8	11653	0	0	0
T9	11956	3	0	0
T10	58440	62	0	0
T11	4459	0	0	0
T12	0	14	0	0
T13	0	193	0	0
T14	0	11	0	0
T15	0	5	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26849032	968	0	0
T4	5722	1	0	0
T5	11704	0	0	0
T6	90143	0	0	0
T7	11681	0	0	0
T8	11653	0	0	0
T9	11956	1	0	0
T10	58440	0	0	0
T11	4459	0	0	0
T12	10070	0	0	0
T13	0	19	0	0
T14	0	11	0	0
T15	0	1	0	0
T25	11690	0	0	0
T28	0	1	0	0
T41	0	13	0	0
T51	0	7	0	0
T55	0	8	0	0
T56	0	6	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1694550	21584	0	0
T1	214	1	0	0
T2	587	6	0	0
T3	7090	94	0	0
T4	356	6	0	0
T5	733	3	0	0
T6	5647	91	0	0
T7	733	3	0	0
T8	730	3	0	0
T9	747	6	0	0
T10	3668	74	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1694550	990	0	0
T13	15155	24	0	0
T14	1146	11	0	0
T15	362	0	0	0
T27	405	0	0	0
T28	776	0	0	0
T29	5470	0	0	0
T41	0	12	0	0
T44	0	8	0	0
T45	0	7	0	0
T51	29494	6	0	0
T55	957	8	0	0
T56	0	7	0	0
T89	340	0	0	0
T90	0	11	0	0
T91	3678	0	0	0
T92	0	5	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1694550	21584	0	0
T1	214	1	0	0
T2	587	6	0	0
T3	7090	94	0	0
T4	356	6	0	0
T5	733	3	0	0
T6	5647	91	0	0
T7	733	3	0	0
T8	730	3	0	0
T9	747	6	0	0
T10	3668	74	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1694550	990	0	0
T13	15155	24	0	0
T14	1146	11	0	0
T15	362	0	0	0
T27	405	0	0	0
T28	776	0	0	0
T29	5470	0	0	0
T41	0	12	0	0
T44	0	8	0	0
T45	0	7	0	0
T51	29494	6	0	0
T55	957	8	0	0
T56	0	7	0	0
T89	340	0	0	0
T90	0	11	0	0
T91	3678	0	0	0
T92	0	5	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	14125	0	0
T2	4709	5	0	0
T3	56605	75	0	0
T4	2859	4	0	0
T5	5846	0	0	0
T6	45070	75	0	0
T7	5842	0	0	0
T8	5821	0	0	0
T9	5977	4	0	0
T10	29245	75	0	0
T11	2229	0	0	0
T12	0	16	0	0
T13	0	212	0	0
T14	0	11	0	0
T15	0	5	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	1069	0	0
T2	4709	1	0	0
T3	56605	0	0	0
T4	2859	0	0	0
T5	5846	0	0	0
T6	45070	0	0	0
T7	5842	0	0	0
T8	5821	0	0	0
T9	5977	0	0	0
T10	29245	0	0	0
T11	2229	0	0	0
T13	0	22	0	0
T14	0	11	0	0
T15	0	1	0	0
T40	0	1	0	0
T41	0	12	0	0
T44	0	6	0	0
T51	0	6	0	0
T55	0	11	0	0
T56	0	7	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	14125	0	0
T2	4709	5	0	0
T3	56605	75	0	0
T4	2859	4	0	0
T5	5846	0	0	0
T6	45070	75	0	0
T7	5842	0	0	0
T8	5821	0	0	0
T9	5977	4	0	0
T10	29245	75	0	0
T11	2229	0	0	0
T12	0	16	0	0
T13	0	212	0	0
T14	0	11	0	0
T15	0	5	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	1069	0	0
T2	4709	1	0	0
T3	56605	0	0	0
T4	2859	0	0	0
T5	5846	0	0	0
T6	45070	0	0	0
T7	5842	0	0	0
T8	5821	0	0	0
T9	5977	0	0	0
T10	29245	0	0	0
T11	2229	0	0	0
T13	0	22	0	0
T14	0	11	0	0
T15	0	1	0	0
T40	0	1	0	0
T41	0	12	0	0
T44	0	6	0	0
T51	0	6	0	0
T55	0	11	0	0
T56	0	7	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	14154	0	0
T2	4709	4	0	0
T3	56605	75	0	0
T4	2859	4	0	0
T5	5846	0	0	0
T6	45070	75	0	0
T7	5842	0	0	0
T8	5821	0	0	0
T9	5977	4	0	0
T10	29245	75	0	0
T11	2229	0	0	0
T12	0	16	0	0
T13	0	208	0	0
T14	0	12	0	0
T15	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	1093	0	0
T13	118842	19	0	0
T14	9173	12	0	0
T15	2901	0	0	0
T27	3249	0	0	0
T28	6225	0	0	0
T29	43371	0	0	0
T41	0	8	0	0
T44	0	8	0	0
T45	0	7	0	0
T51	232785	6	0	0
T55	7662	10	0	0
T56	0	10	0	0
T89	2728	0	0	0
T90	0	12	0	0
T91	29305	0	0	0
T92	0	2	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	14154	0	0
T2	4709	4	0	0
T3	56605	75	0	0
T4	2859	4	0	0
T5	5846	0	0	0
T6	45070	75	0	0
T7	5842	0	0	0
T8	5821	0	0	0
T9	5977	4	0	0
T10	29245	75	0	0
T11	2229	0	0	0
T12	0	16	0	0
T13	0	208	0	0
T14	0	12	0	0
T15	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	1093	0	0
T13	118842	19	0	0
T14	9173	12	0	0
T15	2901	0	0	0
T27	3249	0	0	0
T28	6225	0	0	0
T29	43371	0	0	0
T41	0	8	0	0
T44	0	8	0	0
T45	0	7	0	0
T51	232785	6	0	0
T55	7662	10	0	0
T56	0	10	0	0
T89	2728	0	0	0
T90	0	12	0	0
T91	29305	0	0	0
T92	0	2	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	14200	0	0
T2	4709	5	0	0
T3	56605	75	0	0
T4	2859	5	0	0
T5	5846	0	0	0
T6	45070	75	0	0
T7	5842	0	0	0
T8	5821	0	0	0
T9	5977	4	0	0
T10	29245	75	0	0
T11	2229	0	0	0
T12	0	16	0	0
T13	0	208	0	0
T14	0	14	0	0
T15	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	1139	0	0
T2	4709	1	0	0
T3	56605	0	0	0
T4	2859	1	0	0
T5	5846	0	0	0
T6	45070	0	0	0
T7	5842	0	0	0
T8	5821	0	0	0
T9	5977	0	0	0
T10	29245	0	0	0
T11	2229	0	0	0
T13	0	19	0	0
T14	0	14	0	0
T28	0	1	0	0
T41	0	15	0	0
T44	0	4	0	0
T51	0	6	0	0
T55	0	11	0	0
T56	0	10	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	14200	0	0
T2	4709	5	0	0
T3	56605	75	0	0
T4	2859	5	0	0
T5	5846	0	0	0
T6	45070	75	0	0
T7	5842	0	0	0
T8	5821	0	0	0
T9	5977	4	0	0
T10	29245	75	0	0
T11	2229	0	0	0
T12	0	16	0	0
T13	0	208	0	0
T14	0	14	0	0
T15	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	1139	0	0
T2	4709	1	0	0
T3	56605	0	0	0
T4	2859	1	0	0
T5	5846	0	0	0
T6	45070	0	0	0
T7	5842	0	0	0
T8	5821	0	0	0
T9	5977	0	0	0
T10	29245	0	0	0
T11	2229	0	0	0
T13	0	19	0	0
T14	0	14	0	0
T28	0	1	0	0
T41	0	15	0	0
T44	0	4	0	0
T51	0	6	0	0
T55	0	11	0	0
T56	0	10	0	0