Unified Coverage Report :: Module :: prim_mubi4_sender

Module : prim_mubi4_sender

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_daon_por.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_por_io.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_por_usb.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_io.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_io.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_sys.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_spi_device.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_usb.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_i2c0.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_i2c1.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.u_d0_i2c2.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender	100.00	100.00					100.00
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender	100.00	100.00					100.00

---

Module Instance : tb.dut.u_daon_por.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_daon_lc_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_d0_lc_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_daon_lc_io_div4_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							u_d0_lc_io_div4_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_sys

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_sys_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_device

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_host0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_host1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_d0_usb_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_flops.u_prim_flop	100.00	100.00				100.00

Line Coverage for Module : prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Module : prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	906205698	501190766	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	906205698	501190766	0	0
T1	115990	72100	0	0
T2	317948	239903	0	0
T3	3821096	2492308	0	0
T4	193068	115263	0	0
T5	394786	42054	0	0
T6	3041998	1725362	0	0
T7	394302	41928	0	0
T8	393220	41856	0	0
T9	403544	325645	0	0
T10	1972798	650278	0	0

Line Coverage for Instance : tb.dut.u_daon_por.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_por.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	55934980	34454374	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55934980	34454374	0	0
T1	7162	4492	0	0
T2	19627	15402	0	0
T3	235857	163660	0	0
T4	11919	7703	0	0
T5	24371	2928	0	0
T6	187759	115649	0	0
T7	24337	2930	0	0
T8	24279	2925	0	0
T9	24911	20735	0	0
T10	121762	49483	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_por_io.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	53695677	33074925	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53695677	33074925	0	0
T1	6876	4312	0	0
T2	18843	14787	0	0
T3	226445	157072	0	0
T4	11443	7395	0	0
T5	23392	2811	0	0
T6	180272	110957	0	0
T7	23369	2812	0	0
T8	23301	2808	0	0
T9	23918	19910	0	0
T10	116873	47496	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	26849123	16533791	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26849123	16533791	0	0
T1	3436	2155	0	0
T2	9423	7394	0	0
T3	113214	78527	0	0
T4	5720	3696	0	0
T5	11696	1404	0	0
T6	90124	55461	0	0
T7	11682	1405	0	0
T8	11650	1400	0	0
T9	11956	9951	0	0
T10	58463	23741	0	0

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	13424229	8264145	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	8264145	0	0
T1	1717	1077	0	0
T2	4709	3694	0	0
T3	56605	39238	0	0
T4	2859	1848	0	0
T5	5846	694	0	0
T6	45070	27752	0	0
T7	5842	694	0	0
T8	5821	690	0	0
T9	5977	4975	0	0
T10	29245	11849	0	0

Line Coverage for Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_por_usb.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	26849032	16533572	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26849032	16533572	0	0
T1	3436	2155	0	0
T2	9421	7392	0	0
T3	113227	78535	0	0
T4	5722	3698	0	0
T5	11704	1404	0	0
T6	90143	55497	0	0
T7	11681	1405	0	0
T8	11653	1400	0	0
T9	11956	9951	0	0
T10	58440	23699	0	0

Line Coverage for Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	55934980	30719194	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55934980	30719194	0	0
T1	7162	4485	0	0
T2	19627	14803	0	0
T3	235857	153285	0	0
T4	11919	7108	0	0
T5	24371	2836	0	0
T6	187759	106138	0	0
T7	24337	2822	0	0
T8	24279	2823	0	0
T9	24911	20129	0	0
T10	121762	39716	0	0

Line Coverage for Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	55934980	29996900	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55934980	29996900	0	0
T1	7162	4419	0	0
T2	19627	14635	0	0
T3	235857	150861	0	0
T4	11919	6940	0	0
T5	24371	2344	0	0
T6	187759	103714	0	0
T7	24337	2333	0	0
T8	24279	2332	0	0
T9	24911	19961	0	0
T10	121762	37226	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	55934980	30719428	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55934980	30719428	0	0
T1	7162	4485	0	0
T2	19627	14803	0	0
T3	235857	153339	0	0
T4	11919	7108	0	0
T5	24371	2836	0	0
T6	187759	106088	0	0
T7	24337	2821	0	0
T8	24279	2823	0	0
T9	24911	20129	0	0
T10	121762	39666	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	55934980	29998196	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55934980	29998196	0	0
T1	7162	4419	0	0
T2	19627	14635	0	0
T3	235857	150911	0	0
T4	11919	6940	0	0
T5	24371	2344	0	0
T6	187759	103714	0	0
T7	24337	2333	0	0
T8	24279	2332	0	0
T9	24911	19961	0	0
T10	121762	37297	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_aon.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	1694550	912008	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1694550	912008	0	0
T1	214	133	0	0
T2	587	440	0	0
T3	7090	4496	0	0
T4	356	204	0	0
T5	733	75	0	0
T6	5647	3084	0	0
T7	733	75	0	0
T8	730	74	0	0
T9	747	598	0	0
T10	3668	1088	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	53695677	29490915	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53695677	29490915	0	0
T1	6876	4305	0	0
T2	18843	14211	0	0
T3	226445	147152	0	0
T4	11443	6823	0	0
T5	23392	2761	0	0
T6	180272	101845	0	0
T7	23369	2752	0	0
T8	23301	2751	0	0
T9	23918	19328	0	0
T10	116873	38058	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	53695677	28795314	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53695677	28795314	0	0
T1	6876	4241	0	0
T2	18843	14051	0	0
T3	226445	144816	0	0
T4	11443	6663	0	0
T5	23392	2249	0	0
T6	180272	99561	0	0
T7	23369	2240	0	0
T8	23301	2239	0	0
T9	23918	19168	0	0
T10	116873	35742	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	26849123	14735285	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26849123	14735285	0	0
T1	3436	2152	0	0
T2	9423	7104	0	0
T3	113214	73535	0	0
T4	5720	3408	0	0
T5	11696	1380	0	0
T6	90124	50859	0	0
T7	11682	1373	0	0
T8	11650	1372	0	0
T9	11956	9659	0	0
T10	58463	18983	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	26849123	14387700	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26849123	14387700	0	0
T1	3436	2120	0	0
T2	9423	7024	0	0
T3	113214	72367	0	0
T4	5720	3328	0	0
T5	11696	1124	0	0
T6	90124	49727	0	0
T7	11682	1117	0	0
T8	11650	1116	0	0
T9	11956	9579	0	0
T10	58463	17825	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	13424229	7340601	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	7340601	0	0
T1	1717	1075	0	0
T2	4709	3543	0	0
T3	56605	36625	0	0
T4	2859	1697	0	0
T5	5846	668	0	0
T6	45070	25323	0	0
T7	5842	668	0	0
T8	5821	664	0	0
T9	5977	4822	0	0
T10	29245	9376	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	13424229	7166665	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	7166665	0	0
T1	1717	1059	0	0
T2	4709	3503	0	0
T3	56605	36043	0	0
T4	2859	1657	0	0
T5	5846	540	0	0
T6	45070	24741	0	0
T7	5842	540	0	0
T8	5821	536	0	0
T9	5977	4782	0	0
T10	29245	8794	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	13424229	7340601	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	7340601	0	0
T1	1717	1075	0	0
T2	4709	3543	0	0
T3	56605	36625	0	0
T4	2859	1697	0	0
T5	5846	668	0	0
T6	45070	25323	0	0
T7	5842	668	0	0
T8	5821	664	0	0
T9	5977	4822	0	0
T10	29245	9376	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	13424229	7166665	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	7166665	0	0
T1	1717	1059	0	0
T2	4709	3503	0	0
T3	56605	36043	0	0
T4	2859	1657	0	0
T5	5846	540	0	0
T6	45070	24741	0	0
T7	5842	540	0	0
T8	5821	536	0	0
T9	5977	4782	0	0
T10	29245	8794	0	0

Line Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_lc_usb.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	26849032	14735330	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26849032	14735330	0	0
T1	3436	2152	0	0
T2	9421	7102	0	0
T3	113227	73537	0	0
T4	5722	3410	0	0
T5	11704	1380	0	0
T6	90143	50898	0	0
T7	11681	1373	0	0
T8	11653	1372	0	0
T9	11956	9659	0	0
T10	58440	18973	0	0

Line Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_lc_usb.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	26849032	14387413	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26849032	14387413	0	0
T1	3436	2120	0	0
T2	9421	7022	0	0
T3	113227	72375	0	0
T4	5722	3330	0	0
T5	11704	1124	0	0
T6	90143	49734	0	0
T7	11681	1117	0	0
T8	11653	1116	0	0
T9	11956	9579	0	0
T10	58440	17837	0	0

Line Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_sys.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	55934980	29695827	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55934980	29695827	0	0
T1	7162	4419	0	0
T2	19627	14547	0	0
T3	235857	149104	0	0
T4	11919	6857	0	0
T5	24371	2344	0	0
T6	187759	101829	0	0
T7	24337	2333	0	0
T8	24279	2332	0	0
T9	24911	19927	0	0
T10	121762	35750	0	0

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	13424229	7268477	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	7268477	0	0
T1	1717	1075	0	0
T2	4709	3522	0	0
T3	56605	36175	0	0
T4	2859	1677	0	0
T5	5846	678	0	0
T6	45070	24871	0	0
T7	5842	678	0	0
T8	5821	674	0	0
T9	5977	4814	0	0
T10	29245	9005	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_spi_device.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	13424229	7021237	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	7021237	0	0
T1	1717	1059	0	0
T2	4709	3396	0	0
T3	56605	36031	0	0
T4	2859	1657	0	0
T5	5846	550	0	0
T6	45070	24741	0	0
T7	5842	550	0	0
T8	5821	546	0	0
T9	5977	4782	0	0
T10	29245	8780	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host0.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	53695677	28194000	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53695677	28194000	0	0
T1	6876	4241	0	0
T2	18843	14051	0	0
T3	226445	144876	0	0
T4	11443	6543	0	0
T5	23392	2249	0	0
T6	180272	99561	0	0
T7	23369	2240	0	0
T8	23301	2239	0	0
T9	23918	18559	0	0
T10	116873	35746	0	0

Line Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_spi_host1.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	26849123	14113044	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26849123	14113044	0	0
T1	3436	2120	0	0
T2	9423	7024	0	0
T3	113214	72357	0	0
T4	5720	3328	0	0
T5	11696	1124	0	0
T6	90124	49703	0	0
T7	11682	1117	0	0
T8	11650	1116	0	0
T9	11956	9579	0	0
T10	58463	17829	0	0

Line Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_usb.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	26849032	14107010	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26849032	14107010	0	0
T1	3436	2120	0	0
T2	9421	7022	0	0
T3	113227	72377	0	0
T4	5722	3278	0	0
T5	11704	1124	0	0
T6	90143	49702	0	0
T7	11681	1117	0	0
T8	11653	1116	0	0
T9	11956	9324	0	0
T10	58440	17837	0	0

Line Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_usb_aon.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	1694550	872880	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1694550	872880	0	0
T1	214	131	0	0
T2	587	434	0	0
T3	7090	4423	0	0
T4	356	200	0	0
T5	733	59	0	0
T6	5647	3010	0	0
T7	733	59	0	0
T8	730	58	0	0
T9	747	592	0	0
T10	3668	1015	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_i2c0.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	13424229	7017463	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	7017463	0	0
T1	1717	1059	0	0
T2	4709	3442	0	0
T3	56605	36043	0	0
T4	2859	1657	0	0
T5	5846	550	0	0
T6	45070	24729	0	0
T7	5842	550	0	0
T8	5821	546	0	0
T9	5977	4782	0	0
T10	29245	8777	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_i2c1.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	13424229	7030850	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	7030850	0	0
T1	1717	1059	0	0
T2	4709	3503	0	0
T3	56605	36033	0	0
T4	2859	1657	0	0
T5	5846	550	0	0
T6	45070	24741	0	0
T7	5842	550	0	0
T8	5821	546	0	0
T9	5977	4782	0	0
T10	29245	8779	0	0

Line Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.u_d0_i2c2.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	13424229	7029929	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13424229	7029929	0	0
T1	1717	1059	0	0
T2	4709	3447	0	0
T3	56605	36043	0	0
T4	2859	1639	0	0
T5	5846	550	0	0
T6	45070	24741	0	0
T7	5842	550	0	0
T8	5821	546	0	0
T9	5977	4782	0	0
T10	29245	8783	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	1694550	1052747	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1694550	1052747	0	0
T1	214	135	0	0
T2	587	464	0	0
T3	7090	4929	0	0
T4	356	232	0	0
T5	733	91	0	0
T6	5647	3491	0	0
T7	733	91	0	0
T8	730	90	0	0
T9	747	623	0	0
T10	3668	1506	0	0

Line Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	34	0	0
CONT_ASSIGN	82	1	1	100.00
CONT_ASSIGN	85	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sender.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
34		unreachable
82	1	1
85	1	1

---

Assert Coverage for Instance : tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OutputsKnown_A	1694550	1034280	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1694550	1034280	0	0
T1	214	133	0	0
T2	587	460	0	0
T3	7090	4875	0	0
T4	356	228	0	0
T5	733	75	0	0
T6	5647	3437	0	0
T7	733	75	0	0
T8	730	74	0	0
T9	747	619	0	0
T10	3668	1452	0	0