Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12615711	7679	0	0
alert_regwen_rd_A	12615711	5858	0	0
cpu_regwen_rd_A	12615711	5932	0	0
sw_rst_ctrl_n_0_rd_A	12615711	12181	0	0
sw_rst_ctrl_n_1_rd_A	12615711	11953	0	0
sw_rst_ctrl_n_2_rd_A	12615711	12010	0	0
sw_rst_ctrl_n_3_rd_A	12615711	12346	0	0
sw_rst_ctrl_n_4_rd_A	12615711	12142	0	0
sw_rst_ctrl_n_5_rd_A	12615711	11996	0	0
sw_rst_ctrl_n_6_rd_A	12615711	11928	0	0
sw_rst_ctrl_n_7_rd_A	12615711	12440	0	0
sw_rst_regwen_0_rd_A	12615711	6498	0	0
sw_rst_regwen_1_rd_A	12615711	6461	0	0
sw_rst_regwen_2_rd_A	12615711	6243	0	0
sw_rst_regwen_3_rd_A	12615711	6219	0	0
sw_rst_regwen_4_rd_A	12615711	6529	0	0
sw_rst_regwen_5_rd_A	12615711	6319	0	0
sw_rst_regwen_6_rd_A	12615711	6396	0	0
sw_rst_regwen_7_rd_A	12615711	6592	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12615711	7679	0	0
T59	12076	3	0	0
T60	2986	14	0	0
T61	2822	42	0	0
T62	6697	409	0	0
T63	20637	2	0	0
T76	9636	177	0	0
T78	11847	735	0	0
T79	4038	126	0	0
T80	4648	24	0	0
T93	3570	40	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12615711	5858	0	0
T16	4287	0	0	0
T29	38163	21	0	0
T30	53343	0	0	0
T40	5854	0	0	0
T41	254430	380	0	0
T51	206244	212	0	0
T55	7644	0	0	0
T56	9037	0	0	0
T89	2179	0	0	0
T91	25963	0	0	0
T92	0	104	0	0
T95	0	77	0	0
T96	0	17	0	0
T99	0	156	0	0
T113	0	196	0	0
T114	0	115	0	0
T115	0	165	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12615711	5932	0	0
T16	4287	0	0	0
T29	38163	23	0	0
T30	53343	0	0	0
T40	5854	0	0	0
T41	254430	369	0	0
T51	206244	162	0	0
T55	7644	0	0	0
T56	9037	0	0	0
T89	2179	0	0	0
T91	25963	0	0	0
T92	0	82	0	0
T95	0	61	0	0
T96	0	16	0	0
T99	0	229	0	0
T113	0	181	0	0
T114	0	161	0	0
T115	0	152	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12615711	12181	0	0
T9	5734	10	0	0
T10	26101	0	0	0
T11	2186	0	0	0
T12	4001	0	0	0
T13	95554	0	0	0
T14	9083	0	0	0
T15	2708	0	0	0
T25	5302	0	0	0
T26	5286	0	0	0
T27	2777	15	0	0
T28	0	10	0	0
T29	0	26	0	0
T40	0	16	0	0
T41	0	467	0	0
T51	0	217	0	0
T56	0	78	0	0
T92	0	164	0	0
T95	0	71	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12615711	11953	0	0
T9	5734	13	0	0
T10	26101	0	0	0
T11	2186	0	0	0
T12	4001	0	0	0
T13	95554	0	0	0
T14	9083	0	0	0
T15	2708	0	0	0
T25	5302	0	0	0
T26	5286	0	0	0
T27	2777	31	0	0
T28	0	13	0	0
T29	0	29	0	0
T40	0	12	0	0
T41	0	484	0	0
T51	0	214	0	0
T56	0	88	0	0
T92	0	176	0	0
T95	0	69	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12615711	12010	0	0
T9	5734	11	0	0
T10	26101	0	0	0
T11	2186	0	0	0
T12	4001	0	0	0
T13	95554	0	0	0
T14	9083	0	0	0
T15	2708	0	0	0
T25	5302	0	0	0
T26	5286	0	0	0
T27	2777	23	0	0
T28	0	14	0	0
T29	0	39	0	0
T40	0	15	0	0
T41	0	514	0	0
T51	0	263	0	0
T56	0	90	0	0
T92	0	118	0	0
T95	0	52	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12615711	12346	0	0
T9	5734	15	0	0
T10	26101	0	0	0
T11	2186	0	0	0
T12	4001	0	0	0
T13	95554	0	0	0
T14	9083	0	0	0
T15	2708	0	0	0
T25	5302	0	0	0
T26	5286	0	0	0
T27	2777	3	0	0
T28	0	12	0	0
T29	0	36	0	0
T40	0	15	0	0
T41	0	520	0	0
T51	0	234	0	0
T56	0	95	0	0
T92	0	136	0	0
T95	0	52	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12615711	12142	0	0
T9	5734	13	0	0
T10	26101	0	0	0
T11	2186	0	0	0
T12	4001	0	0	0
T13	95554	0	0	0
T14	9083	0	0	0
T15	2708	0	0	0
T25	5302	0	0	0
T26	5286	0	0	0
T27	2777	14	0	0
T28	0	20	0	0
T29	0	41	0	0
T40	0	8	0	0
T41	0	507	0	0
T51	0	195	0	0
T56	0	83	0	0
T92	0	180	0	0
T95	0	59	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12615711	11996	0	0
T9	5734	7	0	0
T10	26101	0	0	0
T11	2186	0	0	0
T12	4001	0	0	0
T13	95554	0	0	0
T14	9083	0	0	0
T15	2708	0	0	0
T25	5302	0	0	0
T26	5286	0	0	0
T27	2777	2	0	0
T28	0	21	0	0
T29	0	37	0	0
T40	0	12	0	0
T41	0	523	0	0
T51	0	185	0	0
T56	0	81	0	0
T92	0	155	0	0
T95	0	55	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12615711	11928	0	0
T9	5734	23	0	0
T10	26101	0	0	0
T11	2186	0	0	0
T12	4001	0	0	0
T13	95554	0	0	0
T14	9083	0	0	0
T15	2708	0	0	0
T25	5302	0	0	0
T26	5286	0	0	0
T27	2777	15	0	0
T28	0	14	0	0
T29	0	49	0	0
T40	0	15	0	0
T41	0	534	0	0
T51	0	227	0	0
T56	0	98	0	0
T92	0	139	0	0
T95	0	57	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12615711	12440	0	0
T9	5734	10	0	0
T10	26101	0	0	0
T11	2186	0	0	0
T12	4001	0	0	0
T13	95554	0	0	0
T14	9083	0	0	0
T15	2708	0	0	0
T25	5302	0	0	0
T26	5286	0	0	0
T27	2777	20	0	0
T28	0	15	0	0
T29	0	53	0	0
T40	0	11	0	0
T41	0	530	0	0
T51	0	188	0	0
T56	0	93	0	0
T92	0	127	0	0
T95	0	61	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12615711	6498	0	0
T9	5734	11	0	0
T10	26101	0	0	0
T11	2186	0	0	0
T12	4001	0	0	0
T13	95554	0	0	0
T14	9083	0	0	0
T15	2708	0	0	0
T25	5302	0	0	0
T26	5286	0	0	0
T27	2777	0	0	0
T28	0	4	0	0
T29	0	50	0	0
T40	0	13	0	0
T41	0	389	0	0
T51	0	196	0	0
T56	0	17	0	0
T92	0	77	0	0
T95	0	61	0	0
T116	0	25	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12615711	6461	0	0
T9	5734	4	0	0
T10	26101	0	0	0
T11	2186	0	0	0
T12	4001	0	0	0
T13	95554	0	0	0
T14	9083	0	0	0
T15	2708	0	0	0
T25	5302	0	0	0
T26	5286	0	0	0
T27	2777	0	0	0
T28	0	9	0	0
T29	0	42	0	0
T40	0	8	0	0
T41	0	333	0	0
T51	0	201	0	0
T56	0	32	0	0
T92	0	82	0	0
T95	0	57	0	0
T116	0	56	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12615711	6243	0	0
T9	5734	15	0	0
T10	26101	0	0	0
T11	2186	0	0	0
T12	4001	0	0	0
T13	95554	0	0	0
T14	9083	0	0	0
T15	2708	0	0	0
T25	5302	0	0	0
T26	5286	0	0	0
T27	2777	0	0	0
T28	0	10	0	0
T29	0	47	0	0
T40	0	2	0	0
T41	0	325	0	0
T51	0	178	0	0
T56	0	9	0	0
T92	0	66	0	0
T95	0	65	0	0
T116	0	36	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12615711	6219	0	0
T9	5734	13	0	0
T10	26101	0	0	0
T11	2186	0	0	0
T12	4001	0	0	0
T13	95554	0	0	0
T14	9083	0	0	0
T15	2708	0	0	0
T25	5302	0	0	0
T26	5286	0	0	0
T27	2777	0	0	0
T28	0	4	0	0
T29	0	32	0	0
T40	0	13	0	0
T41	0	345	0	0
T51	0	145	0	0
T56	0	12	0	0
T92	0	75	0	0
T95	0	58	0	0
T116	0	37	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12615711	6529	0	0
T9	5734	6	0	0
T10	26101	0	0	0
T11	2186	0	0	0
T12	4001	0	0	0
T13	95554	0	0	0
T14	9083	0	0	0
T15	2708	0	0	0
T25	5302	0	0	0
T26	5286	0	0	0
T27	2777	0	0	0
T29	0	19	0	0
T40	0	4	0	0
T41	0	357	0	0
T51	0	163	0	0
T56	0	9	0	0
T92	0	69	0	0
T95	0	78	0	0
T96	0	47	0	0
T116	0	31	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12615711	6319	0	0
T9	5734	3	0	0
T10	26101	0	0	0
T11	2186	0	0	0
T12	4001	0	0	0
T13	95554	0	0	0
T14	9083	0	0	0
T15	2708	0	0	0
T25	5302	0	0	0
T26	5286	0	0	0
T27	2777	0	0	0
T28	0	13	0	0
T29	0	49	0	0
T40	0	6	0	0
T41	0	397	0	0
T51	0	212	0	0
T56	0	11	0	0
T92	0	108	0	0
T95	0	62	0	0
T116	0	28	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12615711	6396	0	0
T9	5734	4	0	0
T10	26101	0	0	0
T11	2186	0	0	0
T12	4001	0	0	0
T13	95554	0	0	0
T14	9083	0	0	0
T15	2708	0	0	0
T25	5302	0	0	0
T26	5286	0	0	0
T27	2777	0	0	0
T28	0	3	0	0
T29	0	59	0	0
T40	0	13	0	0
T41	0	275	0	0
T51	0	187	0	0
T56	0	12	0	0
T92	0	64	0	0
T95	0	46	0	0
T116	0	30	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12615711	6592	0	0
T9	5734	8	0	0
T10	26101	0	0	0
T11	2186	0	0	0
T12	4001	0	0	0
T13	95554	0	0	0
T14	9083	0	0	0
T15	2708	0	0	0
T25	5302	0	0	0
T26	5286	0	0	0
T27	2777	0	0	0
T28	0	6	0	0
T29	0	39	0	0
T40	0	7	0	0
T41	0	344	0	0
T51	0	178	0	0
T56	0	18	0	0
T92	0	81	0	0
T95	0	52	0	0
T116	0	21	0	0