Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

Group : rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

---

Summary for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable_cp	2	0	2	100.00	100	1	1	2
reset_info_cp	8	0	8	100.00	100	1	1	0

Crosses for Group rstmgr_env_pkg::rstmgr_env_cov::cpu_info_capture_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
capture_cross	16	0	16	100.00	100	1	1	0

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7803

1

T1

6

T2

11

T6

16

auto[1]

10636

1

T1

1

T2

90

T6

85

---

Summary for Variable reset_info_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	8	0	8	100.00

User Defined Bins for reset_info_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
others	5706	Excluded

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	6197	1			T1	1		T2	27		T3	1
reset_info_cp[2]	2932	1			T2	18		T6	20		T9	9
reset_info_cp[4]	3722	1			T2	22		T6	15		T9	12
reset_info_cp[8]	108	1			T8	1		T9	1		T11	2
reset_info_cp[16]	99	1			T8	1		T9	1		T38	2
reset_info_cp[32]	105	1			T6	1		T38	3		T67	1
reset_info_cp[64]	84	1			T10	1		T11	1		T67	1
reset_info_cp[128]	105	1			T6	1		T11	3		T37	1

---

Summary for Cross capture_cross

Samples crossed: reset_info_cp enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for capture_cross

Bins

reset_info_cp	enable_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
reset_info_cp[1]	auto[0]	2959	1			T2	11		T6	16		T9	7
reset_info_cp[1]	auto[1]	2619	1			T2	15		T6	10		T9	9
reset_info_cp[2]	auto[0]	931	1			T9	4		T11	28		T37	3
reset_info_cp[2]	auto[1]	2001	1			T2	18		T6	20		T9	5
reset_info_cp[4]	auto[0]	1318	1			T9	7		T11	48		T37	5
reset_info_cp[4]	auto[1]	2404	1			T2	22		T6	15		T9	5
reset_info_cp[8]	auto[0]	40	1			T8	1		T11	2		T73	1
reset_info_cp[8]	auto[1]	68	1			T9	1		T37	1		T38	1
reset_info_cp[16]	auto[0]	45	1			T8	1		T70	1		T66	1
reset_info_cp[16]	auto[1]	54	1			T9	1		T38	2		T70	1
reset_info_cp[32]	auto[0]	44	1			T38	2		T67	1		T73	1
reset_info_cp[32]	auto[1]	61	1			T6	1		T38	1		T32	2
reset_info_cp[64]	auto[0]	32	1			T87	1		T124	1		T126	1
reset_info_cp[64]	auto[1]	52	1			T10	1		T11	1		T67	1
reset_info_cp[128]	auto[0]	48	1			T11	2		T88	1		T124	1
reset_info_cp[128]	auto[1]	57	1			T6	1		T11	1		T37	1