---

Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonActive_A	0	0	1583728	0	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorInactive_A	0	0	52245747	0	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Active_A	0	0	12538562	0	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoInactive_A	0	0	50154887	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AlertsKnownO_A	0	0	11125207	6248275	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	11125207	90	0	0
tb.dut.ParameterMatch_A	0	0	504	504	0	0
tb.dut.PwrKnownO_A	0	0	11125207	6248275	0	0
tb.dut.ResetsKnownO_A	0	0	11125207	6248275	0	0
tb.dut.RstEnKnownO_A	0	0	11125207	6248275	0	0
tb.dut.TlAReadyKnownO_A	0	0	11125207	6248275	0	0
tb.dut.TlDValidKnownO_A	0	0	11125207	6248275	0	0
tb.dut.gen_d0_i2c0_assert.FpvSecCmD0I2c0FsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_d0_i2c1_assert.FpvSecCmD0I2c1FsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_d0_i2c2_assert.FpvSecCmD0I2c2FsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_d0_lc_assert.FpvSecCmD0LcFsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_d0_lc_io_assert.FpvSecCmD0LcIoFsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_d0_lc_io_div2_assert.FpvSecCmD0LcIoDiv2FsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_d0_lc_shadowed_assert.FpvSecCmD0LcShadowedFsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_d0_lc_usb_assert.FpvSecCmD0LcUsbFsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_d0_spi_device_assert.FpvSecCmD0SpiDeviceFsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_d0_spi_host0_assert.FpvSecCmD0SpiHost0FsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_d0_spi_host1_assert.FpvSecCmD0SpiHost1FsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_d0_sys_assert.FpvSecCmD0SysFsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_d0_usb_aon_assert.FpvSecCmD0UsbAonFsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_d0_usb_assert.FpvSecCmD0UsbFsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_daon_lc_aon_assert.FpvSecCmDAonLcAonFsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_daon_lc_assert.FpvSecCmDAonLcFsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_daon_lc_io_assert.FpvSecCmDAonLcIoFsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_daon_lc_io_div2_assert.FpvSecCmDAonLcIoDiv2FsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_daon_lc_shadowed_assert.FpvSecCmDAonLcShadowedFsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_daon_lc_usb_assert.FpvSecCmDAonLcUsbFsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_daon_por_assert.FpvSecCmDAonPorFsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_daon_por_io_assert.FpvSecCmDAonPorIoFsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_daon_por_io_div2_assert.FpvSecCmDAonPorIoDiv2FsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_daon_por_io_div4_assert.FpvSecCmDAonPorIoDiv4FsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_daon_por_usb_assert.FpvSecCmDAonPorUsbFsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_daon_sys_io_div4_assert.FpvSecCmDAonSysIoDiv4FsmCheck_A	0	0	11125207	90	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_prim_mubi4_sender.OutputsKnown_A	0	0	1583728	934626	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown0	0	0	9194	8690	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_clean_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown0	0	0	8832	8328	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_out_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown0	0	0	7142	6638	0	0
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon.u_rst_root_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.gen_rst_por_aon[0].u_por_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown0	0	0	8832	8328	0	0
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_por_domain_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.gen_rst_por_aon[1].gen_rst_por_domain.u_prim_mubi4_sender.OutputsKnown_A	0	0	1583728	915868	0	0
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.gen_rst_por_aon[1].u_por_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOff_A	0	0	11125207	12594	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].LcHandshakeOn_A	0	0	11125207	116242	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOff_A	0	0	11125207	6287688	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[0].SysHandshakeOn_A	0	0	11125207	185953	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOff_A	0	0	11125207	12594	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].LcHandshakeOn_A	0	0	11125207	116242	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOff_A	0	0	11125207	6287688	0	0
tb.dut.pwrmgr_rstmgr_sva_if.gen_assertions_per_power_domains[1].SysHandshakeOn_A	0	0	11125207	185953	0	0
tb.dut.rstmgr_attrs_sva_if.AlertInfoAttr_A	0	0	504	504	0	0
tb.dut.rstmgr_attrs_sva_if.CpuInfoAttr_A	0	0	504	504	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveFall_A	0	0	52245747	8832	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorAboveRise_A	0	0	52245747	8832	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveFall_A	0	0	50154887	8832	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoAboveRise_A	0	0	50154887	8832	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveFall_A	0	0	25078022	8832	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv2AboveRise_A	0	0	25078022	8832	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveFall_A	0	0	12538562	8832	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorIoDiv4AboveRise_A	0	0	12538562	8832	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveFall_A	0	0	25078098	8832	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeEffAonToRstPorUcbAboveRise_A	0	0	25078098	8832	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveFall_A	0	0	52245747	21426	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAboveRise_A	0	0	52245747	21426	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveFall_A	0	0	1583728	21426	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcAonAboveRise_A	0	0	1583728	21426	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveFall_A	0	0	52245747	21426	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeLcToLcShadowedAboveRise_A	0	0	52245747	21426	0	0
tb.dut.rstmgr_cascading_sva_if.CascadePorToAonAboveFall_A	0	0	1583728	7152	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveFall_A	0	0	52245747	21426	0	0
tb.dut.rstmgr_cascading_sva_if.CascadeSysToSysAboveRise_A	0	0	52245747	21426	0	0
tb.dut.rstmgr_cascading_sva_if.ScanRstToAonRise_A	0	0	1583728	219	0	0
tb.dut.rstmgr_cascading_sva_if.StablePorToAonRise_A	0	0	1583728	8832	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveFall_A	0	0	11125207	21426	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLcToSysAboveRise_A	0	0	11125207	21426	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveFall_A	0	0	11125207	21426	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].CascadeLocalRstToLcAboveRise_A	0	0	11125207	21426	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	0	0	12538562	21426	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	0	0	12538562	21426	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveFall_A	0	0	11125207	21426	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLcToSysAboveRise_A	0	0	11125207	21426	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveFall_A	0	0	11125207	21426	0	0
tb.dut.rstmgr_cascading_sva_if.g_power_domains[1].CascadeLocalRstToLcAboveRise_A	0	0	11125207	21426	0	0
tb.dut.rstmgr_csr_assert.TlulOOBAddrErr_A	0	0	11943447	9438	0	0
tb.dut.rstmgr_csr_assert.alert_regwen_rd_A	0	0	11943447	5098	0	0
tb.dut.rstmgr_csr_assert.cpu_regwen_rd_A	0	0	11943447	5121	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_0_rd_A	0	0	11943447	9475	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_1_rd_A	0	0	11943447	9388	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_2_rd_A	0	0	11943447	9232	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_3_rd_A	0	0	11943447	9465	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_4_rd_A	0	0	11943447	9157	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_5_rd_A	0	0	11943447	9474	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_6_rd_A	0	0	11943447	9463	0	0
tb.dut.rstmgr_csr_assert.sw_rst_ctrl_n_7_rd_A	0	0	11943447	9533	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_0_rd_A	0	0	11943447	5792	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_1_rd_A	0	0	11943447	5739	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_2_rd_A	0	0	11943447	5713	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_3_rd_A	0	0	11943447	5743	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_4_rd_A	0	0	11943447	5568	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_5_rd_A	0	0	11943447	5695	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_6_rd_A	0	0	11943447	5863	0	0
tb.dut.rstmgr_csr_assert.sw_rst_regwen_7_rd_A	0	0	11943447	5751	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Active_A	0	0	12538562	13782	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c0EnTracksRstI2c0Inactive_A	0	0	12538562	22508	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Active_A	0	0	12538562	13845	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c1EnTracksRstI2c1Inactive_A	0	0	12538562	22575	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Active_A	0	0	12538562	13907	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstI2c2EnTracksRstI2c2Inactive_A	0	0	12538562	22632	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Active_A	0	0	25078022	12673	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A	0	0	25078022	21426	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A	0	0	12538562	12694	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A	0	0	12538562	21476	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoActive_A	0	0	50154887	12665	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcIoEnTracksRstLcIoInactive_A	0	0	50154887	21426	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedActive_A	0	0	52245747	12644	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcShadowedEnTracksRstLcShadowedInactive_A	0	0	52245747	21426	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbActive_A	0	0	25078098	12672	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstLcUsbEnTracksRstLcUsbInactive_A	0	0	25078098	21426	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonActive_A	0	0	1583728	50	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstPorAonEnTracksRstPorAonInactive_A	0	0	1583728	8812	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceActive_A	0	0	12538562	13545	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiDeviceEnTracksRstSpiDeviceInactive_A	0	0	12538562	22270	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Active_A	0	0	50154887	13595	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost0EnTracksRstSpiHost0Inactive_A	0	0	50154887	22320	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Active_A	0	0	25078022	13635	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSpiHost1EnTracksRstSpiHost1Inactive_A	0	0	25078022	22358	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysActive_A	0	0	52245747	12665	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstSysEnTracksRstSysInactive_A	0	0	52245747	21426	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonActive_A	0	0	1583728	13345	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbAonEnTracksRstUsbAonInactive_A	0	0	1583728	21667	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbActive_A	0	0	25078098	13675	0	0
tb.dut.rstmgr_rst_en_track_sva_if.D0RstUsbEnTracksRstUsbInactive_A	0	0	25078098	22392	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonActive_A	0	0	1583728	12623	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcAonEnTracksRstLcAonInactive_A	0	0	1583728	21406	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Active_A	0	0	25078022	12616	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv2EnTracksRstLcIoDiv2Inactive_A	0	0	25078022	21426	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedActive_A	0	0	12538562	12644	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoDiv4ShadowedEnTracksRstLcIoDiv4ShadowedInactive_A	0	0	12538562	21476	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoActive_A	0	0	50154887	12617	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcIoEnTracksRstLcIoInactive_A	0	0	50154887	21426	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedActive_A	0	0	52245747	12672	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcShadowedEnTracksRstLcShadowedInactive_A	0	0	52245747	21476	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbActive_A	0	0	25078098	12616	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstLcUsbEnTracksRstLcUsbInactive_A	0	0	25078098	21426	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorAonEnTracksRstPorAonInactive_A	0	0	1583728	8832	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorEnTracksRstPorActive_A	0	0	52245747	29	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Active_A	0	0	25078022	28	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv2EnTracksRstPorIoDiv2Inactive_A	0	0	25078022	2315	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoDiv4EnTracksRstPorIoDiv4Inactive_A	0	0	12538562	8832	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorIoEnTracksRstPorIoActive_A	0	0	50154887	26	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbActive_A	0	0	25078098	28	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstPorUsbEnTracksRstPorUsbInactive_A	0	0	25078098	2315	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Active_A	0	0	12538562	12624	0	0
tb.dut.rstmgr_rst_en_track_sva_if.DAonRstSysIoDiv4EnTracksRstSysIoDiv4Inactive_A	0	0	12538562	21426	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOff_A	0	0	12538562	13437	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstEnOn_A	0	0	12538562	1030	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOff_A	0	0	12538562	13437	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[0].RstNOn_A	0	0	12538562	1030	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOff_A	0	0	50154887	12284	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstEnOn_A	0	0	50154887	994	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOff_A	0	0	50154887	12284	0	0
tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[1].RstNOn_A	0	0	50154887	994	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[2].RstEnOn_A	0	0	25078022	972	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[4].RstEnOn_A	0	0	1583728	1090	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstEnOn_A	0	0	12538562	1114	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[5].RstNOn_A	0	0	12538562	1114	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstEnOn_A	0	0	12538562	1177	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[6].RstNOn_A	0	0	12538562	1177	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstEnOn_A	0	0	12538562	1239	0	0
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tb.dut.rstmgr_sw_rst_sva_if.gen_assertions[7].RstNOn_A	0	0	12538562	1239	0	0
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tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	11943447	6784134	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	11943447	6784134	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	11943447	1849605	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	11943447	6784134	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	11943447	6784134	0	0
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tb.dut.tlul_assert_device.gen_assert_final[98].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
tb.dut.tlul_assert_device.gen_assert_final[99].noOutstandingReqsAtEndOfSim_A	0	0	619	619	0	0
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tb.dut.tlul_assert_device.gen_device.aDataKnown_M	0	0	11944066	483857	0	0
tb.dut.tlul_assert_device.gen_device.addrSizeAlignedErr_A	0	0	11943447	6342	0	0
tb.dut.tlul_assert_device.gen_device.contigMask_M	0	0	11944066	793382	0	0
tb.dut.tlul_assert_device.gen_device.dDataKnown_A	0	0	11944066	948242	0	0
tb.dut.tlul_assert_device.gen_device.legalAOpcodeErr_A	0	0	11943447	6954	0	0
tb.dut.tlul_assert_device.gen_device.legalAParam_M	0	0	11944066	1088108	0	0
tb.dut.tlul_assert_device.gen_device.legalDParam_A	0	0	11944066	1849822	0	0
tb.dut.tlul_assert_device.gen_device.pendingReqPerSrc_M	0	0	11944066	1088108	0	0
tb.dut.tlul_assert_device.gen_device.respMustHaveReq_A	0	0	11944066	1849822	0	0
tb.dut.tlul_assert_device.gen_device.respOpcode_A	0	0	11944066	1849822	0	0
tb.dut.tlul_assert_device.gen_device.respSzEqReqSz_A	0	0	11944066	1849822	0	0
tb.dut.tlul_assert_device.gen_device.sizeGTEMaskErr_A	0	0	11943447	3808	0	0
tb.dut.tlul_assert_device.gen_device.sizeMatchesMaskErr_A	0	0	11943447	2995	0	0
tb.dut.tlul_assert_device.p_dbw.TlDbw_A	0	0	619	619	0	0
tb.dut.u_alert_info.CntStoreSlot_A	0	0	504	504	0	0
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tb.dut.u_cpu_info.CntStoreSlot_A	0	0	504	504	0	0
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tb.dut.u_ctrl_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_ctrl_scanmode_sync.OutputsKnown_A	0	0	12538562	7319916	0	0
tb.dut.u_ctrl_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	12538562	7319916	0	0
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tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_i2c0.u_prim_mubi4_sender.OutputsKnown_A	0	0	12538562	6147724	0	0
tb.dut.u_d0_i2c0.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22505	22001	0	0
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tb.dut.u_d0_i2c0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
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tb.dut.u_d0_i2c0.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
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tb.dut.u_d0_i2c1.u_prim_mubi4_sender.OutputsKnown_A	0	0	12538562	6149938	0	0
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22573	22069	0	0
tb.dut.u_d0_i2c1.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_i2c1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
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tb.dut.u_d0_i2c1.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_i2c2.u_prim_mubi4_sender.OutputsKnown_A	0	0	12538562	6149126	0	0
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22630	22126	0	0
tb.dut.u_d0_i2c2.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_i2c2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_i2c2.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_i2c2.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_lc.u_prim_mubi4_sender.OutputsKnown_A	0	0	52245747	26296040	0	0
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21426	20922	0	0
tb.dut.u_d0_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_lc.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_lc_io.u_prim_mubi4_sender.OutputsKnown_A	0	0	50154887	25243084	0	0
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21426	20922	0	0
tb.dut.u_d0_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_lc_io.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A	0	0	25078022	12611272	0	0
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21426	20922	0	0
tb.dut.u_d0_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A	0	0	12538562	6278671	0	0
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21426	20922	0	0
tb.dut.u_d0_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A	0	0	12538562	6278671	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21426	20922	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A	0	0	52245747	26297192	0	0
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21426	20922	0	0
tb.dut.u_d0_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_lc_usb.u_prim_mubi4_sender.OutputsKnown_A	0	0	25078098	12611323	0	0
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21426	20922	0	0
tb.dut.u_d0_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_lc_usb.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_spi_device.u_prim_mubi4_sender.OutputsKnown_A	0	0	12538562	6144457	0	0
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22269	21765	0	0
tb.dut.u_d0_spi_device.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_spi_device.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_spi_device.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_spi_device.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_spi_host0.u_prim_mubi4_sender.OutputsKnown_A	0	0	50154887	24710502	0	0
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22314	21810	0	0
tb.dut.u_d0_spi_host0.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_spi_host0.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_spi_host0.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_spi_host0.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_spi_host1.u_prim_mubi4_sender.OutputsKnown_A	0	0	25078022	12343114	0	0
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22355	21851	0	0
tb.dut.u_d0_spi_host1.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_spi_host1.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_spi_host1.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_spi_host1.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_sys.u_prim_mubi4_sender.OutputsKnown_A	0	0	52245747	26005581	0	0
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21426	20922	0	0
tb.dut.u_d0_sys.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_sys.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_sys.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_sys.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_usb.u_prim_mubi4_sender.OutputsKnown_A	0	0	25078098	12338185	0	0
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22388	21884	0	0
tb.dut.u_d0_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_usb.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21356	20852	0	0
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_usb_aon.u_prim_mubi4_sender.OutputsKnown_A	0	0	1583728	762113	0	0
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	22457	21953	0	0
tb.dut.u_d0_usb_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_d0_usb_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_d0_usb_aon.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_d0_usb_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_lc.u_prim_mubi4_sender.OutputsKnown_A	0	0	52245747	27023664	0	0
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21426	20922	0	0
tb.dut.u_daon_lc.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_lc.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_lc.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_lc.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21356	20852	0	0
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_lc_aon.u_prim_mubi4_sender.OutputsKnown_A	0	0	1583728	801424	0	0
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21426	20922	0	0
tb.dut.u_daon_lc_aon.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_lc_aon.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_lc_aon.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_lc_aon.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_lc_io.u_prim_mubi4_sender.OutputsKnown_A	0	0	50154887	25943992	0	0
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21426	20922	0	0
tb.dut.u_daon_lc_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_lc_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_lc_io.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_lc_io.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_lc_io_div2.u_prim_mubi4_sender.OutputsKnown_A	0	0	25078022	12962006	0	0
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21426	20922	0	0
tb.dut.u_daon_lc_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_lc_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_lc_io_div4.u_prim_mubi4_sender.OutputsKnown_A	0	0	12538562	6453920	0	0
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21426	20922	0	0
tb.dut.u_daon_lc_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_lc_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_prim_mubi4_sender.OutputsKnown_A	0	0	12538562	6453920	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21426	20922	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_lc_io_div4_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_lc_shadowed.u_prim_mubi4_sender.OutputsKnown_A	0	0	52245747	27023763	0	0
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21426	20922	0	0
tb.dut.u_daon_lc_shadowed.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_lc_shadowed.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_lc_usb.u_prim_mubi4_sender.OutputsKnown_A	0	0	25078098	12961971	0	0
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21426	20922	0	0
tb.dut.u_daon_lc_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_lc_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_lc_usb.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_lc_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_por.u_prim_mubi4_sender.OutputsKnown_A	0	0	52245747	30522775	0	0
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	8832	8328	0	0
tb.dut.u_daon_por.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_por.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_por.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_por.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_por_io.u_prim_mubi4_sender.OutputsKnown_A	0	0	50154887	29301190	0	0
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	8832	8328	0	0
tb.dut.u_daon_por_io.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_por_io.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_por_io.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_por_io.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_por_io_div2.u_prim_mubi4_sender.OutputsKnown_A	0	0	25078022	14646761	0	0
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	8832	8328	0	0
tb.dut.u_daon_por_io_div2.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_por_io_div2.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_por_io_div2.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_por_io_div2.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_por_io_div4.u_prim_mubi4_sender.OutputsKnown_A	0	0	12538562	7319916	0	0
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	8832	8328	0	0
tb.dut.u_daon_por_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_por_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_por_io_div4.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_por_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_por_usb.u_prim_mubi4_sender.OutputsKnown_A	0	0	25078098	14646778	0	0
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	8832	8328	0	0
tb.dut.u_daon_por_usb.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_por_usb.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_por_usb.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_por_usb.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown0	0	0	21476	20972	0	0
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync.g_scan_mux.u_scan_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_sys_io_div4.u_prim_mubi4_sender.OutputsKnown_A	0	0	12538562	6384305	0	0
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown0	0	0	21426	20922	0	0
tb.dut.u_daon_sys_io_div4.u_rst_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.NumCopiesMustBeGreaterZero_A	0	0	504	504	0	0
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.OutputsKnown_A	0	0	11125207	6248275	0	0
tb.dut.u_daon_sys_io_div4.u_scanmode_sync.gen_no_flops.OutputDelay_A	0	0	11125207	6248275	0	0
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0	0	0	21426	20922	0	0
tb.dut.u_lc_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0	0	0	21426	20922	0	0
tb.dut.u_lc_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_reg.en2addrHit	0	0	11943447	932022	0	0
tb.dut.u_reg.reAfterRv	0	0	11943447	931846	0	0
tb.dut.u_reg.rePulse	0	0	11943447	498710	0	0
tb.dut.u_reg.u_chk.PayLoadWidthCheck	0	0	619	619	0	0
tb.dut.u_reg.u_reg_if.AllowedLatency_A	0	0	619	619	0	0
tb.dut.u_reg.u_reg_if.MatchedWidthAssert	0	0	619	619	0	0
tb.dut.u_reg.u_reg_if.u_err.dataWidthOnly32_A	0	0	619	619	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	619	619	0	0
tb.dut.u_reg.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	619	619	0	0
tb.dut.u_reg.u_rsp_intg_gen.DataWidthCheck_A	0	0	619	619	0	0
tb.dut.u_reg.u_rsp_intg_gen.PayLoadWidthCheck	0	0	619	619	0	0
tb.dut.u_reg.wePulse	0	0	11943447	433136	0	0
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown0	0	0	21426	20922	0	0
tb.dut.u_sys_src.gen_rst_pd_n[0].u_rst_pd_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown0	0	0	21426	20922	0	0
tb.dut.u_sys_src.u_rst_aon_mux.gen_generic.u_impl_generic.selKnown1	0	0	2600	2096	0	0

---

Detail Report for Cover Sequences

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	11944066	5610	5610	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	11944066	2401	2401	1
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	11944066	2404	2404	1
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	11944066	1683	1683	1
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	11944066	92	92	1
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	11944066	1340	1340	1
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	11944066	1272	1272	1
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	11944066	3293	3293	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	11944066	52827	52827	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	11944066	407690	407690	454

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	11944066	5610	5610	0
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	11944066	2401	2401	1
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	11944066	2404	2404	1
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	11944066	1683	1683	1
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	11944066	92	92	1
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	11944066	1340	1340	1
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	11944066	1272	1272	1
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	11944066	3293	3293	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	11944066	52827	52827	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	11944066	407690	407690	454