Group : rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg
dashboard | hierarchy | modlist | groups | tests | asserts

Group : rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv



Summary for Group rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 12 0 12 100.00


Variables for Group rstmgr_env_pkg::rstmgr_env_cov::reset_stretcher_cg
VARIABLE   EXPECTED   UNCOVERED   COVERED   PERCENT   GOAL   WEIGHT   AT LEAST   AUTO BIN MAX   COMMENT   
count_cp 4 0 4 100.00 100 1 1 0
length_cp 8 0 8 100.00 100 1 1 0


Summary for Variable count_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for count_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 9658 Excluded


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
cb[0] 1301 1 T1 1 T2 3 T3 1
cb[1] 1171 1 T2 4 T4 4 T5 4
cb[2] 1062 1 T2 4 T4 4 T5 3
cb[3] 1003 1 T2 4 T4 4 T6 4



Summary for Variable length_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 8 0 8 100.00


User Defined Bins for length_cp

Excluded/Illegal bins
NAMECOUNTSTATUS
others 11658 Excluded


Covered bins
NAME   COUNT   AT LEAST   STATUS   TEST   COUNT   TEST   COUNT   TEST   COUNT   
lb[0] 370 1 T2 1 T4 2 T5 1
lb[1] 316 1 T4 1 T5 2 T6 2
lb[2] 330 1 T2 1 T4 3 T5 1
lb[3] 316 1 T2 1 T4 1 T9 1
lb[4] 329 1 T4 3 T5 2 T10 1
lb[5] 287 1 T4 4 T5 2 T9 1
lb[6] 333 1 T4 2 T5 1 T11 2
lb[7] 256 1 T2 1 T6 1 T11 6