Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.44 99.40 99.31 99.87 99.83 99.46 98.77


Total test records in report: 619
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T539 /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3160147896 Aug 10 05:25:28 PM PDT 24 Aug 10 05:25:29 PM PDT 24 243701065 ps
T540 /workspace/coverage/default/36.rstmgr_sw_rst.1390191563 Aug 10 05:24:50 PM PDT 24 Aug 10 05:24:53 PM PDT 24 446625688 ps
T541 /workspace/coverage/default/26.rstmgr_stress_all.1831393895 Aug 10 05:24:43 PM PDT 24 Aug 10 05:25:03 PM PDT 24 3776677707 ps
T542 /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.3849948313 Aug 10 05:24:14 PM PDT 24 Aug 10 05:24:15 PM PDT 24 79320611 ps
T42 /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1852626206 Aug 10 04:58:14 PM PDT 24 Aug 10 04:58:24 PM PDT 24 2277503233 ps
T43 /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2084805911 Aug 10 04:58:23 PM PDT 24 Aug 10 04:58:25 PM PDT 24 425913884 ps
T44 /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3052897201 Aug 10 04:58:12 PM PDT 24 Aug 10 04:58:14 PM PDT 24 254607215 ps
T45 /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1208536985 Aug 10 04:58:14 PM PDT 24 Aug 10 04:58:16 PM PDT 24 219150214 ps
T46 /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2968618315 Aug 10 04:58:31 PM PDT 24 Aug 10 04:58:34 PM PDT 24 466995031 ps
T103 /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3487962330 Aug 10 04:58:21 PM PDT 24 Aug 10 04:58:22 PM PDT 24 94614810 ps
T543 /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2253363412 Aug 10 04:58:28 PM PDT 24 Aug 10 04:58:30 PM PDT 24 81195016 ps
T93 /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.111559306 Aug 10 04:58:29 PM PDT 24 Aug 10 04:58:30 PM PDT 24 70743303 ps
T47 /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2640697025 Aug 10 04:58:28 PM PDT 24 Aug 10 04:58:30 PM PDT 24 116204476 ps
T53 /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3556471748 Aug 10 04:58:23 PM PDT 24 Aug 10 04:58:25 PM PDT 24 175284797 ps
T121 /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3933000236 Aug 10 04:58:29 PM PDT 24 Aug 10 04:58:30 PM PDT 24 87534936 ps
T54 /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.750305459 Aug 10 04:58:13 PM PDT 24 Aug 10 04:58:16 PM PDT 24 930873717 ps
T79 /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2481452797 Aug 10 04:58:39 PM PDT 24 Aug 10 04:58:41 PM PDT 24 860283845 ps
T80 /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3394337691 Aug 10 04:58:12 PM PDT 24 Aug 10 04:58:15 PM PDT 24 291156835 ps
T81 /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.58317776 Aug 10 04:58:24 PM PDT 24 Aug 10 04:58:25 PM PDT 24 183737407 ps
T544 /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2773503671 Aug 10 04:58:22 PM PDT 24 Aug 10 04:58:23 PM PDT 24 86996701 ps
T545 /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2585052719 Aug 10 04:58:13 PM PDT 24 Aug 10 04:58:14 PM PDT 24 68947117 ps
T111 /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2033975621 Aug 10 04:58:12 PM PDT 24 Aug 10 04:58:15 PM PDT 24 879743470 ps
T82 /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2321869502 Aug 10 04:58:24 PM PDT 24 Aug 10 04:58:27 PM PDT 24 198749891 ps
T546 /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.4153510117 Aug 10 04:58:15 PM PDT 24 Aug 10 04:58:21 PM PDT 24 484833739 ps
T94 /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2628459583 Aug 10 04:58:32 PM PDT 24 Aug 10 04:58:33 PM PDT 24 68532641 ps
T547 /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.713529120 Aug 10 04:58:12 PM PDT 24 Aug 10 04:58:13 PM PDT 24 73030866 ps
T95 /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.885937961 Aug 10 04:58:34 PM PDT 24 Aug 10 04:58:36 PM PDT 24 280152836 ps
T83 /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1148533973 Aug 10 04:58:14 PM PDT 24 Aug 10 04:58:18 PM PDT 24 469611374 ps
T84 /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.505945936 Aug 10 04:58:23 PM PDT 24 Aug 10 04:58:25 PM PDT 24 233107860 ps
T96 /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1392138644 Aug 10 04:58:21 PM PDT 24 Aug 10 04:58:23 PM PDT 24 262023522 ps
T97 /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3777636373 Aug 10 04:58:21 PM PDT 24 Aug 10 04:58:22 PM PDT 24 79240764 ps
T85 /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2876041432 Aug 10 04:58:14 PM PDT 24 Aug 10 04:58:17 PM PDT 24 370819248 ps
T107 /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.4035146941 Aug 10 04:58:14 PM PDT 24 Aug 10 04:58:17 PM PDT 24 946086513 ps
T104 /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3157287508 Aug 10 04:58:22 PM PDT 24 Aug 10 04:58:25 PM PDT 24 479250723 ps
T548 /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2839121478 Aug 10 04:58:21 PM PDT 24 Aug 10 04:58:22 PM PDT 24 75282429 ps
T549 /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3314223043 Aug 10 04:58:24 PM PDT 24 Aug 10 04:58:25 PM PDT 24 190249921 ps
T550 /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2380936946 Aug 10 04:58:25 PM PDT 24 Aug 10 04:58:26 PM PDT 24 188697981 ps
T551 /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1651647740 Aug 10 04:58:14 PM PDT 24 Aug 10 04:58:16 PM PDT 24 188368448 ps
T552 /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1113291929 Aug 10 04:58:15 PM PDT 24 Aug 10 04:58:16 PM PDT 24 188875020 ps
T553 /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2534067268 Aug 10 04:58:24 PM PDT 24 Aug 10 04:58:26 PM PDT 24 153194763 ps
T98 /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.4189444739 Aug 10 04:58:22 PM PDT 24 Aug 10 04:58:24 PM PDT 24 97111405 ps
T554 /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3151093351 Aug 10 04:58:24 PM PDT 24 Aug 10 04:58:26 PM PDT 24 176235750 ps
T555 /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1386873064 Aug 10 04:58:24 PM PDT 24 Aug 10 04:58:27 PM PDT 24 503120100 ps
T556 /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2748780427 Aug 10 04:58:13 PM PDT 24 Aug 10 04:58:14 PM PDT 24 83650006 ps
T99 /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3057719325 Aug 10 04:58:21 PM PDT 24 Aug 10 04:58:22 PM PDT 24 89231745 ps
T120 /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2277436571 Aug 10 04:58:22 PM PDT 24 Aug 10 04:58:24 PM PDT 24 470942525 ps
T557 /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2624104852 Aug 10 04:58:12 PM PDT 24 Aug 10 04:58:14 PM PDT 24 468201951 ps
T100 /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4283094011 Aug 10 04:58:21 PM PDT 24 Aug 10 04:58:23 PM PDT 24 252025849 ps
T558 /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1720168448 Aug 10 04:58:19 PM PDT 24 Aug 10 04:58:21 PM PDT 24 121031624 ps
T105 /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2973545543 Aug 10 04:58:16 PM PDT 24 Aug 10 04:58:20 PM PDT 24 921172521 ps
T101 /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1212000093 Aug 10 04:58:22 PM PDT 24 Aug 10 04:58:24 PM PDT 24 73446330 ps
T102 /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.4276784922 Aug 10 04:58:23 PM PDT 24 Aug 10 04:58:24 PM PDT 24 74830379 ps
T559 /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1769570353 Aug 10 04:58:14 PM PDT 24 Aug 10 04:58:20 PM PDT 24 1041620152 ps
T560 /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.427702735 Aug 10 04:58:23 PM PDT 24 Aug 10 04:58:25 PM PDT 24 191497971 ps
T119 /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2158034111 Aug 10 04:58:22 PM PDT 24 Aug 10 04:58:26 PM PDT 24 875752614 ps
T561 /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1573505882 Aug 10 04:58:24 PM PDT 24 Aug 10 04:58:26 PM PDT 24 189232142 ps
T562 /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1246263056 Aug 10 04:58:29 PM PDT 24 Aug 10 04:58:31 PM PDT 24 124487990 ps
T108 /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1210474257 Aug 10 04:58:15 PM PDT 24 Aug 10 04:58:18 PM PDT 24 832043074 ps
T563 /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3648996117 Aug 10 04:58:28 PM PDT 24 Aug 10 04:58:30 PM PDT 24 499991754 ps
T564 /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3430923852 Aug 10 04:58:13 PM PDT 24 Aug 10 04:58:16 PM PDT 24 445654534 ps
T565 /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2389690112 Aug 10 04:58:25 PM PDT 24 Aug 10 04:58:26 PM PDT 24 105702547 ps
T566 /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3043393660 Aug 10 04:58:22 PM PDT 24 Aug 10 04:58:25 PM PDT 24 875580836 ps
T567 /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3226010641 Aug 10 04:58:11 PM PDT 24 Aug 10 04:58:14 PM PDT 24 201730934 ps
T568 /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1313933365 Aug 10 04:58:14 PM PDT 24 Aug 10 04:58:17 PM PDT 24 428864862 ps
T569 /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.852238904 Aug 10 04:58:13 PM PDT 24 Aug 10 04:58:18 PM PDT 24 789278802 ps
T570 /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2681667438 Aug 10 04:58:31 PM PDT 24 Aug 10 04:58:33 PM PDT 24 423739745 ps
T571 /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3935627554 Aug 10 04:58:16 PM PDT 24 Aug 10 04:58:17 PM PDT 24 197772606 ps
T572 /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1411179133 Aug 10 04:58:23 PM PDT 24 Aug 10 04:58:25 PM PDT 24 222743573 ps
T573 /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1649256699 Aug 10 04:58:22 PM PDT 24 Aug 10 04:58:23 PM PDT 24 66234236 ps
T574 /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.398535882 Aug 10 04:58:25 PM PDT 24 Aug 10 04:58:27 PM PDT 24 266402463 ps
T575 /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2284837114 Aug 10 04:58:13 PM PDT 24 Aug 10 04:58:14 PM PDT 24 77534554 ps
T576 /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.755098763 Aug 10 04:58:16 PM PDT 24 Aug 10 04:58:18 PM PDT 24 154571335 ps
T577 /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1482819698 Aug 10 04:58:13 PM PDT 24 Aug 10 04:58:14 PM PDT 24 217744174 ps
T578 /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3633438148 Aug 10 04:58:13 PM PDT 24 Aug 10 04:58:19 PM PDT 24 1184915565 ps
T579 /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3137023547 Aug 10 04:58:21 PM PDT 24 Aug 10 04:58:24 PM PDT 24 412779099 ps
T580 /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3175032083 Aug 10 04:58:14 PM PDT 24 Aug 10 04:58:16 PM PDT 24 119199839 ps
T581 /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2109981188 Aug 10 04:58:23 PM PDT 24 Aug 10 04:58:27 PM PDT 24 488405481 ps
T582 /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3029513944 Aug 10 04:58:20 PM PDT 24 Aug 10 04:58:22 PM PDT 24 165574014 ps
T583 /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.29131086 Aug 10 04:58:15 PM PDT 24 Aug 10 04:58:16 PM PDT 24 96032114 ps
T584 /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.576348316 Aug 10 04:58:13 PM PDT 24 Aug 10 04:58:15 PM PDT 24 105499762 ps
T585 /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2129309436 Aug 10 04:58:22 PM PDT 24 Aug 10 04:58:24 PM PDT 24 226322654 ps
T586 /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3969688565 Aug 10 04:58:21 PM PDT 24 Aug 10 04:58:23 PM PDT 24 495617316 ps
T587 /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.206592145 Aug 10 04:58:14 PM PDT 24 Aug 10 04:58:16 PM PDT 24 346065793 ps
T588 /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2433708834 Aug 10 04:58:22 PM PDT 24 Aug 10 04:58:24 PM PDT 24 262166170 ps
T589 /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1864119654 Aug 10 04:58:16 PM PDT 24 Aug 10 04:58:17 PM PDT 24 64859650 ps
T590 /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1953313994 Aug 10 04:58:21 PM PDT 24 Aug 10 04:58:22 PM PDT 24 82529621 ps
T591 /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.136097991 Aug 10 04:58:25 PM PDT 24 Aug 10 04:58:26 PM PDT 24 103192830 ps
T592 /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4064095036 Aug 10 04:58:11 PM PDT 24 Aug 10 04:58:12 PM PDT 24 119148864 ps
T593 /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2395393025 Aug 10 04:58:22 PM PDT 24 Aug 10 04:58:23 PM PDT 24 68493302 ps
T594 /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3942655766 Aug 10 04:58:22 PM PDT 24 Aug 10 04:58:23 PM PDT 24 89827396 ps
T595 /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2765268992 Aug 10 04:58:13 PM PDT 24 Aug 10 04:58:14 PM PDT 24 89818764 ps
T106 /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.385332445 Aug 10 04:58:23 PM PDT 24 Aug 10 04:58:25 PM PDT 24 441236631 ps
T596 /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2281633269 Aug 10 04:58:22 PM PDT 24 Aug 10 04:58:25 PM PDT 24 144859258 ps
T597 /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.425667349 Aug 10 04:58:23 PM PDT 24 Aug 10 04:58:25 PM PDT 24 127781342 ps
T598 /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3748313155 Aug 10 04:58:31 PM PDT 24 Aug 10 04:58:32 PM PDT 24 113580631 ps
T599 /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.15817356 Aug 10 04:58:20 PM PDT 24 Aug 10 04:58:21 PM PDT 24 83579035 ps
T109 /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4089966389 Aug 10 04:58:21 PM PDT 24 Aug 10 04:58:25 PM PDT 24 973113630 ps
T600 /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2531040409 Aug 10 04:58:17 PM PDT 24 Aug 10 04:58:18 PM PDT 24 102280175 ps
T601 /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3577065825 Aug 10 04:58:16 PM PDT 24 Aug 10 04:58:17 PM PDT 24 136525268 ps
T602 /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2967853429 Aug 10 04:58:21 PM PDT 24 Aug 10 04:58:22 PM PDT 24 81817017 ps
T603 /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3654699694 Aug 10 04:58:21 PM PDT 24 Aug 10 04:58:23 PM PDT 24 178493330 ps
T604 /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1091236202 Aug 10 04:58:14 PM PDT 24 Aug 10 04:58:16 PM PDT 24 465195705 ps
T605 /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1319738805 Aug 10 04:58:24 PM PDT 24 Aug 10 04:58:25 PM PDT 24 184122747 ps
T606 /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1626371924 Aug 10 04:58:24 PM PDT 24 Aug 10 04:58:25 PM PDT 24 71040834 ps
T607 /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2388685587 Aug 10 04:58:15 PM PDT 24 Aug 10 04:58:19 PM PDT 24 645325013 ps
T608 /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2466637444 Aug 10 04:58:24 PM PDT 24 Aug 10 04:58:27 PM PDT 24 424079321 ps
T609 /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.818994888 Aug 10 04:58:11 PM PDT 24 Aug 10 04:58:13 PM PDT 24 166118591 ps
T610 /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2935856872 Aug 10 04:58:16 PM PDT 24 Aug 10 04:58:17 PM PDT 24 65994777 ps
T611 /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1135906337 Aug 10 04:58:13 PM PDT 24 Aug 10 04:58:14 PM PDT 24 65193462 ps
T612 /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.4100503216 Aug 10 04:58:13 PM PDT 24 Aug 10 04:58:14 PM PDT 24 88068292 ps
T110 /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.129902980 Aug 10 04:58:28 PM PDT 24 Aug 10 04:58:31 PM PDT 24 780409304 ps
T613 /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4108766388 Aug 10 04:58:14 PM PDT 24 Aug 10 04:58:16 PM PDT 24 98831272 ps
T614 /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.577011444 Aug 10 04:58:21 PM PDT 24 Aug 10 04:58:23 PM PDT 24 217375698 ps
T615 /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2707325635 Aug 10 04:58:16 PM PDT 24 Aug 10 04:58:18 PM PDT 24 108700636 ps
T616 /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.734390000 Aug 10 04:58:17 PM PDT 24 Aug 10 04:58:18 PM PDT 24 153664257 ps
T89 /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3671868777 Aug 10 04:58:13 PM PDT 24 Aug 10 04:58:14 PM PDT 24 140658038 ps
T617 /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2246620466 Aug 10 04:58:16 PM PDT 24 Aug 10 04:58:18 PM PDT 24 173701211 ps
T618 /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3277724205 Aug 10 04:58:22 PM PDT 24 Aug 10 04:58:24 PM PDT 24 148070845 ps
T619 /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1117005344 Aug 10 04:58:38 PM PDT 24 Aug 10 04:58:40 PM PDT 24 215025229 ps

Test location /workspace/coverage/default/44.rstmgr_reset.3847246383
Short name T9
Test name
Test status
Simulation time 1470592261 ps
CPU time 5.47 seconds
Started Aug 10 05:25:23 PM PDT 24
Finished Aug 10 05:25:28 PM PDT 24
Peak memory 200616 kb
Host smart-2b461b25-7067-43b7-b362-d65b59c10f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847246383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_reset.3847246383
Directory /workspace/44.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst.3999055051
Short name T31
Test name
Test status
Simulation time 531900809 ps
CPU time 2.75 seconds
Started Aug 10 05:24:39 PM PDT 24
Finished Aug 10 05:24:42 PM PDT 24
Peak memory 200488 kb
Host smart-f324b15a-1c67-4fa8-82b5-199fe8c3aee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999055051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst.3999055051
Directory /workspace/4.rstmgr_sw_rst/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_intg_err.2481452797
Short name T79
Test name
Test status
Simulation time 860283845 ps
CPU time 2.75 seconds
Started Aug 10 04:58:39 PM PDT 24
Finished Aug 10 04:58:41 PM PDT 24
Peak memory 200220 kb
Host smart-f14c1824-12d8-45fd-942e-5d15b6b4e23b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481452797 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_intg_er
r.2481452797
Directory /workspace/19.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm.964876943
Short name T48
Test name
Test status
Simulation time 8644840507 ps
CPU time 15.73 seconds
Started Aug 10 05:24:14 PM PDT 24
Finished Aug 10 05:24:29 PM PDT 24
Peak memory 217636 kb
Host smart-6a0f9de3-07c1-4ab5-aed0-9dc46cea308c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964876943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm.964876943
Directory /workspace/1.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_cnsty.1766950802
Short name T6
Test name
Test status
Simulation time 1891122174 ps
CPU time 7.85 seconds
Started Aug 10 05:24:54 PM PDT 24
Finished Aug 10 05:25:02 PM PDT 24
Peak memory 221596 kb
Host smart-6b1a8183-52e4-448b-84ec-0829bac2667e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766950802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_cnsty.1766950802
Directory /workspace/17.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_errors.1148533973
Short name T83
Test name
Test status
Simulation time 469611374 ps
CPU time 3.36 seconds
Started Aug 10 04:58:14 PM PDT 24
Finished Aug 10 04:58:18 PM PDT 24
Peak memory 208308 kb
Host smart-2be850f4-6126-4497-9a68-020187af0eb9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148533973 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_errors.1148533973
Directory /workspace/3.rstmgr_tl_errors/latest

Test location /workspace/coverage/default/11.rstmgr_stress_all.416718993
Short name T11
Test name
Test status
Simulation time 6749466385 ps
CPU time 29.7 seconds
Started Aug 10 05:24:28 PM PDT 24
Finished Aug 10 05:24:58 PM PDT 24
Peak memory 208840 kb
Host smart-ca56958b-f3d6-47f3-a5ac-f676e3a57a18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=416718993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_stress_all.416718993
Directory /workspace/11.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_alert_test.231326034
Short name T51
Test name
Test status
Simulation time 68872820 ps
CPU time 0.79 seconds
Started Aug 10 05:24:29 PM PDT 24
Finished Aug 10 05:24:30 PM PDT 24
Peak memory 200160 kb
Host smart-ad30124d-6d2a-4b09-bb75-20ab31dceb36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231326034 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_alert_test.231326034
Directory /workspace/15.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_stress_all.3234676848
Short name T174
Test name
Test status
Simulation time 11914453010 ps
CPU time 37.97 seconds
Started Aug 10 05:24:37 PM PDT 24
Finished Aug 10 05:25:15 PM PDT 24
Peak memory 200472 kb
Host smart-48351d07-1203-4672-900a-2b81356f762d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234676848 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_stress_all.3234676848
Directory /workspace/19.rstmgr_stress_all/latest

Test location /workspace/coverage/default/11.rstmgr_sec_cm_scan_intersig_mubi.2711979979
Short name T134
Test name
Test status
Simulation time 154405180 ps
CPU time 1.13 seconds
Started Aug 10 05:24:38 PM PDT 24
Finished Aug 10 05:24:39 PM PDT 24
Peak memory 200340 kb
Host smart-c08918e7-2e7e-424c-8e21-c73ff56b4b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711979979 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sec_cm_scan_intersig_mubi.2711979979
Directory /workspace/11.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_cnsty.4222208369
Short name T32
Test name
Test status
Simulation time 1234241160 ps
CPU time 5.66 seconds
Started Aug 10 05:25:11 PM PDT 24
Finished Aug 10 05:25:16 PM PDT 24
Peak memory 217752 kb
Host smart-e92cdde2-554a-45ae-a430-196bbefb005e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222208369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_cnsty.4222208369
Directory /workspace/45.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_intg_err.2033975621
Short name T111
Test name
Test status
Simulation time 879743470 ps
CPU time 3.06 seconds
Started Aug 10 04:58:12 PM PDT 24
Finished Aug 10 04:58:15 PM PDT 24
Peak memory 200152 kb
Host smart-1bff3cfc-43ef-4313-827f-6ea728079bc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033975621 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_intg_err
.2033975621
Directory /workspace/1.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst_reset_race.2143921179
Short name T8
Test name
Test status
Simulation time 105316382 ps
CPU time 0.94 seconds
Started Aug 10 05:24:27 PM PDT 24
Finished Aug 10 05:24:28 PM PDT 24
Peak memory 200244 kb
Host smart-d38d9b07-61dd-4e33-a879-025d36ae5645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143921179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst_reset_race.2143921179
Directory /workspace/16.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_rw.111559306
Short name T93
Test name
Test status
Simulation time 70743303 ps
CPU time 0.89 seconds
Started Aug 10 04:58:29 PM PDT 24
Finished Aug 10 04:58:30 PM PDT 24
Peak memory 200032 kb
Host smart-c5fe971c-2843-4ade-b397-36b9ade7b51d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=111559306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_csr_rw.111559306
Directory /workspace/16.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_intg_err.4089966389
Short name T109
Test name
Test status
Simulation time 973113630 ps
CPU time 3.03 seconds
Started Aug 10 04:58:21 PM PDT 24
Finished Aug 10 04:58:25 PM PDT 24
Peak memory 200112 kb
Host smart-0c7b28db-cfef-449b-841c-3746ecbd43d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4089966389 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_intg_er
r.4089966389
Directory /workspace/11.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.rstmgr_por_stretcher.2262649715
Short name T15
Test name
Test status
Simulation time 192411542 ps
CPU time 0.91 seconds
Started Aug 10 05:24:42 PM PDT 24
Finished Aug 10 05:24:43 PM PDT 24
Peak memory 200144 kb
Host smart-1b7de090-9295-473f-a5f8-40649af211f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2262649715 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_por_stretcher.2262649715
Directory /workspace/10.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_shadow_attack.3020044277
Short name T138
Test name
Test status
Simulation time 244199463 ps
CPU time 1.19 seconds
Started Aug 10 05:24:36 PM PDT 24
Finished Aug 10 05:24:37 PM PDT 24
Peak memory 217504 kb
Host smart-236952b3-19d3-4808-8787-a5cfa413453b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3020044277 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_shadow_attack.3020044277
Directory /workspace/15.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_mem_rw_with_rand_reset.1482819698
Short name T577
Test name
Test status
Simulation time 217744174 ps
CPU time 1.52 seconds
Started Aug 10 04:58:13 PM PDT 24
Finished Aug 10 04:58:14 PM PDT 24
Peak memory 208304 kb
Host smart-2e1768ef-25da-4949-b6f4-22ea31c8cfe9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1482819698 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.rstmgr_csr_mem_rw_with_rand_reset.1482819698
Directory /workspace/0.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_intg_err.385332445
Short name T106
Test name
Test status
Simulation time 441236631 ps
CPU time 1.79 seconds
Started Aug 10 04:58:23 PM PDT 24
Finished Aug 10 04:58:25 PM PDT 24
Peak memory 200208 kb
Host smart-dc5bae79-f271-4d47-ab50-418122a66d64
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385332445 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_intg_err
.385332445
Directory /workspace/16.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_intg_err.4035146941
Short name T107
Test name
Test status
Simulation time 946086513 ps
CPU time 3.28 seconds
Started Aug 10 04:58:14 PM PDT 24
Finished Aug 10 04:58:17 PM PDT 24
Peak memory 200288 kb
Host smart-fed02525-e35d-4bc1-904d-20cc8759e21f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035146941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_intg_err
.4035146941
Directory /workspace/2.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.rstmgr_stress_all.403847550
Short name T61
Test name
Test status
Simulation time 4470932908 ps
CPU time 20.79 seconds
Started Aug 10 05:24:31 PM PDT 24
Finished Aug 10 05:24:52 PM PDT 24
Peak memory 200480 kb
Host smart-530bef60-c5a4-4889-98a9-93ba7150baea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403847550 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_stress_all.403847550
Directory /workspace/10.rstmgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_aliasing.4108766388
Short name T613
Test name
Test status
Simulation time 98831272 ps
CPU time 1.35 seconds
Started Aug 10 04:58:14 PM PDT 24
Finished Aug 10 04:58:16 PM PDT 24
Peak memory 208380 kb
Host smart-87b841a8-e723-40b3-80a4-61319d58f15d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4108766388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_aliasing.4
108766388
Directory /workspace/0.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_bit_bash.3633438148
Short name T578
Test name
Test status
Simulation time 1184915565 ps
CPU time 5.6 seconds
Started Aug 10 04:58:13 PM PDT 24
Finished Aug 10 04:58:19 PM PDT 24
Peak memory 200128 kb
Host smart-c027c2f2-f8f1-4b5a-842d-9bb667bacf1f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633438148 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_bit_bash.3
633438148
Directory /workspace/0.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_hw_reset.2765268992
Short name T595
Test name
Test status
Simulation time 89818764 ps
CPU time 0.82 seconds
Started Aug 10 04:58:13 PM PDT 24
Finished Aug 10 04:58:14 PM PDT 24
Peak memory 200092 kb
Host smart-7515df06-1e08-4612-8ac7-562e4354ef20
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765268992 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_hw_reset.2
765268992
Directory /workspace/0.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_csr_rw.1864119654
Short name T589
Test name
Test status
Simulation time 64859650 ps
CPU time 0.86 seconds
Started Aug 10 04:58:16 PM PDT 24
Finished Aug 10 04:58:17 PM PDT 24
Peak memory 200056 kb
Host smart-94461e6b-8349-468f-a3f9-32e9acb20e9a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864119654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_csr_rw.1864119654
Directory /workspace/0.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_same_csr_outstanding.576348316
Short name T584
Test name
Test status
Simulation time 105499762 ps
CPU time 1.29 seconds
Started Aug 10 04:58:13 PM PDT 24
Finished Aug 10 04:58:15 PM PDT 24
Peak memory 200208 kb
Host smart-bd71754b-f542-456f-8323-7db74535e40e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576348316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_sam
e_csr_outstanding.576348316
Directory /workspace/0.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_errors.3394337691
Short name T80
Test name
Test status
Simulation time 291156835 ps
CPU time 2.21 seconds
Started Aug 10 04:58:12 PM PDT 24
Finished Aug 10 04:58:15 PM PDT 24
Peak memory 210700 kb
Host smart-86d7538f-62c5-4409-bdcf-8ab1aec9507c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394337691 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_errors.3394337691
Directory /workspace/0.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.rstmgr_tl_intg_err.2624104852
Short name T557
Test name
Test status
Simulation time 468201951 ps
CPU time 1.84 seconds
Started Aug 10 04:58:12 PM PDT 24
Finished Aug 10 04:58:14 PM PDT 24
Peak memory 200224 kb
Host smart-cec0763a-11e5-420a-a83f-da2dd7b586c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624104852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.rstmgr_tl_intg_err
.2624104852
Directory /workspace/0.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_aliasing.755098763
Short name T576
Test name
Test status
Simulation time 154571335 ps
CPU time 2.03 seconds
Started Aug 10 04:58:16 PM PDT 24
Finished Aug 10 04:58:18 PM PDT 24
Peak memory 200152 kb
Host smart-46f09b32-44e2-4cc5-879e-09f0fbb375fe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755098763 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_aliasing.755098763
Directory /workspace/1.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_bit_bash.4153510117
Short name T546
Test name
Test status
Simulation time 484833739 ps
CPU time 5.87 seconds
Started Aug 10 04:58:15 PM PDT 24
Finished Aug 10 04:58:21 PM PDT 24
Peak memory 200176 kb
Host smart-443e4071-0a7d-4c61-848c-04519b0ada54
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153510117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_bit_bash.4
153510117
Directory /workspace/1.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_hw_reset.3487962330
Short name T103
Test name
Test status
Simulation time 94614810 ps
CPU time 0.87 seconds
Started Aug 10 04:58:21 PM PDT 24
Finished Aug 10 04:58:22 PM PDT 24
Peak memory 200020 kb
Host smart-8791f567-23ec-4aee-8411-deba12595e9a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3487962330 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_hw_reset.3
487962330
Directory /workspace/1.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_mem_rw_with_rand_reset.3577065825
Short name T601
Test name
Test status
Simulation time 136525268 ps
CPU time 1.53 seconds
Started Aug 10 04:58:16 PM PDT 24
Finished Aug 10 04:58:17 PM PDT 24
Peak memory 208400 kb
Host smart-22f113ac-2396-4761-a9f3-079038b0ac76
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577065825 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.rstmgr_csr_mem_rw_with_rand_reset.3577065825
Directory /workspace/1.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_csr_rw.713529120
Short name T547
Test name
Test status
Simulation time 73030866 ps
CPU time 0.81 seconds
Started Aug 10 04:58:12 PM PDT 24
Finished Aug 10 04:58:13 PM PDT 24
Peak memory 199996 kb
Host smart-56f5e5f1-98fc-434a-8681-fc86c351575c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713529120 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_csr_rw.713529120
Directory /workspace/1.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_same_csr_outstanding.2531040409
Short name T600
Test name
Test status
Simulation time 102280175 ps
CPU time 1.24 seconds
Started Aug 10 04:58:17 PM PDT 24
Finished Aug 10 04:58:18 PM PDT 24
Peak memory 200172 kb
Host smart-b957e651-b363-41aa-b9c8-34d1ed203013
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531040409 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_sa
me_csr_outstanding.2531040409
Directory /workspace/1.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.rstmgr_tl_errors.1208536985
Short name T45
Test name
Test status
Simulation time 219150214 ps
CPU time 1.95 seconds
Started Aug 10 04:58:14 PM PDT 24
Finished Aug 10 04:58:16 PM PDT 24
Peak memory 208340 kb
Host smart-0cf1ac64-2064-4e83-b772-8b28775d4d8e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208536985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.rstmgr_tl_errors.1208536985
Directory /workspace/1.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_mem_rw_with_rand_reset.3654699694
Short name T603
Test name
Test status
Simulation time 178493330 ps
CPU time 1.72 seconds
Started Aug 10 04:58:21 PM PDT 24
Finished Aug 10 04:58:23 PM PDT 24
Peak memory 208420 kb
Host smart-a92ceb4d-3d4a-4ba6-897b-c924c99bc5d1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654699694 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.rstmgr_csr_mem_rw_with_rand_reset.3654699694
Directory /workspace/10.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_csr_rw.1626371924
Short name T606
Test name
Test status
Simulation time 71040834 ps
CPU time 0.84 seconds
Started Aug 10 04:58:24 PM PDT 24
Finished Aug 10 04:58:25 PM PDT 24
Peak memory 200008 kb
Host smart-c0594b80-20b9-465f-ab8f-1175030838ab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626371924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_csr_rw.1626371924
Directory /workspace/10.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_same_csr_outstanding.3057719325
Short name T99
Test name
Test status
Simulation time 89231745 ps
CPU time 1.01 seconds
Started Aug 10 04:58:21 PM PDT 24
Finished Aug 10 04:58:22 PM PDT 24
Peak memory 200128 kb
Host smart-14233b70-050a-4783-9b9b-ca682749295a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057719325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_s
ame_csr_outstanding.3057719325
Directory /workspace/10.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_errors.2281633269
Short name T596
Test name
Test status
Simulation time 144859258 ps
CPU time 2.16 seconds
Started Aug 10 04:58:22 PM PDT 24
Finished Aug 10 04:58:25 PM PDT 24
Peak memory 208324 kb
Host smart-5b026e2a-9ed7-40bd-a5f5-498b25823250
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2281633269 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_errors.2281633269
Directory /workspace/10.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.rstmgr_tl_intg_err.3137023547
Short name T579
Test name
Test status
Simulation time 412779099 ps
CPU time 1.82 seconds
Started Aug 10 04:58:21 PM PDT 24
Finished Aug 10 04:58:24 PM PDT 24
Peak memory 200112 kb
Host smart-8dfbe7f6-dd8d-4caf-a425-a7034b6bd5b1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137023547 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.rstmgr_tl_intg_er
r.3137023547
Directory /workspace/10.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_mem_rw_with_rand_reset.58317776
Short name T81
Test name
Test status
Simulation time 183737407 ps
CPU time 1.26 seconds
Started Aug 10 04:58:24 PM PDT 24
Finished Aug 10 04:58:25 PM PDT 24
Peak memory 208288 kb
Host smart-12b8c93d-a52f-440d-9c01-814cb50f10e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58317776 -assert nopostproc +UVM_TESTNAME=r
stmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.rstmgr_csr_mem_rw_with_rand_reset.58317776
Directory /workspace/11.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_csr_rw.2967853429
Short name T602
Test name
Test status
Simulation time 81817017 ps
CPU time 0.79 seconds
Started Aug 10 04:58:21 PM PDT 24
Finished Aug 10 04:58:22 PM PDT 24
Peak memory 200020 kb
Host smart-0684064b-9392-4759-895a-424309a6cd0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967853429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_csr_rw.2967853429
Directory /workspace/11.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_same_csr_outstanding.1212000093
Short name T101
Test name
Test status
Simulation time 73446330 ps
CPU time 0.96 seconds
Started Aug 10 04:58:22 PM PDT 24
Finished Aug 10 04:58:24 PM PDT 24
Peak memory 200132 kb
Host smart-1e4502d5-d7fe-4bfc-acb8-447cd2d948dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212000093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_s
ame_csr_outstanding.1212000093
Directory /workspace/11.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.rstmgr_tl_errors.2466637444
Short name T608
Test name
Test status
Simulation time 424079321 ps
CPU time 2.93 seconds
Started Aug 10 04:58:24 PM PDT 24
Finished Aug 10 04:58:27 PM PDT 24
Peak memory 208248 kb
Host smart-7446f9ca-a4ec-483b-a21a-5ba21520a4e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466637444 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.rstmgr_tl_errors.2466637444
Directory /workspace/11.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_mem_rw_with_rand_reset.2534067268
Short name T553
Test name
Test status
Simulation time 153194763 ps
CPU time 1.31 seconds
Started Aug 10 04:58:24 PM PDT 24
Finished Aug 10 04:58:26 PM PDT 24
Peak memory 216576 kb
Host smart-66ef3a61-727c-4ad2-8993-a4da3433516b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534067268 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.rstmgr_csr_mem_rw_with_rand_reset.2534067268
Directory /workspace/12.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_csr_rw.15817356
Short name T599
Test name
Test status
Simulation time 83579035 ps
CPU time 0.89 seconds
Started Aug 10 04:58:20 PM PDT 24
Finished Aug 10 04:58:21 PM PDT 24
Peak memory 200016 kb
Host smart-d21dfc3d-5b0e-4b09-b7ff-de28c77a3678
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15817356 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_csr_rw.15817356
Directory /workspace/12.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_same_csr_outstanding.2129309436
Short name T585
Test name
Test status
Simulation time 226322654 ps
CPU time 1.44 seconds
Started Aug 10 04:58:22 PM PDT 24
Finished Aug 10 04:58:24 PM PDT 24
Peak memory 200236 kb
Host smart-b17d65c6-93ac-42a4-b769-f9b446dcc79e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129309436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_s
ame_csr_outstanding.2129309436
Directory /workspace/12.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_errors.3157287508
Short name T104
Test name
Test status
Simulation time 479250723 ps
CPU time 3.02 seconds
Started Aug 10 04:58:22 PM PDT 24
Finished Aug 10 04:58:25 PM PDT 24
Peak memory 211792 kb
Host smart-dc2a3656-00d0-4da7-b29e-cef2380a4736
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157287508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_errors.3157287508
Directory /workspace/12.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.rstmgr_tl_intg_err.3648996117
Short name T563
Test name
Test status
Simulation time 499991754 ps
CPU time 2.02 seconds
Started Aug 10 04:58:28 PM PDT 24
Finished Aug 10 04:58:30 PM PDT 24
Peak memory 200212 kb
Host smart-bec14baf-80c8-4c6e-8fc1-222d438fc82e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3648996117 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.rstmgr_tl_intg_er
r.3648996117
Directory /workspace/12.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_mem_rw_with_rand_reset.3556471748
Short name T53
Test name
Test status
Simulation time 175284797 ps
CPU time 1.12 seconds
Started Aug 10 04:58:23 PM PDT 24
Finished Aug 10 04:58:25 PM PDT 24
Peak memory 208352 kb
Host smart-52cfbc79-5195-49a2-b844-fd4de09cf8af
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556471748 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.rstmgr_csr_mem_rw_with_rand_reset.3556471748
Directory /workspace/13.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_csr_rw.2395393025
Short name T593
Test name
Test status
Simulation time 68493302 ps
CPU time 0.83 seconds
Started Aug 10 04:58:22 PM PDT 24
Finished Aug 10 04:58:23 PM PDT 24
Peak memory 200000 kb
Host smart-a648c31b-cd72-4df8-abcd-01b6967b29df
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395393025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_csr_rw.2395393025
Directory /workspace/13.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_same_csr_outstanding.2433708834
Short name T588
Test name
Test status
Simulation time 262166170 ps
CPU time 1.54 seconds
Started Aug 10 04:58:22 PM PDT 24
Finished Aug 10 04:58:24 PM PDT 24
Peak memory 200168 kb
Host smart-ee9b612d-4113-4c75-b8f8-0e38aee7fd26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2433708834 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_s
ame_csr_outstanding.2433708834
Directory /workspace/13.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_errors.2109981188
Short name T581
Test name
Test status
Simulation time 488405481 ps
CPU time 3.03 seconds
Started Aug 10 04:58:23 PM PDT 24
Finished Aug 10 04:58:27 PM PDT 24
Peak memory 208300 kb
Host smart-93857bbc-14f5-41fd-9b31-39d7d98897a5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109981188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_errors.2109981188
Directory /workspace/13.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.rstmgr_tl_intg_err.1386873064
Short name T555
Test name
Test status
Simulation time 503120100 ps
CPU time 2.11 seconds
Started Aug 10 04:58:24 PM PDT 24
Finished Aug 10 04:58:27 PM PDT 24
Peak memory 200184 kb
Host smart-d0385eec-dc85-4616-be2b-fbf9a6405bfd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386873064 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.rstmgr_tl_intg_er
r.1386873064
Directory /workspace/13.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_mem_rw_with_rand_reset.2380936946
Short name T550
Test name
Test status
Simulation time 188697981 ps
CPU time 1.23 seconds
Started Aug 10 04:58:25 PM PDT 24
Finished Aug 10 04:58:26 PM PDT 24
Peak memory 200048 kb
Host smart-fb676006-488b-4cbe-87aa-9f256e109c03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380936946 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.rstmgr_csr_mem_rw_with_rand_reset.2380936946
Directory /workspace/14.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_csr_rw.4276784922
Short name T102
Test name
Test status
Simulation time 74830379 ps
CPU time 0.83 seconds
Started Aug 10 04:58:23 PM PDT 24
Finished Aug 10 04:58:24 PM PDT 24
Peak memory 200008 kb
Host smart-8ff1a897-384e-4efc-9760-9bd16f7c4531
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276784922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_csr_rw.4276784922
Directory /workspace/14.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_same_csr_outstanding.398535882
Short name T574
Test name
Test status
Simulation time 266402463 ps
CPU time 1.69 seconds
Started Aug 10 04:58:25 PM PDT 24
Finished Aug 10 04:58:27 PM PDT 24
Peak memory 200084 kb
Host smart-58cb1d6b-f201-43d7-8eac-66f835e13469
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398535882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_sa
me_csr_outstanding.398535882
Directory /workspace/14.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_errors.3277724205
Short name T618
Test name
Test status
Simulation time 148070845 ps
CPU time 2.03 seconds
Started Aug 10 04:58:22 PM PDT 24
Finished Aug 10 04:58:24 PM PDT 24
Peak memory 208208 kb
Host smart-b3732da3-dfc3-4705-83ae-f9898210951b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3277724205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_errors.3277724205
Directory /workspace/14.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.rstmgr_tl_intg_err.2277436571
Short name T120
Test name
Test status
Simulation time 470942525 ps
CPU time 1.79 seconds
Started Aug 10 04:58:22 PM PDT 24
Finished Aug 10 04:58:24 PM PDT 24
Peak memory 200268 kb
Host smart-3c0815dd-3061-4235-8d36-3942296844fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2277436571 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.rstmgr_tl_intg_er
r.2277436571
Directory /workspace/14.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_mem_rw_with_rand_reset.3029513944
Short name T582
Test name
Test status
Simulation time 165574014 ps
CPU time 1.64 seconds
Started Aug 10 04:58:20 PM PDT 24
Finished Aug 10 04:58:22 PM PDT 24
Peak memory 208472 kb
Host smart-e96efd39-319e-43c9-abb8-0c932fef449d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3029513944 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.rstmgr_csr_mem_rw_with_rand_reset.3029513944
Directory /workspace/15.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_csr_rw.2773503671
Short name T544
Test name
Test status
Simulation time 86996701 ps
CPU time 0.84 seconds
Started Aug 10 04:58:22 PM PDT 24
Finished Aug 10 04:58:23 PM PDT 24
Peak memory 200000 kb
Host smart-e9dfd49a-f600-4bf3-9596-1c8f596067bb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773503671 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_csr_rw.2773503671
Directory /workspace/15.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_same_csr_outstanding.4189444739
Short name T98
Test name
Test status
Simulation time 97111405 ps
CPU time 1.25 seconds
Started Aug 10 04:58:22 PM PDT 24
Finished Aug 10 04:58:24 PM PDT 24
Peak memory 200140 kb
Host smart-4fff0091-1382-449e-8c29-2ef69a14d0b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4189444739 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_s
ame_csr_outstanding.4189444739
Directory /workspace/15.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_errors.505945936
Short name T84
Test name
Test status
Simulation time 233107860 ps
CPU time 1.8 seconds
Started Aug 10 04:58:23 PM PDT 24
Finished Aug 10 04:58:25 PM PDT 24
Peak memory 208192 kb
Host smart-a0104892-4061-4184-b9de-289d2a6816dc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=505945936 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_errors.505945936
Directory /workspace/15.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.rstmgr_tl_intg_err.3043393660
Short name T566
Test name
Test status
Simulation time 875580836 ps
CPU time 2.82 seconds
Started Aug 10 04:58:22 PM PDT 24
Finished Aug 10 04:58:25 PM PDT 24
Peak memory 200216 kb
Host smart-2606c563-1279-4d36-bd66-b055363e1fdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3043393660 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.rstmgr_tl_intg_er
r.3043393660
Directory /workspace/15.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_csr_mem_rw_with_rand_reset.1573505882
Short name T561
Test name
Test status
Simulation time 189232142 ps
CPU time 1.79 seconds
Started Aug 10 04:58:24 PM PDT 24
Finished Aug 10 04:58:26 PM PDT 24
Peak memory 208360 kb
Host smart-55e6bf8c-697a-4764-af6a-725cc25024a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573505882 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.rstmgr_csr_mem_rw_with_rand_reset.1573505882
Directory /workspace/16.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_same_csr_outstanding.425667349
Short name T597
Test name
Test status
Simulation time 127781342 ps
CPU time 1.06 seconds
Started Aug 10 04:58:23 PM PDT 24
Finished Aug 10 04:58:25 PM PDT 24
Peak memory 200100 kb
Host smart-ec15c6ba-a0d4-451f-a29e-9588e0ad481c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425667349 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_sa
me_csr_outstanding.425667349
Directory /workspace/16.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.rstmgr_tl_errors.3151093351
Short name T554
Test name
Test status
Simulation time 176235750 ps
CPU time 2.37 seconds
Started Aug 10 04:58:24 PM PDT 24
Finished Aug 10 04:58:26 PM PDT 24
Peak memory 211804 kb
Host smart-e138360c-44f3-46e6-80ab-0bf3b534124b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151093351 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.rstmgr_tl_errors.3151093351
Directory /workspace/16.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_mem_rw_with_rand_reset.577011444
Short name T614
Test name
Test status
Simulation time 217375698 ps
CPU time 1.36 seconds
Started Aug 10 04:58:21 PM PDT 24
Finished Aug 10 04:58:23 PM PDT 24
Peak memory 208288 kb
Host smart-9f751fb3-3a02-4899-b0cb-224d5e6644b1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=577011444 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.rstmgr_csr_mem_rw_with_rand_reset.577011444
Directory /workspace/17.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_csr_rw.2253363412
Short name T543
Test name
Test status
Simulation time 81195016 ps
CPU time 0.84 seconds
Started Aug 10 04:58:28 PM PDT 24
Finished Aug 10 04:58:30 PM PDT 24
Peak memory 200032 kb
Host smart-9708e803-4f46-4710-8f98-3359bc603081
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2253363412 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_csr_rw.2253363412
Directory /workspace/17.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_same_csr_outstanding.1411179133
Short name T572
Test name
Test status
Simulation time 222743573 ps
CPU time 1.58 seconds
Started Aug 10 04:58:23 PM PDT 24
Finished Aug 10 04:58:25 PM PDT 24
Peak memory 200160 kb
Host smart-3ced0e09-c77c-44ad-a6bf-755518c8f73a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1411179133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_s
ame_csr_outstanding.1411179133
Directory /workspace/17.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_errors.2640697025
Short name T47
Test name
Test status
Simulation time 116204476 ps
CPU time 1.66 seconds
Started Aug 10 04:58:28 PM PDT 24
Finished Aug 10 04:58:30 PM PDT 24
Peak memory 208324 kb
Host smart-78a1c547-1d61-4015-8487-3b41889d0110
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640697025 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_errors.2640697025
Directory /workspace/17.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.rstmgr_tl_intg_err.2084805911
Short name T43
Test name
Test status
Simulation time 425913884 ps
CPU time 1.74 seconds
Started Aug 10 04:58:23 PM PDT 24
Finished Aug 10 04:58:25 PM PDT 24
Peak memory 200172 kb
Host smart-f8117720-d194-4f5c-9449-01449505154b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084805911 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.rstmgr_tl_intg_er
r.2084805911
Directory /workspace/17.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_mem_rw_with_rand_reset.3748313155
Short name T598
Test name
Test status
Simulation time 113580631 ps
CPU time 0.98 seconds
Started Aug 10 04:58:31 PM PDT 24
Finished Aug 10 04:58:32 PM PDT 24
Peak memory 200200 kb
Host smart-904ae2a7-637e-4e7d-b206-b59e8f9ba91d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748313155 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.rstmgr_csr_mem_rw_with_rand_reset.3748313155
Directory /workspace/18.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_csr_rw.2628459583
Short name T94
Test name
Test status
Simulation time 68532641 ps
CPU time 0.76 seconds
Started Aug 10 04:58:32 PM PDT 24
Finished Aug 10 04:58:33 PM PDT 24
Peak memory 200068 kb
Host smart-75ed74cb-98ea-42ed-9b6d-19c00bb770a9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628459583 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_csr_rw.2628459583
Directory /workspace/18.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_same_csr_outstanding.1117005344
Short name T619
Test name
Test status
Simulation time 215025229 ps
CPU time 1.5 seconds
Started Aug 10 04:58:38 PM PDT 24
Finished Aug 10 04:58:40 PM PDT 24
Peak memory 200236 kb
Host smart-b719fe27-3993-402e-ab5b-1425adf85821
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117005344 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_s
ame_csr_outstanding.1117005344
Directory /workspace/18.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_errors.427702735
Short name T560
Test name
Test status
Simulation time 191497971 ps
CPU time 2.62 seconds
Started Aug 10 04:58:23 PM PDT 24
Finished Aug 10 04:58:25 PM PDT 24
Peak memory 208352 kb
Host smart-0c6d2ad0-5d10-4f49-ab71-e16428b3b9a6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=427702735 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_errors.427702735
Directory /workspace/18.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.rstmgr_tl_intg_err.2681667438
Short name T570
Test name
Test status
Simulation time 423739745 ps
CPU time 1.87 seconds
Started Aug 10 04:58:31 PM PDT 24
Finished Aug 10 04:58:33 PM PDT 24
Peak memory 200148 kb
Host smart-b49fa4a1-c5d0-4171-8efd-9c77a3ed9547
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681667438 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.rstmgr_tl_intg_er
r.2681667438
Directory /workspace/18.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_mem_rw_with_rand_reset.1246263056
Short name T562
Test name
Test status
Simulation time 124487990 ps
CPU time 1.11 seconds
Started Aug 10 04:58:29 PM PDT 24
Finished Aug 10 04:58:31 PM PDT 24
Peak memory 200356 kb
Host smart-ed70e8a7-7e81-4d37-a44a-2f17474ef097
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246263056 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.rstmgr_csr_mem_rw_with_rand_reset.1246263056
Directory /workspace/19.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_csr_rw.3933000236
Short name T121
Test name
Test status
Simulation time 87534936 ps
CPU time 0.91 seconds
Started Aug 10 04:58:29 PM PDT 24
Finished Aug 10 04:58:30 PM PDT 24
Peak memory 200008 kb
Host smart-2fb1db9d-f431-411a-b30d-af093b383beb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933000236 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_csr_rw.3933000236
Directory /workspace/19.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_same_csr_outstanding.885937961
Short name T95
Test name
Test status
Simulation time 280152836 ps
CPU time 1.69 seconds
Started Aug 10 04:58:34 PM PDT 24
Finished Aug 10 04:58:36 PM PDT 24
Peak memory 200244 kb
Host smart-40e0465a-2e34-44bb-926c-36a46152c614
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=885937961 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_sa
me_csr_outstanding.885937961
Directory /workspace/19.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.rstmgr_tl_errors.2968618315
Short name T46
Test name
Test status
Simulation time 466995031 ps
CPU time 3.27 seconds
Started Aug 10 04:58:31 PM PDT 24
Finished Aug 10 04:58:34 PM PDT 24
Peak memory 208436 kb
Host smart-61e45d79-5266-4d61-864e-3a32445cf432
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968618315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.rstmgr_tl_errors.2968618315
Directory /workspace/19.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_aliasing.3052897201
Short name T44
Test name
Test status
Simulation time 254607215 ps
CPU time 1.64 seconds
Started Aug 10 04:58:12 PM PDT 24
Finished Aug 10 04:58:14 PM PDT 24
Peak memory 200084 kb
Host smart-a3db2c97-c525-4c96-868d-42fa0c238d89
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052897201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_aliasing.3
052897201
Directory /workspace/2.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_bit_bash.1769570353
Short name T559
Test name
Test status
Simulation time 1041620152 ps
CPU time 5.53 seconds
Started Aug 10 04:58:14 PM PDT 24
Finished Aug 10 04:58:20 PM PDT 24
Peak memory 200136 kb
Host smart-858b1046-a1c1-4135-b2f4-9bccbb88bafc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769570353 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_bit_bash.1
769570353
Directory /workspace/2.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_hw_reset.2748780427
Short name T556
Test name
Test status
Simulation time 83650006 ps
CPU time 0.79 seconds
Started Aug 10 04:58:13 PM PDT 24
Finished Aug 10 04:58:14 PM PDT 24
Peak memory 199968 kb
Host smart-96ba6c44-5f09-471d-9b59-d24d16f65ae1
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748780427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_hw_reset.2
748780427
Directory /workspace/2.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_mem_rw_with_rand_reset.2246620466
Short name T617
Test name
Test status
Simulation time 173701211 ps
CPU time 1.56 seconds
Started Aug 10 04:58:16 PM PDT 24
Finished Aug 10 04:58:18 PM PDT 24
Peak memory 208380 kb
Host smart-0eb67c0d-0902-4a2c-ade2-2c6d9db4172e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246620466 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.rstmgr_csr_mem_rw_with_rand_reset.2246620466
Directory /workspace/2.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_csr_rw.1135906337
Short name T611
Test name
Test status
Simulation time 65193462 ps
CPU time 0.8 seconds
Started Aug 10 04:58:13 PM PDT 24
Finished Aug 10 04:58:14 PM PDT 24
Peak memory 199992 kb
Host smart-47fa169b-b6c3-4738-bbd4-7e08bcce6a50
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1135906337 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_csr_rw.1135906337
Directory /workspace/2.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_same_csr_outstanding.2284837114
Short name T575
Test name
Test status
Simulation time 77534554 ps
CPU time 0.92 seconds
Started Aug 10 04:58:13 PM PDT 24
Finished Aug 10 04:58:14 PM PDT 24
Peak memory 200132 kb
Host smart-5cb295d1-86e2-4b62-8397-eea176cad6af
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2284837114 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_sa
me_csr_outstanding.2284837114
Directory /workspace/2.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.rstmgr_tl_errors.2388685587
Short name T607
Test name
Test status
Simulation time 645325013 ps
CPU time 3.97 seconds
Started Aug 10 04:58:15 PM PDT 24
Finished Aug 10 04:58:19 PM PDT 24
Peak memory 208352 kb
Host smart-08e694a1-49df-4d2b-9697-ebefd0aa9eb2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388685587 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.rstmgr_tl_errors.2388685587
Directory /workspace/2.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_aliasing.3430923852
Short name T564
Test name
Test status
Simulation time 445654534 ps
CPU time 2.64 seconds
Started Aug 10 04:58:13 PM PDT 24
Finished Aug 10 04:58:16 PM PDT 24
Peak memory 200072 kb
Host smart-bef6e1df-ed36-4f75-91d0-5e22cae92636
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430923852 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_aliasing.3
430923852
Directory /workspace/3.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_bit_bash.1852626206
Short name T42
Test name
Test status
Simulation time 2277503233 ps
CPU time 9.74 seconds
Started Aug 10 04:58:14 PM PDT 24
Finished Aug 10 04:58:24 PM PDT 24
Peak memory 200208 kb
Host smart-b9b22423-bb2a-4940-97a7-214004e6fa82
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1852626206 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_bit_bash.1
852626206
Directory /workspace/3.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_hw_reset.3671868777
Short name T89
Test name
Test status
Simulation time 140658038 ps
CPU time 0.92 seconds
Started Aug 10 04:58:13 PM PDT 24
Finished Aug 10 04:58:14 PM PDT 24
Peak memory 199992 kb
Host smart-240591c4-f347-4749-9f8f-702655414dcf
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671868777 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_hw_reset.3
671868777
Directory /workspace/3.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_mem_rw_with_rand_reset.818994888
Short name T609
Test name
Test status
Simulation time 166118591 ps
CPU time 1.44 seconds
Started Aug 10 04:58:11 PM PDT 24
Finished Aug 10 04:58:13 PM PDT 24
Peak memory 208432 kb
Host smart-600ca146-d24e-4d05-9b5b-bbfcafc5c018
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=818994888 -assert nopostproc +UVM_TESTNAME=
rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 3.rstmgr_csr_mem_rw_with_rand_reset.818994888
Directory /workspace/3.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_csr_rw.4100503216
Short name T612
Test name
Test status
Simulation time 88068292 ps
CPU time 0.91 seconds
Started Aug 10 04:58:13 PM PDT 24
Finished Aug 10 04:58:14 PM PDT 24
Peak memory 200052 kb
Host smart-70fe61c3-0255-4b6c-bf8b-d33bc95114a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100503216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_csr_rw.4100503216
Directory /workspace/3.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_same_csr_outstanding.4283094011
Short name T100
Test name
Test status
Simulation time 252025849 ps
CPU time 1.63 seconds
Started Aug 10 04:58:21 PM PDT 24
Finished Aug 10 04:58:23 PM PDT 24
Peak memory 200156 kb
Host smart-5499e085-adad-4886-8abf-dd8ced93fd83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283094011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_sa
me_csr_outstanding.4283094011
Directory /workspace/3.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.rstmgr_tl_intg_err.750305459
Short name T54
Test name
Test status
Simulation time 930873717 ps
CPU time 3 seconds
Started Aug 10 04:58:13 PM PDT 24
Finished Aug 10 04:58:16 PM PDT 24
Peak memory 200192 kb
Host smart-0db29235-da41-4d14-bcfa-ea45cc2bd65e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750305459 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.rstmgr_tl_intg_err.
750305459
Directory /workspace/3.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_aliasing.206592145
Short name T587
Test name
Test status
Simulation time 346065793 ps
CPU time 2.26 seconds
Started Aug 10 04:58:14 PM PDT 24
Finished Aug 10 04:58:16 PM PDT 24
Peak memory 208292 kb
Host smart-b5a22844-1564-4ed3-856e-729c798740dd
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206592145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_aliasing.206592145
Directory /workspace/4.rstmgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_bit_bash.852238904
Short name T569
Test name
Test status
Simulation time 789278802 ps
CPU time 4.67 seconds
Started Aug 10 04:58:13 PM PDT 24
Finished Aug 10 04:58:18 PM PDT 24
Peak memory 200036 kb
Host smart-af045f6d-24f2-42c9-9c14-ccfe9109baaf
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=852238904 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_bit_bash.852238904
Directory /workspace/4.rstmgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_hw_reset.29131086
Short name T583
Test name
Test status
Simulation time 96032114 ps
CPU time 0.82 seconds
Started Aug 10 04:58:15 PM PDT 24
Finished Aug 10 04:58:16 PM PDT 24
Peak memory 200048 kb
Host smart-9626dd7e-0664-4de5-aca4-3c9fb22ee6b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29131086 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_hw_reset.29131086
Directory /workspace/4.rstmgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_mem_rw_with_rand_reset.1113291929
Short name T552
Test name
Test status
Simulation time 188875020 ps
CPU time 1.29 seconds
Started Aug 10 04:58:15 PM PDT 24
Finished Aug 10 04:58:16 PM PDT 24
Peak memory 208340 kb
Host smart-0619faaf-b97a-44e8-a0ea-694c382eaac1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1113291929 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.rstmgr_csr_mem_rw_with_rand_reset.1113291929
Directory /workspace/4.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_csr_rw.3777636373
Short name T97
Test name
Test status
Simulation time 79240764 ps
CPU time 0.79 seconds
Started Aug 10 04:58:21 PM PDT 24
Finished Aug 10 04:58:22 PM PDT 24
Peak memory 199932 kb
Host smart-3b18a12c-e606-450e-9a91-ad1b2a12d4c4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777636373 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_csr_rw.3777636373
Directory /workspace/4.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_same_csr_outstanding.734390000
Short name T616
Test name
Test status
Simulation time 153664257 ps
CPU time 1.28 seconds
Started Aug 10 04:58:17 PM PDT 24
Finished Aug 10 04:58:18 PM PDT 24
Peak memory 200096 kb
Host smart-0dc4d2c2-65e1-4ead-95ab-c9bd34dc9b5c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734390000 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_sam
e_csr_outstanding.734390000
Directory /workspace/4.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_errors.3226010641
Short name T567
Test name
Test status
Simulation time 201730934 ps
CPU time 2.85 seconds
Started Aug 10 04:58:11 PM PDT 24
Finished Aug 10 04:58:14 PM PDT 24
Peak memory 208284 kb
Host smart-1cda9834-6769-460d-ad3c-d772dd819f89
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226010641 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_errors.3226010641
Directory /workspace/4.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.rstmgr_tl_intg_err.2973545543
Short name T105
Test name
Test status
Simulation time 921172521 ps
CPU time 3.06 seconds
Started Aug 10 04:58:16 PM PDT 24
Finished Aug 10 04:58:20 PM PDT 24
Peak memory 200168 kb
Host smart-9aefb91f-381d-46cb-b7d4-5f61d40e5fa9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973545543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.rstmgr_tl_intg_err
.2973545543
Directory /workspace/4.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_mem_rw_with_rand_reset.3935627554
Short name T571
Test name
Test status
Simulation time 197772606 ps
CPU time 1.36 seconds
Started Aug 10 04:58:16 PM PDT 24
Finished Aug 10 04:58:17 PM PDT 24
Peak memory 200192 kb
Host smart-2b9fde3d-6092-4c78-b4e0-416d4541d27b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935627554 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.rstmgr_csr_mem_rw_with_rand_reset.3935627554
Directory /workspace/5.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_csr_rw.2935856872
Short name T610
Test name
Test status
Simulation time 65994777 ps
CPU time 0.84 seconds
Started Aug 10 04:58:16 PM PDT 24
Finished Aug 10 04:58:17 PM PDT 24
Peak memory 200056 kb
Host smart-14149434-6329-4473-a85b-236826a39530
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935856872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_csr_rw.2935856872
Directory /workspace/5.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_same_csr_outstanding.3175032083
Short name T580
Test name
Test status
Simulation time 119199839 ps
CPU time 1.1 seconds
Started Aug 10 04:58:14 PM PDT 24
Finished Aug 10 04:58:16 PM PDT 24
Peak memory 200084 kb
Host smart-27d0ad3a-0d07-4c8f-bbc2-7e715e957cc3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175032083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_sa
me_csr_outstanding.3175032083
Directory /workspace/5.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_errors.1313933365
Short name T568
Test name
Test status
Simulation time 428864862 ps
CPU time 2.77 seconds
Started Aug 10 04:58:14 PM PDT 24
Finished Aug 10 04:58:17 PM PDT 24
Peak memory 208308 kb
Host smart-10789cf9-4369-40a2-a69b-5cd7071ff0db
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313933365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_errors.1313933365
Directory /workspace/5.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.rstmgr_tl_intg_err.1210474257
Short name T108
Test name
Test status
Simulation time 832043074 ps
CPU time 2.76 seconds
Started Aug 10 04:58:15 PM PDT 24
Finished Aug 10 04:58:18 PM PDT 24
Peak memory 200276 kb
Host smart-2b4a1412-979b-480f-bce6-014a2327538c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1210474257 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.rstmgr_tl_intg_err
.1210474257
Directory /workspace/5.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_mem_rw_with_rand_reset.1651647740
Short name T551
Test name
Test status
Simulation time 188368448 ps
CPU time 1.38 seconds
Started Aug 10 04:58:14 PM PDT 24
Finished Aug 10 04:58:16 PM PDT 24
Peak memory 200348 kb
Host smart-e515eb1f-3d97-4bfe-9051-d7a419dc71b3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651647740 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.rstmgr_csr_mem_rw_with_rand_reset.1651647740
Directory /workspace/6.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_csr_rw.2839121478
Short name T548
Test name
Test status
Simulation time 75282429 ps
CPU time 0.8 seconds
Started Aug 10 04:58:21 PM PDT 24
Finished Aug 10 04:58:22 PM PDT 24
Peak memory 199932 kb
Host smart-70a6f681-675a-4428-b809-14cec8e9607b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839121478 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_csr_rw.2839121478
Directory /workspace/6.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_same_csr_outstanding.4064095036
Short name T592
Test name
Test status
Simulation time 119148864 ps
CPU time 1.07 seconds
Started Aug 10 04:58:11 PM PDT 24
Finished Aug 10 04:58:12 PM PDT 24
Peak memory 200084 kb
Host smart-acabbd07-2149-4b9a-b2cc-c88449e6ee70
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064095036 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_sa
me_csr_outstanding.4064095036
Directory /workspace/6.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_errors.2876041432
Short name T85
Test name
Test status
Simulation time 370819248 ps
CPU time 2.83 seconds
Started Aug 10 04:58:14 PM PDT 24
Finished Aug 10 04:58:17 PM PDT 24
Peak memory 208384 kb
Host smart-9136b9b6-a9fd-41bf-9298-ece7bf694bcf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876041432 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_errors.2876041432
Directory /workspace/6.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.rstmgr_tl_intg_err.3969688565
Short name T586
Test name
Test status
Simulation time 495617316 ps
CPU time 1.89 seconds
Started Aug 10 04:58:21 PM PDT 24
Finished Aug 10 04:58:23 PM PDT 24
Peak memory 200156 kb
Host smart-b3551f6c-3143-420e-bc2b-9d6a0899795f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969688565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.rstmgr_tl_intg_err
.3969688565
Directory /workspace/6.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_mem_rw_with_rand_reset.3314223043
Short name T549
Test name
Test status
Simulation time 190249921 ps
CPU time 1.34 seconds
Started Aug 10 04:58:24 PM PDT 24
Finished Aug 10 04:58:25 PM PDT 24
Peak memory 208392 kb
Host smart-db12fb7a-684b-443b-a938-c618442ccd67
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314223043 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.rstmgr_csr_mem_rw_with_rand_reset.3314223043
Directory /workspace/7.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_csr_rw.2585052719
Short name T545
Test name
Test status
Simulation time 68947117 ps
CPU time 0.76 seconds
Started Aug 10 04:58:13 PM PDT 24
Finished Aug 10 04:58:14 PM PDT 24
Peak memory 200008 kb
Host smart-8d5681f3-8516-4d36-b9b1-9f0d92bb83e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585052719 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_csr_rw.2585052719
Directory /workspace/7.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_same_csr_outstanding.1953313994
Short name T590
Test name
Test status
Simulation time 82529621 ps
CPU time 1.03 seconds
Started Aug 10 04:58:21 PM PDT 24
Finished Aug 10 04:58:22 PM PDT 24
Peak memory 200068 kb
Host smart-09a29fd9-1bcd-4d56-99d4-958e0cb64dbd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1953313994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_sa
me_csr_outstanding.1953313994
Directory /workspace/7.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_errors.2707325635
Short name T615
Test name
Test status
Simulation time 108700636 ps
CPU time 1.62 seconds
Started Aug 10 04:58:16 PM PDT 24
Finished Aug 10 04:58:18 PM PDT 24
Peak memory 200136 kb
Host smart-5091a35c-a7ff-4cb1-a467-f70c426090bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707325635 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_errors.2707325635
Directory /workspace/7.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.rstmgr_tl_intg_err.1091236202
Short name T604
Test name
Test status
Simulation time 465195705 ps
CPU time 1.98 seconds
Started Aug 10 04:58:14 PM PDT 24
Finished Aug 10 04:58:16 PM PDT 24
Peak memory 200208 kb
Host smart-2295cd39-d3bd-4cf4-a0fc-443dcdf102c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091236202 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.rstmgr_tl_intg_err
.1091236202
Directory /workspace/7.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_mem_rw_with_rand_reset.1319738805
Short name T605
Test name
Test status
Simulation time 184122747 ps
CPU time 1.31 seconds
Started Aug 10 04:58:24 PM PDT 24
Finished Aug 10 04:58:25 PM PDT 24
Peak memory 208364 kb
Host smart-37dc7a67-5ecf-4b64-be9c-fa114e84e22e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319738805 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.rstmgr_csr_mem_rw_with_rand_reset.1319738805
Directory /workspace/8.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_csr_rw.3942655766
Short name T594
Test name
Test status
Simulation time 89827396 ps
CPU time 0.89 seconds
Started Aug 10 04:58:22 PM PDT 24
Finished Aug 10 04:58:23 PM PDT 24
Peak memory 200020 kb
Host smart-0a994b1f-6f87-487b-9af7-fb9e49125799
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942655766 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_csr_rw.3942655766
Directory /workspace/8.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_same_csr_outstanding.136097991
Short name T591
Test name
Test status
Simulation time 103192830 ps
CPU time 1.25 seconds
Started Aug 10 04:58:25 PM PDT 24
Finished Aug 10 04:58:26 PM PDT 24
Peak memory 200096 kb
Host smart-0a64a3bc-32d8-4890-b53b-d19e47991601
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136097991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstm
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_sam
e_csr_outstanding.136097991
Directory /workspace/8.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_errors.2321869502
Short name T82
Test name
Test status
Simulation time 198749891 ps
CPU time 2.91 seconds
Started Aug 10 04:58:24 PM PDT 24
Finished Aug 10 04:58:27 PM PDT 24
Peak memory 211820 kb
Host smart-394090b8-3902-43d5-b7aa-489f609a4705
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321869502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_errors.2321869502
Directory /workspace/8.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.rstmgr_tl_intg_err.129902980
Short name T110
Test name
Test status
Simulation time 780409304 ps
CPU time 3 seconds
Started Aug 10 04:58:28 PM PDT 24
Finished Aug 10 04:58:31 PM PDT 24
Peak memory 200280 kb
Host smart-fb2ce800-ab6c-424b-a2ff-26537b96a0fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129902980 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.rstmgr_tl_intg_err.
129902980
Directory /workspace/8.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_mem_rw_with_rand_reset.2389690112
Short name T565
Test name
Test status
Simulation time 105702547 ps
CPU time 0.91 seconds
Started Aug 10 04:58:25 PM PDT 24
Finished Aug 10 04:58:26 PM PDT 24
Peak memory 199836 kb
Host smart-0a117e7a-3f3b-468e-9ede-d07078b92ac8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389690112 -assert nopostproc +UVM_TESTNAME
=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.rstmgr_csr_mem_rw_with_rand_reset.2389690112
Directory /workspace/9.rstmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_csr_rw.1649256699
Short name T573
Test name
Test status
Simulation time 66234236 ps
CPU time 0.79 seconds
Started Aug 10 04:58:22 PM PDT 24
Finished Aug 10 04:58:23 PM PDT 24
Peak memory 199996 kb
Host smart-a8e0a1de-a88d-4164-ac2e-82e01e1d3ce5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649256699 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_csr_rw.1649256699
Directory /workspace/9.rstmgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_same_csr_outstanding.1392138644
Short name T96
Test name
Test status
Simulation time 262023522 ps
CPU time 1.63 seconds
Started Aug 10 04:58:21 PM PDT 24
Finished Aug 10 04:58:23 PM PDT 24
Peak memory 200288 kb
Host smart-9654290c-609e-44bb-ac1f-2962b13f3096
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1392138644 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rst
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_sa
me_csr_outstanding.1392138644
Directory /workspace/9.rstmgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_errors.1720168448
Short name T558
Test name
Test status
Simulation time 121031624 ps
CPU time 1.66 seconds
Started Aug 10 04:58:19 PM PDT 24
Finished Aug 10 04:58:21 PM PDT 24
Peak memory 208296 kb
Host smart-262573bc-708e-4588-8e2e-175ecea91703
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720168448 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_errors.1720168448
Directory /workspace/9.rstmgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.rstmgr_tl_intg_err.2158034111
Short name T119
Test name
Test status
Simulation time 875752614 ps
CPU time 3.24 seconds
Started Aug 10 04:58:22 PM PDT 24
Finished Aug 10 04:58:26 PM PDT 24
Peak memory 200188 kb
Host smart-6c08087a-4481-41f5-94a1-452ecc8c14a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158034111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.rstmgr_tl_intg_err
.2158034111
Directory /workspace/9.rstmgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.rstmgr_alert_test.3535715863
Short name T433
Test name
Test status
Simulation time 76646734 ps
CPU time 0.8 seconds
Started Aug 10 05:24:08 PM PDT 24
Finished Aug 10 05:24:09 PM PDT 24
Peak memory 200136 kb
Host smart-78014dbe-a1d0-44dc-8244-e54c0e2a6b0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535715863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_alert_test.3535715863
Directory /workspace/0.rstmgr_alert_test/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_cnsty.3626236316
Short name T337
Test name
Test status
Simulation time 2356801600 ps
CPU time 8.18 seconds
Started Aug 10 05:24:13 PM PDT 24
Finished Aug 10 05:24:22 PM PDT 24
Peak memory 217416 kb
Host smart-fe1a1174-0fb4-4700-b2b9-84b216397190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626236316 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_cnsty.3626236316
Directory /workspace/0.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/0.rstmgr_leaf_rst_shadow_attack.1926849825
Short name T231
Test name
Test status
Simulation time 243860578 ps
CPU time 1.12 seconds
Started Aug 10 05:24:04 PM PDT 24
Finished Aug 10 05:24:05 PM PDT 24
Peak memory 217460 kb
Host smart-0ead15ec-ab5c-4f44-a2e3-ad8dd3eb535c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1926849825 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_leaf_rst_shadow_attack.1926849825
Directory /workspace/0.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/0.rstmgr_por_stretcher.2002729937
Short name T245
Test name
Test status
Simulation time 159740463 ps
CPU time 0.94 seconds
Started Aug 10 05:24:08 PM PDT 24
Finished Aug 10 05:24:09 PM PDT 24
Peak memory 199996 kb
Host smart-fe7af316-45f4-480c-8774-0ffaeea7ca0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002729937 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_por_stretcher.2002729937
Directory /workspace/0.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/0.rstmgr_reset.3101517874
Short name T113
Test name
Test status
Simulation time 2041423967 ps
CPU time 7.22 seconds
Started Aug 10 05:24:18 PM PDT 24
Finished Aug 10 05:24:25 PM PDT 24
Peak memory 200392 kb
Host smart-529f4bce-574c-4185-a89d-7fd155171d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101517874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_reset.3101517874
Directory /workspace/0.rstmgr_reset/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm.3426176808
Short name T55
Test name
Test status
Simulation time 16616322442 ps
CPU time 25.98 seconds
Started Aug 10 05:24:14 PM PDT 24
Finished Aug 10 05:24:40 PM PDT 24
Peak memory 217676 kb
Host smart-61713220-ea94-4e88-bf36-19c0c0127a4e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426176808 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm.3426176808
Directory /workspace/0.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/0.rstmgr_sec_cm_scan_intersig_mubi.4096726350
Short name T385
Test name
Test status
Simulation time 178580034 ps
CPU time 1.16 seconds
Started Aug 10 05:24:11 PM PDT 24
Finished Aug 10 05:24:12 PM PDT 24
Peak memory 200268 kb
Host smart-3911d4bb-7b96-459c-8c13-b6ce6c0357e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4096726350 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sec_cm_scan_intersig_mubi.4096726350
Directory /workspace/0.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/0.rstmgr_smoke.238856069
Short name T510
Test name
Test status
Simulation time 190204339 ps
CPU time 1.37 seconds
Started Aug 10 05:24:01 PM PDT 24
Finished Aug 10 05:24:03 PM PDT 24
Peak memory 200544 kb
Host smart-7103845e-a568-4f81-acf0-17a027902aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238856069 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_smoke.238856069
Directory /workspace/0.rstmgr_smoke/latest

Test location /workspace/coverage/default/0.rstmgr_stress_all.3504680038
Short name T314
Test name
Test status
Simulation time 4161929836 ps
CPU time 14.12 seconds
Started Aug 10 05:23:57 PM PDT 24
Finished Aug 10 05:24:12 PM PDT 24
Peak memory 200528 kb
Host smart-846b05e8-2243-490b-b36d-6c2fec46802c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3504680038 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_stress_all.3504680038
Directory /workspace/0.rstmgr_stress_all/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst.3884667586
Short name T535
Test name
Test status
Simulation time 134402313 ps
CPU time 1.75 seconds
Started Aug 10 05:24:11 PM PDT 24
Finished Aug 10 05:24:13 PM PDT 24
Peak memory 200184 kb
Host smart-81099e99-418a-4fab-9006-697cd4318a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884667586 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst.3884667586
Directory /workspace/0.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/0.rstmgr_sw_rst_reset_race.2018675578
Short name T116
Test name
Test status
Simulation time 107956564 ps
CPU time 0.88 seconds
Started Aug 10 05:24:12 PM PDT 24
Finished Aug 10 05:24:13 PM PDT 24
Peak memory 200376 kb
Host smart-92306d4f-7578-4728-8670-79d4de10e709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018675578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.rstmgr_sw_rst_reset_race.2018675578
Directory /workspace/0.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/1.rstmgr_alert_test.1280565169
Short name T378
Test name
Test status
Simulation time 69441085 ps
CPU time 0.76 seconds
Started Aug 10 05:24:16 PM PDT 24
Finished Aug 10 05:24:17 PM PDT 24
Peak memory 200152 kb
Host smart-49809bcc-ad0b-4132-b84d-57b68f9c5c90
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280565169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_alert_test.1280565169
Directory /workspace/1.rstmgr_alert_test/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_cnsty.1098546971
Short name T36
Test name
Test status
Simulation time 1896463163 ps
CPU time 7.78 seconds
Started Aug 10 05:24:02 PM PDT 24
Finished Aug 10 05:24:09 PM PDT 24
Peak memory 221708 kb
Host smart-b6a712ae-79d4-49e7-a8f3-c78394544246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098546971 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_cnsty.1098546971
Directory /workspace/1.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/1.rstmgr_leaf_rst_shadow_attack.2680494452
Short name T533
Test name
Test status
Simulation time 245816339 ps
CPU time 1.12 seconds
Started Aug 10 05:24:22 PM PDT 24
Finished Aug 10 05:24:23 PM PDT 24
Peak memory 217568 kb
Host smart-ad1eb20e-de9a-4c28-915d-6da1da0e10b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680494452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_leaf_rst_shadow_attack.2680494452
Directory /workspace/1.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/1.rstmgr_por_stretcher.3808385336
Short name T249
Test name
Test status
Simulation time 188249821 ps
CPU time 0.93 seconds
Started Aug 10 05:24:08 PM PDT 24
Finished Aug 10 05:24:09 PM PDT 24
Peak memory 200136 kb
Host smart-31c06dd0-3e8f-4b5a-b514-3ad56c3d9e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808385336 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_por_stretcher.3808385336
Directory /workspace/1.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/1.rstmgr_reset.39864946
Short name T240
Test name
Test status
Simulation time 961743735 ps
CPU time 4.92 seconds
Started Aug 10 05:24:22 PM PDT 24
Finished Aug 10 05:24:27 PM PDT 24
Peak memory 200576 kb
Host smart-bacc212b-bb3c-4205-8b6b-2f8ebf101074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39864946 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_reset.39864946
Directory /workspace/1.rstmgr_reset/latest

Test location /workspace/coverage/default/1.rstmgr_sec_cm_scan_intersig_mubi.2391532637
Short name T537
Test name
Test status
Simulation time 105063736 ps
CPU time 1.02 seconds
Started Aug 10 05:24:07 PM PDT 24
Finished Aug 10 05:24:08 PM PDT 24
Peak memory 200340 kb
Host smart-f7d6ff83-d9ed-4916-a6f7-95949bb471ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391532637 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sec_cm_scan_intersig_mubi.2391532637
Directory /workspace/1.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/1.rstmgr_smoke.1980781212
Short name T495
Test name
Test status
Simulation time 229359510 ps
CPU time 1.45 seconds
Started Aug 10 05:24:23 PM PDT 24
Finished Aug 10 05:24:24 PM PDT 24
Peak memory 200460 kb
Host smart-78d34c6a-7ccd-470b-af1f-069b9dba9fcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1980781212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_smoke.1980781212
Directory /workspace/1.rstmgr_smoke/latest

Test location /workspace/coverage/default/1.rstmgr_stress_all.208540327
Short name T91
Test name
Test status
Simulation time 6215998844 ps
CPU time 21.61 seconds
Started Aug 10 05:24:06 PM PDT 24
Finished Aug 10 05:24:28 PM PDT 24
Peak memory 209700 kb
Host smart-5b14aee4-1dd6-49e7-986e-f49a569203c0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208540327 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_stress_all.208540327
Directory /workspace/1.rstmgr_stress_all/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst.2558929827
Short name T400
Test name
Test status
Simulation time 342944650 ps
CPU time 2.27 seconds
Started Aug 10 05:24:03 PM PDT 24
Finished Aug 10 05:24:06 PM PDT 24
Peak memory 208472 kb
Host smart-576278e3-e5a3-4bae-9363-9ab556014891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2558929827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst.2558929827
Directory /workspace/1.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/1.rstmgr_sw_rst_reset_race.3908033315
Short name T474
Test name
Test status
Simulation time 129565048 ps
CPU time 1.06 seconds
Started Aug 10 05:24:08 PM PDT 24
Finished Aug 10 05:24:10 PM PDT 24
Peak memory 200336 kb
Host smart-98fd07ef-865d-4314-9b4c-e9e6daa6f0fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908033315 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.rstmgr_sw_rst_reset_race.3908033315
Directory /workspace/1.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/10.rstmgr_alert_test.2523213245
Short name T188
Test name
Test status
Simulation time 70481641 ps
CPU time 0.82 seconds
Started Aug 10 05:24:29 PM PDT 24
Finished Aug 10 05:24:30 PM PDT 24
Peak memory 200000 kb
Host smart-cb66aef7-9986-4ee4-9d6b-d162b43fa463
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523213245 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_alert_test.2523213245
Directory /workspace/10.rstmgr_alert_test/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_cnsty.4065827749
Short name T437
Test name
Test status
Simulation time 2363096148 ps
CPU time 8.54 seconds
Started Aug 10 05:24:31 PM PDT 24
Finished Aug 10 05:24:40 PM PDT 24
Peak memory 221832 kb
Host smart-c2a851be-7971-44c6-b502-3bf055908b39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4065827749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_cnsty.4065827749
Directory /workspace/10.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/10.rstmgr_leaf_rst_shadow_attack.3111923964
Short name T417
Test name
Test status
Simulation time 244399323 ps
CPU time 1.1 seconds
Started Aug 10 05:24:29 PM PDT 24
Finished Aug 10 05:24:31 PM PDT 24
Peak memory 217588 kb
Host smart-28ca694e-4123-46a7-94a7-a289156dffa2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111923964 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_leaf_rst_shadow_attack.3111923964
Directory /workspace/10.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/10.rstmgr_reset.1347199378
Short name T87
Test name
Test status
Simulation time 2248956959 ps
CPU time 7.84 seconds
Started Aug 10 05:24:25 PM PDT 24
Finished Aug 10 05:24:33 PM PDT 24
Peak memory 200612 kb
Host smart-cbbe5514-3c96-4833-8811-6e904958eb91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347199378 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_reset.1347199378
Directory /workspace/10.rstmgr_reset/latest

Test location /workspace/coverage/default/10.rstmgr_sec_cm_scan_intersig_mubi.2794078762
Short name T518
Test name
Test status
Simulation time 167277944 ps
CPU time 1.26 seconds
Started Aug 10 05:24:29 PM PDT 24
Finished Aug 10 05:24:30 PM PDT 24
Peak memory 200268 kb
Host smart-53f89350-318b-4ff7-b5e5-2263fc91fe1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794078762 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sec_cm_scan_intersig_mubi.2794078762
Directory /workspace/10.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/10.rstmgr_smoke.214688084
Short name T206
Test name
Test status
Simulation time 256414888 ps
CPU time 1.55 seconds
Started Aug 10 05:24:46 PM PDT 24
Finished Aug 10 05:24:48 PM PDT 24
Peak memory 200476 kb
Host smart-da510d56-1165-4223-9e8d-23e72809ec68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=214688084 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_smoke.214688084
Directory /workspace/10.rstmgr_smoke/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst.2124493815
Short name T133
Test name
Test status
Simulation time 462581528 ps
CPU time 2.48 seconds
Started Aug 10 05:24:34 PM PDT 24
Finished Aug 10 05:24:36 PM PDT 24
Peak memory 200188 kb
Host smart-4fd94f10-02ea-47f8-a859-8fda80387eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124493815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst.2124493815
Directory /workspace/10.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/10.rstmgr_sw_rst_reset_race.356901500
Short name T131
Test name
Test status
Simulation time 95438690 ps
CPU time 0.96 seconds
Started Aug 10 05:24:31 PM PDT 24
Finished Aug 10 05:24:32 PM PDT 24
Peak memory 200188 kb
Host smart-9dbb3c63-8e1e-422c-9ca7-98b97453c753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356901500 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.rstmgr_sw_rst_reset_race.356901500
Directory /workspace/10.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/11.rstmgr_alert_test.1075594713
Short name T352
Test name
Test status
Simulation time 66786082 ps
CPU time 0.83 seconds
Started Aug 10 05:24:18 PM PDT 24
Finished Aug 10 05:24:19 PM PDT 24
Peak memory 200052 kb
Host smart-76684429-c856-4c25-84ad-5d41d64fe0ef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075594713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_alert_test.1075594713
Directory /workspace/11.rstmgr_alert_test/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_cnsty.2570285240
Short name T334
Test name
Test status
Simulation time 1891168478 ps
CPU time 7.48 seconds
Started Aug 10 05:24:25 PM PDT 24
Finished Aug 10 05:24:33 PM PDT 24
Peak memory 221748 kb
Host smart-4cb48b5a-5074-4190-827f-74d0539ed6d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570285240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_cnsty.2570285240
Directory /workspace/11.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/11.rstmgr_leaf_rst_shadow_attack.2506068170
Short name T251
Test name
Test status
Simulation time 244697162 ps
CPU time 1.06 seconds
Started Aug 10 05:24:29 PM PDT 24
Finished Aug 10 05:24:31 PM PDT 24
Peak memory 217540 kb
Host smart-6eda72eb-e9ed-4f8f-ad87-30fa881f6794
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506068170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_leaf_rst_shadow_attack.2506068170
Directory /workspace/11.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/11.rstmgr_por_stretcher.2987446874
Short name T369
Test name
Test status
Simulation time 132823447 ps
CPU time 0.83 seconds
Started Aug 10 05:24:31 PM PDT 24
Finished Aug 10 05:24:32 PM PDT 24
Peak memory 200056 kb
Host smart-2645f78e-f836-4b09-8fca-006f3620ffff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987446874 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_por_stretcher.2987446874
Directory /workspace/11.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/11.rstmgr_reset.860793536
Short name T505
Test name
Test status
Simulation time 1188626818 ps
CPU time 4.82 seconds
Started Aug 10 05:24:52 PM PDT 24
Finished Aug 10 05:24:56 PM PDT 24
Peak memory 200552 kb
Host smart-598b03bc-870a-4d78-a5f6-d110fa4f012c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860793536 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_reset.860793536
Directory /workspace/11.rstmgr_reset/latest

Test location /workspace/coverage/default/11.rstmgr_smoke.771758359
Short name T242
Test name
Test status
Simulation time 120531388 ps
CPU time 1.22 seconds
Started Aug 10 05:24:26 PM PDT 24
Finished Aug 10 05:24:27 PM PDT 24
Peak memory 200504 kb
Host smart-a689a8fb-84a3-4239-8ae9-e58f36b28506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771758359 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_smoke.771758359
Directory /workspace/11.rstmgr_smoke/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst.2116100078
Short name T185
Test name
Test status
Simulation time 406402226 ps
CPU time 2.33 seconds
Started Aug 10 05:24:36 PM PDT 24
Finished Aug 10 05:24:38 PM PDT 24
Peak memory 200108 kb
Host smart-87444856-31d9-42f5-8dcc-5a2ddaef51e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116100078 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst.2116100078
Directory /workspace/11.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/11.rstmgr_sw_rst_reset_race.4209958313
Short name T272
Test name
Test status
Simulation time 138747906 ps
CPU time 1.17 seconds
Started Aug 10 05:24:28 PM PDT 24
Finished Aug 10 05:24:30 PM PDT 24
Peak memory 200352 kb
Host smart-f2fa6aec-e070-4aa6-9dbe-1eafd39f1577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4209958313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.rstmgr_sw_rst_reset_race.4209958313
Directory /workspace/11.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/12.rstmgr_alert_test.2913500885
Short name T214
Test name
Test status
Simulation time 84653899 ps
CPU time 0.84 seconds
Started Aug 10 05:24:32 PM PDT 24
Finished Aug 10 05:24:33 PM PDT 24
Peak memory 200152 kb
Host smart-af0b27e4-187e-4560-8a30-606c96471a8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913500885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_alert_test.2913500885
Directory /workspace/12.rstmgr_alert_test/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_cnsty.3120699020
Short name T273
Test name
Test status
Simulation time 1223924166 ps
CPU time 6.6 seconds
Started Aug 10 05:24:31 PM PDT 24
Finished Aug 10 05:24:38 PM PDT 24
Peak memory 221652 kb
Host smart-aa56918b-f271-44b1-9685-556d6e291b38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120699020 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_cnsty.3120699020
Directory /workspace/12.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/12.rstmgr_leaf_rst_shadow_attack.3688382628
Short name T508
Test name
Test status
Simulation time 245106746 ps
CPU time 1.03 seconds
Started Aug 10 05:24:30 PM PDT 24
Finished Aug 10 05:24:31 PM PDT 24
Peak memory 217516 kb
Host smart-1bb506aa-f360-487f-9d59-c46af80de7b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688382628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_leaf_rst_shadow_attack.3688382628
Directory /workspace/12.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/12.rstmgr_por_stretcher.1451394144
Short name T513
Test name
Test status
Simulation time 109440367 ps
CPU time 0.83 seconds
Started Aug 10 05:24:36 PM PDT 24
Finished Aug 10 05:24:37 PM PDT 24
Peak memory 200052 kb
Host smart-f22c29e5-21bc-4866-8059-77ea4b84d514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1451394144 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_por_stretcher.1451394144
Directory /workspace/12.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/12.rstmgr_reset.2160571382
Short name T459
Test name
Test status
Simulation time 1034866668 ps
CPU time 5.15 seconds
Started Aug 10 05:24:29 PM PDT 24
Finished Aug 10 05:24:34 PM PDT 24
Peak memory 200456 kb
Host smart-3ed5fc02-3bf8-46ff-b394-9c637cba6f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160571382 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_reset.2160571382
Directory /workspace/12.rstmgr_reset/latest

Test location /workspace/coverage/default/12.rstmgr_sec_cm_scan_intersig_mubi.3631700110
Short name T123
Test name
Test status
Simulation time 181414250 ps
CPU time 1.19 seconds
Started Aug 10 05:24:30 PM PDT 24
Finished Aug 10 05:24:31 PM PDT 24
Peak memory 200324 kb
Host smart-c032c5de-fb77-49b5-9451-2ce74a3e9547
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631700110 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sec_cm_scan_intersig_mubi.3631700110
Directory /workspace/12.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/12.rstmgr_smoke.1874695664
Short name T218
Test name
Test status
Simulation time 198041236 ps
CPU time 1.3 seconds
Started Aug 10 05:24:32 PM PDT 24
Finished Aug 10 05:24:33 PM PDT 24
Peak memory 200484 kb
Host smart-5b9017ae-db4f-43af-9605-6ad670a8241c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1874695664 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_smoke.1874695664
Directory /workspace/12.rstmgr_smoke/latest

Test location /workspace/coverage/default/12.rstmgr_stress_all.639442872
Short name T117
Test name
Test status
Simulation time 1482791183 ps
CPU time 6.01 seconds
Started Aug 10 05:24:27 PM PDT 24
Finished Aug 10 05:24:33 PM PDT 24
Peak memory 200424 kb
Host smart-a47e0ca6-d72a-498a-9bf7-3f37019901d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=639442872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_stress_all.639442872
Directory /workspace/12.rstmgr_stress_all/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst.613683548
Short name T464
Test name
Test status
Simulation time 157070194 ps
CPU time 1.91 seconds
Started Aug 10 05:24:29 PM PDT 24
Finished Aug 10 05:24:31 PM PDT 24
Peak memory 200308 kb
Host smart-de91b36d-270f-4b80-861e-ac2f46da7360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=613683548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst.613683548
Directory /workspace/12.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/12.rstmgr_sw_rst_reset_race.1474288628
Short name T454
Test name
Test status
Simulation time 186446472 ps
CPU time 1.28 seconds
Started Aug 10 05:24:32 PM PDT 24
Finished Aug 10 05:24:34 PM PDT 24
Peak memory 200304 kb
Host smart-6fe708da-641f-412a-8adf-0b0d177fef2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1474288628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.rstmgr_sw_rst_reset_race.1474288628
Directory /workspace/12.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/13.rstmgr_alert_test.3439870156
Short name T222
Test name
Test status
Simulation time 75611109 ps
CPU time 0.84 seconds
Started Aug 10 05:24:28 PM PDT 24
Finished Aug 10 05:24:29 PM PDT 24
Peak memory 200164 kb
Host smart-c92c9a11-ed6d-430c-9b80-c761f2d5115d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3439870156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_alert_test.3439870156
Directory /workspace/13.rstmgr_alert_test/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_cnsty.1731542476
Short name T414
Test name
Test status
Simulation time 2349300314 ps
CPU time 8.51 seconds
Started Aug 10 05:24:38 PM PDT 24
Finished Aug 10 05:24:47 PM PDT 24
Peak memory 217944 kb
Host smart-e64c19bb-8e10-48ee-832b-09c599bd7b30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731542476 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_cnsty.1731542476
Directory /workspace/13.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/13.rstmgr_leaf_rst_shadow_attack.3119559886
Short name T511
Test name
Test status
Simulation time 244787610 ps
CPU time 1.2 seconds
Started Aug 10 05:24:47 PM PDT 24
Finished Aug 10 05:24:49 PM PDT 24
Peak memory 217520 kb
Host smart-e66cb5e5-7bd0-4b08-919c-7111a0a2544e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3119559886 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_leaf_rst_shadow_attack.3119559886
Directory /workspace/13.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/13.rstmgr_por_stretcher.3763195860
Short name T375
Test name
Test status
Simulation time 156540364 ps
CPU time 0.84 seconds
Started Aug 10 05:24:33 PM PDT 24
Finished Aug 10 05:24:33 PM PDT 24
Peak memory 200184 kb
Host smart-9bdf175f-54a4-4cf0-9b78-cde45615e59c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3763195860 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_por_stretcher.3763195860
Directory /workspace/13.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/13.rstmgr_reset.2706855283
Short name T297
Test name
Test status
Simulation time 762081287 ps
CPU time 3.99 seconds
Started Aug 10 05:24:36 PM PDT 24
Finished Aug 10 05:24:40 PM PDT 24
Peak memory 200456 kb
Host smart-fecb2127-4a34-4990-b811-b414b51b27bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706855283 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_reset.2706855283
Directory /workspace/13.rstmgr_reset/latest

Test location /workspace/coverage/default/13.rstmgr_sec_cm_scan_intersig_mubi.2723928981
Short name T227
Test name
Test status
Simulation time 187651129 ps
CPU time 1.2 seconds
Started Aug 10 05:24:32 PM PDT 24
Finished Aug 10 05:24:33 PM PDT 24
Peak memory 200380 kb
Host smart-0dcfac73-3119-4ff0-8db1-971445b540a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2723928981 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sec_cm_scan_intersig_mubi.2723928981
Directory /workspace/13.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/13.rstmgr_smoke.1417572107
Short name T209
Test name
Test status
Simulation time 111653653 ps
CPU time 1.19 seconds
Started Aug 10 05:24:36 PM PDT 24
Finished Aug 10 05:24:38 PM PDT 24
Peak memory 200496 kb
Host smart-f72c36c3-cb90-4729-8898-459cfbfcd15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417572107 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_smoke.1417572107
Directory /workspace/13.rstmgr_smoke/latest

Test location /workspace/coverage/default/13.rstmgr_stress_all.1667880210
Short name T126
Test name
Test status
Simulation time 2344917766 ps
CPU time 9.65 seconds
Started Aug 10 05:24:29 PM PDT 24
Finished Aug 10 05:24:38 PM PDT 24
Peak memory 210092 kb
Host smart-14f84018-b6e6-496b-ab4f-5a4a899fe8ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667880210 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_stress_all.1667880210
Directory /workspace/13.rstmgr_stress_all/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst.107980178
Short name T203
Test name
Test status
Simulation time 124481652 ps
CPU time 1.66 seconds
Started Aug 10 05:24:35 PM PDT 24
Finished Aug 10 05:24:37 PM PDT 24
Peak memory 200244 kb
Host smart-e4518fe7-bc3a-4db5-9f9c-e3fc8fff9285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107980178 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst.107980178
Directory /workspace/13.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/13.rstmgr_sw_rst_reset_race.358127800
Short name T225
Test name
Test status
Simulation time 253415572 ps
CPU time 1.54 seconds
Started Aug 10 05:24:17 PM PDT 24
Finished Aug 10 05:24:18 PM PDT 24
Peak memory 200504 kb
Host smart-d1e5f03e-25e2-4409-a3aa-fa41618cc93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358127800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.rstmgr_sw_rst_reset_race.358127800
Directory /workspace/13.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/14.rstmgr_alert_test.2541992918
Short name T182
Test name
Test status
Simulation time 75484672 ps
CPU time 0.8 seconds
Started Aug 10 05:24:32 PM PDT 24
Finished Aug 10 05:24:33 PM PDT 24
Peak memory 200152 kb
Host smart-4c830152-da51-462d-81be-9ef4e80f6fd2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541992918 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_alert_test.2541992918
Directory /workspace/14.rstmgr_alert_test/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_cnsty.3026311263
Short name T26
Test name
Test status
Simulation time 1222042786 ps
CPU time 5.84 seconds
Started Aug 10 05:24:36 PM PDT 24
Finished Aug 10 05:24:42 PM PDT 24
Peak memory 217736 kb
Host smart-5298a536-b980-4514-b863-9c5ed5c94186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026311263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_cnsty.3026311263
Directory /workspace/14.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/14.rstmgr_leaf_rst_shadow_attack.2637553810
Short name T477
Test name
Test status
Simulation time 243910032 ps
CPU time 1.06 seconds
Started Aug 10 05:24:33 PM PDT 24
Finished Aug 10 05:24:34 PM PDT 24
Peak memory 217584 kb
Host smart-9fb7181f-0fac-4940-8027-d05eb7751c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2637553810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_leaf_rst_shadow_attack.2637553810
Directory /workspace/14.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/14.rstmgr_por_stretcher.2377321173
Short name T212
Test name
Test status
Simulation time 210539398 ps
CPU time 0.98 seconds
Started Aug 10 05:24:22 PM PDT 24
Finished Aug 10 05:24:24 PM PDT 24
Peak memory 200176 kb
Host smart-036c86db-df57-4975-8c0a-5a535e8ac35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377321173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_por_stretcher.2377321173
Directory /workspace/14.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/14.rstmgr_reset.2182086845
Short name T178
Test name
Test status
Simulation time 1063505068 ps
CPU time 5.52 seconds
Started Aug 10 05:24:31 PM PDT 24
Finished Aug 10 05:24:36 PM PDT 24
Peak memory 200560 kb
Host smart-c3566b52-3b62-4cf0-94b9-3fa23d2a7413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182086845 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_reset.2182086845
Directory /workspace/14.rstmgr_reset/latest

Test location /workspace/coverage/default/14.rstmgr_sec_cm_scan_intersig_mubi.111898096
Short name T463
Test name
Test status
Simulation time 147481371 ps
CPU time 1.1 seconds
Started Aug 10 05:24:30 PM PDT 24
Finished Aug 10 05:24:31 PM PDT 24
Peak memory 200248 kb
Host smart-1b85ace2-95db-4371-b3c0-7e5d4d6a9a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111898096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sec_cm_scan_intersig_mubi.111898096
Directory /workspace/14.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/14.rstmgr_smoke.2678107595
Short name T135
Test name
Test status
Simulation time 245493362 ps
CPU time 1.62 seconds
Started Aug 10 05:24:28 PM PDT 24
Finished Aug 10 05:24:30 PM PDT 24
Peak memory 200492 kb
Host smart-6660507c-64e3-4d29-baf8-d0688b91f511
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678107595 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_smoke.2678107595
Directory /workspace/14.rstmgr_smoke/latest

Test location /workspace/coverage/default/14.rstmgr_stress_all.2540448908
Short name T485
Test name
Test status
Simulation time 3447224497 ps
CPU time 16.51 seconds
Started Aug 10 05:24:37 PM PDT 24
Finished Aug 10 05:24:53 PM PDT 24
Peak memory 200524 kb
Host smart-f4675edb-aead-42ad-be8c-0aedd6530a96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540448908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_stress_all.2540448908
Directory /workspace/14.rstmgr_stress_all/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst.462161127
Short name T383
Test name
Test status
Simulation time 122330301 ps
CPU time 1.56 seconds
Started Aug 10 05:24:28 PM PDT 24
Finished Aug 10 05:24:29 PM PDT 24
Peak memory 200188 kb
Host smart-1d811463-06b3-42d4-ab44-10a8b7a8e450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462161127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst.462161127
Directory /workspace/14.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/14.rstmgr_sw_rst_reset_race.588122524
Short name T461
Test name
Test status
Simulation time 173247105 ps
CPU time 1.3 seconds
Started Aug 10 05:24:26 PM PDT 24
Finished Aug 10 05:24:28 PM PDT 24
Peak memory 200336 kb
Host smart-f882e665-7b46-47fe-976c-2554802e7a6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=588122524 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.rstmgr_sw_rst_reset_race.588122524
Directory /workspace/14.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/15.rstmgr_leaf_rst_cnsty.422471844
Short name T30
Test name
Test status
Simulation time 1898046419 ps
CPU time 6.82 seconds
Started Aug 10 05:24:32 PM PDT 24
Finished Aug 10 05:24:39 PM PDT 24
Peak memory 217360 kb
Host smart-23edc9b3-0fda-4f19-bb41-a1c7f23580d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422471844 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_leaf_rst_cnsty.422471844
Directory /workspace/15.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/15.rstmgr_por_stretcher.2650734421
Short name T366
Test name
Test status
Simulation time 91330800 ps
CPU time 0.74 seconds
Started Aug 10 05:24:30 PM PDT 24
Finished Aug 10 05:24:31 PM PDT 24
Peak memory 200004 kb
Host smart-3e367464-17de-4b55-be64-46cd63e1028b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650734421 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_por_stretcher.2650734421
Directory /workspace/15.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/15.rstmgr_reset.2272128497
Short name T90
Test name
Test status
Simulation time 1376083791 ps
CPU time 5.41 seconds
Started Aug 10 05:24:32 PM PDT 24
Finished Aug 10 05:24:38 PM PDT 24
Peak memory 200452 kb
Host smart-19c73208-d05d-43dc-9dc1-9ec379394ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2272128497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_reset.2272128497
Directory /workspace/15.rstmgr_reset/latest

Test location /workspace/coverage/default/15.rstmgr_sec_cm_scan_intersig_mubi.2897623228
Short name T447
Test name
Test status
Simulation time 141363467 ps
CPU time 1.06 seconds
Started Aug 10 05:24:28 PM PDT 24
Finished Aug 10 05:24:30 PM PDT 24
Peak memory 200200 kb
Host smart-69e68fad-271f-4f3f-aaf3-ac36e75a3784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897623228 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sec_cm_scan_intersig_mubi.2897623228
Directory /workspace/15.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/15.rstmgr_smoke.3335504455
Short name T205
Test name
Test status
Simulation time 258498280 ps
CPU time 1.61 seconds
Started Aug 10 05:24:30 PM PDT 24
Finished Aug 10 05:24:32 PM PDT 24
Peak memory 200496 kb
Host smart-be5a50e0-a1bf-4e29-adf7-cb8b4e776341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335504455 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_smoke.3335504455
Directory /workspace/15.rstmgr_smoke/latest

Test location /workspace/coverage/default/15.rstmgr_stress_all.37283650
Short name T263
Test name
Test status
Simulation time 5751150495 ps
CPU time 27.17 seconds
Started Aug 10 05:24:35 PM PDT 24
Finished Aug 10 05:25:03 PM PDT 24
Peak memory 200644 kb
Host smart-8cfcd49e-c82d-4361-96f0-f29ac746831a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37283650 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_stress_all.37283650
Directory /workspace/15.rstmgr_stress_all/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst.2864895494
Short name T402
Test name
Test status
Simulation time 335576706 ps
CPU time 2.16 seconds
Started Aug 10 05:24:39 PM PDT 24
Finished Aug 10 05:24:42 PM PDT 24
Peak memory 200184 kb
Host smart-9adab886-243d-4fea-98c5-6751627dbcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864895494 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst.2864895494
Directory /workspace/15.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/15.rstmgr_sw_rst_reset_race.1470057562
Short name T238
Test name
Test status
Simulation time 93661452 ps
CPU time 0.94 seconds
Started Aug 10 05:24:32 PM PDT 24
Finished Aug 10 05:24:33 PM PDT 24
Peak memory 200352 kb
Host smart-5aa9df55-2bff-41b6-a980-627c94886388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1470057562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.rstmgr_sw_rst_reset_race.1470057562
Directory /workspace/15.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/16.rstmgr_alert_test.1836963055
Short name T3
Test name
Test status
Simulation time 63650542 ps
CPU time 0.74 seconds
Started Aug 10 05:24:48 PM PDT 24
Finished Aug 10 05:24:48 PM PDT 24
Peak memory 200116 kb
Host smart-e69d9cc5-5b6b-41c4-82a8-3f0d9740b03f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836963055 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_alert_test.1836963055
Directory /workspace/16.rstmgr_alert_test/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_cnsty.49209924
Short name T354
Test name
Test status
Simulation time 1218200840 ps
CPU time 5.92 seconds
Started Aug 10 05:24:40 PM PDT 24
Finished Aug 10 05:24:47 PM PDT 24
Peak memory 217460 kb
Host smart-0d3e7b08-9102-45f1-b216-d8786662d198
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49209924 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_cnsty.49209924
Directory /workspace/16.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/16.rstmgr_leaf_rst_shadow_attack.1786637241
Short name T262
Test name
Test status
Simulation time 244484084 ps
CPU time 1.09 seconds
Started Aug 10 05:24:52 PM PDT 24
Finished Aug 10 05:24:53 PM PDT 24
Peak memory 217540 kb
Host smart-f159181a-3570-4f97-a1c4-e86245c6fbc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1786637241 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_leaf_rst_shadow_attack.1786637241
Directory /workspace/16.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/16.rstmgr_por_stretcher.628820497
Short name T472
Test name
Test status
Simulation time 92365012 ps
CPU time 0.75 seconds
Started Aug 10 05:24:41 PM PDT 24
Finished Aug 10 05:24:42 PM PDT 24
Peak memory 200132 kb
Host smart-765b51ed-37ab-4a29-8019-d003e0563b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628820497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_por_stretcher.628820497
Directory /workspace/16.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/16.rstmgr_reset.3795883642
Short name T473
Test name
Test status
Simulation time 1575036757 ps
CPU time 6.6 seconds
Started Aug 10 05:24:29 PM PDT 24
Finished Aug 10 05:24:36 PM PDT 24
Peak memory 200396 kb
Host smart-6f7b16bf-8c36-4093-ab25-87deb523d2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795883642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_reset.3795883642
Directory /workspace/16.rstmgr_reset/latest

Test location /workspace/coverage/default/16.rstmgr_sec_cm_scan_intersig_mubi.2096866435
Short name T504
Test name
Test status
Simulation time 108232732 ps
CPU time 1.01 seconds
Started Aug 10 05:24:35 PM PDT 24
Finished Aug 10 05:24:36 PM PDT 24
Peak memory 200308 kb
Host smart-77c85d5c-e793-4bc6-815c-5d45db2bc1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096866435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sec_cm_scan_intersig_mubi.2096866435
Directory /workspace/16.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/16.rstmgr_smoke.899907016
Short name T394
Test name
Test status
Simulation time 120064908 ps
CPU time 1.13 seconds
Started Aug 10 05:24:29 PM PDT 24
Finished Aug 10 05:24:30 PM PDT 24
Peak memory 200320 kb
Host smart-b28abbce-c8e0-43e1-a94c-78697a4530cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899907016 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_smoke.899907016
Directory /workspace/16.rstmgr_smoke/latest

Test location /workspace/coverage/default/16.rstmgr_stress_all.1054200465
Short name T470
Test name
Test status
Simulation time 9711974393 ps
CPU time 35.87 seconds
Started Aug 10 05:24:30 PM PDT 24
Finished Aug 10 05:25:06 PM PDT 24
Peak memory 208712 kb
Host smart-a73c0636-0b5c-4bde-83c9-42461fcc2301
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054200465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_stress_all.1054200465
Directory /workspace/16.rstmgr_stress_all/latest

Test location /workspace/coverage/default/16.rstmgr_sw_rst.3706060152
Short name T72
Test name
Test status
Simulation time 150278139 ps
CPU time 1.79 seconds
Started Aug 10 05:24:29 PM PDT 24
Finished Aug 10 05:24:31 PM PDT 24
Peak memory 200132 kb
Host smart-f21d1353-016b-4d64-ae67-52d428af494b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706060152 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.rstmgr_sw_rst.3706060152
Directory /workspace/16.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_alert_test.3249322698
Short name T536
Test name
Test status
Simulation time 83445779 ps
CPU time 0.78 seconds
Started Aug 10 05:24:48 PM PDT 24
Finished Aug 10 05:24:49 PM PDT 24
Peak memory 200028 kb
Host smart-d5672586-a5c8-4771-9153-b14e5dbedf41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249322698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_alert_test.3249322698
Directory /workspace/17.rstmgr_alert_test/latest

Test location /workspace/coverage/default/17.rstmgr_leaf_rst_shadow_attack.1367031159
Short name T208
Test name
Test status
Simulation time 245324042 ps
CPU time 1.03 seconds
Started Aug 10 05:24:33 PM PDT 24
Finished Aug 10 05:24:34 PM PDT 24
Peak memory 217524 kb
Host smart-c597c44a-a24a-4029-a428-5f426d0423e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367031159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_leaf_rst_shadow_attack.1367031159
Directory /workspace/17.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/17.rstmgr_por_stretcher.3667450751
Short name T455
Test name
Test status
Simulation time 199247103 ps
CPU time 0.88 seconds
Started Aug 10 05:25:06 PM PDT 24
Finished Aug 10 05:25:07 PM PDT 24
Peak memory 200140 kb
Host smart-c3c806b1-9738-42de-a530-2a00cb6efbfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667450751 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_por_stretcher.3667450751
Directory /workspace/17.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/17.rstmgr_reset.833151399
Short name T516
Test name
Test status
Simulation time 1748545407 ps
CPU time 6.93 seconds
Started Aug 10 05:24:39 PM PDT 24
Finished Aug 10 05:24:46 PM PDT 24
Peak memory 200536 kb
Host smart-b0490cff-1c27-4b75-905e-96831cbdb312
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833151399 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_reset.833151399
Directory /workspace/17.rstmgr_reset/latest

Test location /workspace/coverage/default/17.rstmgr_sec_cm_scan_intersig_mubi.1851551204
Short name T207
Test name
Test status
Simulation time 105954210 ps
CPU time 1 seconds
Started Aug 10 05:24:39 PM PDT 24
Finished Aug 10 05:24:40 PM PDT 24
Peak memory 200364 kb
Host smart-021c19d0-af6e-46f8-8177-e61aa3069b23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851551204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sec_cm_scan_intersig_mubi.1851551204
Directory /workspace/17.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/17.rstmgr_smoke.4099642482
Short name T446
Test name
Test status
Simulation time 233777201 ps
CPU time 1.45 seconds
Started Aug 10 05:24:40 PM PDT 24
Finished Aug 10 05:24:41 PM PDT 24
Peak memory 200376 kb
Host smart-5fc8018e-50df-4f66-815c-635a3e8a2560
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099642482 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_smoke.4099642482
Directory /workspace/17.rstmgr_smoke/latest

Test location /workspace/coverage/default/17.rstmgr_stress_all.662946952
Short name T386
Test name
Test status
Simulation time 2743680005 ps
CPU time 12.08 seconds
Started Aug 10 05:24:53 PM PDT 24
Finished Aug 10 05:25:05 PM PDT 24
Peak memory 200620 kb
Host smart-032b3c68-a68d-4e40-a728-ec96b302722c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662946952 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_stress_all.662946952
Directory /workspace/17.rstmgr_stress_all/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst.2788947560
Short name T149
Test name
Test status
Simulation time 351788267 ps
CPU time 2.23 seconds
Started Aug 10 05:24:31 PM PDT 24
Finished Aug 10 05:24:34 PM PDT 24
Peak memory 200120 kb
Host smart-03133478-7205-4355-b8c3-f626339380ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788947560 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst.2788947560
Directory /workspace/17.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/17.rstmgr_sw_rst_reset_race.3052319662
Short name T278
Test name
Test status
Simulation time 149124913 ps
CPU time 1.04 seconds
Started Aug 10 05:24:28 PM PDT 24
Finished Aug 10 05:24:30 PM PDT 24
Peak memory 200380 kb
Host smart-35a9872c-0713-4dfb-a7c1-cbc6171cc185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052319662 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.rstmgr_sw_rst_reset_race.3052319662
Directory /workspace/17.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/18.rstmgr_alert_test.3793973873
Short name T415
Test name
Test status
Simulation time 99873043 ps
CPU time 0.91 seconds
Started Aug 10 05:24:41 PM PDT 24
Finished Aug 10 05:24:42 PM PDT 24
Peak memory 200176 kb
Host smart-7b4c3b3e-aedd-4fcc-8403-ee7899603c05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3793973873 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_alert_test.3793973873
Directory /workspace/18.rstmgr_alert_test/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_cnsty.665747083
Short name T33
Test name
Test status
Simulation time 1233379760 ps
CPU time 5.56 seconds
Started Aug 10 05:24:34 PM PDT 24
Finished Aug 10 05:24:39 PM PDT 24
Peak memory 221580 kb
Host smart-539783cc-ac08-4bfe-864d-463e2f2eadef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665747083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_cnsty.665747083
Directory /workspace/18.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/18.rstmgr_leaf_rst_shadow_attack.3551745895
Short name T356
Test name
Test status
Simulation time 243913758 ps
CPU time 1.07 seconds
Started Aug 10 05:24:37 PM PDT 24
Finished Aug 10 05:24:38 PM PDT 24
Peak memory 217536 kb
Host smart-38c04a96-8ea3-4d8a-b839-0bd131188fa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551745895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_leaf_rst_shadow_attack.3551745895
Directory /workspace/18.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/18.rstmgr_por_stretcher.1215832885
Short name T353
Test name
Test status
Simulation time 172238497 ps
CPU time 0.91 seconds
Started Aug 10 05:24:31 PM PDT 24
Finished Aug 10 05:24:32 PM PDT 24
Peak memory 200236 kb
Host smart-30e9b0f5-365a-4ca4-970b-21b7ca2f8d2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1215832885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_por_stretcher.1215832885
Directory /workspace/18.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/18.rstmgr_reset.2841306802
Short name T512
Test name
Test status
Simulation time 1742202122 ps
CPU time 6.83 seconds
Started Aug 10 05:24:34 PM PDT 24
Finished Aug 10 05:24:41 PM PDT 24
Peak memory 200532 kb
Host smart-c81f5638-9d62-4968-b9d3-c6d1f0354b86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841306802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_reset.2841306802
Directory /workspace/18.rstmgr_reset/latest

Test location /workspace/coverage/default/18.rstmgr_sec_cm_scan_intersig_mubi.3408674868
Short name T398
Test name
Test status
Simulation time 155665450 ps
CPU time 1.18 seconds
Started Aug 10 05:24:46 PM PDT 24
Finished Aug 10 05:24:47 PM PDT 24
Peak memory 200436 kb
Host smart-ae3d7760-fd91-4d25-a461-a302d70efd5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3408674868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sec_cm_scan_intersig_mubi.3408674868
Directory /workspace/18.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/18.rstmgr_smoke.2447975753
Short name T367
Test name
Test status
Simulation time 119780750 ps
CPU time 1.21 seconds
Started Aug 10 05:24:32 PM PDT 24
Finished Aug 10 05:24:33 PM PDT 24
Peak memory 200468 kb
Host smart-c387849c-5d5a-4dba-9dbc-f7d43a038470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447975753 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_smoke.2447975753
Directory /workspace/18.rstmgr_smoke/latest

Test location /workspace/coverage/default/18.rstmgr_stress_all.1000759842
Short name T486
Test name
Test status
Simulation time 4387351371 ps
CPU time 16.87 seconds
Started Aug 10 05:24:34 PM PDT 24
Finished Aug 10 05:24:51 PM PDT 24
Peak memory 200480 kb
Host smart-ba4af030-1760-46d5-9d99-9e67f6246857
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000759842 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_stress_all.1000759842
Directory /workspace/18.rstmgr_stress_all/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst.1599747857
Short name T295
Test name
Test status
Simulation time 361274734 ps
CPU time 2.27 seconds
Started Aug 10 05:24:38 PM PDT 24
Finished Aug 10 05:24:40 PM PDT 24
Peak memory 200256 kb
Host smart-3847e5e0-01ee-475d-a8d2-1d0e61325522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1599747857 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst.1599747857
Directory /workspace/18.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/18.rstmgr_sw_rst_reset_race.761079684
Short name T220
Test name
Test status
Simulation time 157566697 ps
CPU time 1.23 seconds
Started Aug 10 05:24:33 PM PDT 24
Finished Aug 10 05:24:35 PM PDT 24
Peak memory 200464 kb
Host smart-2dc717bd-9426-44ca-ab9d-c78738b79896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761079684 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.rstmgr_sw_rst_reset_race.761079684
Directory /workspace/18.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/19.rstmgr_alert_test.3138543628
Short name T59
Test name
Test status
Simulation time 70662526 ps
CPU time 0.81 seconds
Started Aug 10 05:24:34 PM PDT 24
Finished Aug 10 05:24:35 PM PDT 24
Peak memory 200120 kb
Host smart-a1a3a309-bd34-4d54-9388-c86ed50db0c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3138543628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_alert_test.3138543628
Directory /workspace/19.rstmgr_alert_test/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_cnsty.1226879604
Short name T10
Test name
Test status
Simulation time 1883339700 ps
CPU time 7.78 seconds
Started Aug 10 05:24:27 PM PDT 24
Finished Aug 10 05:24:35 PM PDT 24
Peak memory 217544 kb
Host smart-f54d094b-5f43-4548-824b-33748fd43051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226879604 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_cnsty.1226879604
Directory /workspace/19.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/19.rstmgr_leaf_rst_shadow_attack.2506507305
Short name T69
Test name
Test status
Simulation time 244745022 ps
CPU time 1.05 seconds
Started Aug 10 05:24:29 PM PDT 24
Finished Aug 10 05:24:30 PM PDT 24
Peak memory 217524 kb
Host smart-1bb5d62f-5cab-4552-b7e7-da6c85ddcbee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506507305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_leaf_rst_shadow_attack.2506507305
Directory /workspace/19.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/19.rstmgr_por_stretcher.194100642
Short name T274
Test name
Test status
Simulation time 99951496 ps
CPU time 0.77 seconds
Started Aug 10 05:24:30 PM PDT 24
Finished Aug 10 05:24:31 PM PDT 24
Peak memory 200148 kb
Host smart-eb7900d8-1045-4c14-9463-2fdc2ff8bac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194100642 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_por_stretcher.194100642
Directory /workspace/19.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/19.rstmgr_reset.3391049653
Short name T112
Test name
Test status
Simulation time 1572372668 ps
CPU time 5.96 seconds
Started Aug 10 05:24:33 PM PDT 24
Finished Aug 10 05:24:39 PM PDT 24
Peak memory 200596 kb
Host smart-2d9ab226-e0b6-497b-a6a3-aeb07f785b61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391049653 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_reset.3391049653
Directory /workspace/19.rstmgr_reset/latest

Test location /workspace/coverage/default/19.rstmgr_sec_cm_scan_intersig_mubi.990153335
Short name T236
Test name
Test status
Simulation time 103871323 ps
CPU time 1.04 seconds
Started Aug 10 05:24:28 PM PDT 24
Finished Aug 10 05:24:29 PM PDT 24
Peak memory 200332 kb
Host smart-5fddd371-db35-4771-acfd-c335128fd367
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990153335 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sec_cm_scan_intersig_mubi.990153335
Directory /workspace/19.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/19.rstmgr_smoke.2600682957
Short name T346
Test name
Test status
Simulation time 254774270 ps
CPU time 1.59 seconds
Started Aug 10 05:24:33 PM PDT 24
Finished Aug 10 05:24:35 PM PDT 24
Peak memory 200368 kb
Host smart-aa1e98a1-4603-46f7-9e92-05c67122d2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600682957 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_smoke.2600682957
Directory /workspace/19.rstmgr_smoke/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst.2277317111
Short name T147
Test name
Test status
Simulation time 148373618 ps
CPU time 1.82 seconds
Started Aug 10 05:24:32 PM PDT 24
Finished Aug 10 05:24:34 PM PDT 24
Peak memory 200276 kb
Host smart-39e5d08f-9ea9-4aed-9f78-a353bde2b82b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277317111 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst.2277317111
Directory /workspace/19.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/19.rstmgr_sw_rst_reset_race.2453284632
Short name T285
Test name
Test status
Simulation time 64202087 ps
CPU time 0.75 seconds
Started Aug 10 05:24:41 PM PDT 24
Finished Aug 10 05:24:42 PM PDT 24
Peak memory 200364 kb
Host smart-74c08ad1-e961-41a8-88d0-db4fc3a8c120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453284632 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.rstmgr_sw_rst_reset_race.2453284632
Directory /workspace/19.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/2.rstmgr_alert_test.2092817260
Short name T313
Test name
Test status
Simulation time 89450940 ps
CPU time 0.85 seconds
Started Aug 10 05:24:07 PM PDT 24
Finished Aug 10 05:24:09 PM PDT 24
Peak memory 200340 kb
Host smart-cb8905c4-c256-4e26-aa75-52e12c1a4d64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092817260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_alert_test.2092817260
Directory /workspace/2.rstmgr_alert_test/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_cnsty.2662351810
Short name T443
Test name
Test status
Simulation time 1229574216 ps
CPU time 5.41 seconds
Started Aug 10 05:24:08 PM PDT 24
Finished Aug 10 05:24:14 PM PDT 24
Peak memory 221672 kb
Host smart-7ccadf74-f7d9-40ca-ad8e-b373d861b87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662351810 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_cnsty.2662351810
Directory /workspace/2.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/2.rstmgr_leaf_rst_shadow_attack.3071189997
Short name T358
Test name
Test status
Simulation time 245984279 ps
CPU time 1.07 seconds
Started Aug 10 05:24:10 PM PDT 24
Finished Aug 10 05:24:11 PM PDT 24
Peak memory 217504 kb
Host smart-9c32db9b-31ba-4e69-86c5-18c880929c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071189997 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_leaf_rst_shadow_attack.3071189997
Directory /workspace/2.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/2.rstmgr_por_stretcher.3159035757
Short name T176
Test name
Test status
Simulation time 128406901 ps
CPU time 0.78 seconds
Started Aug 10 05:24:04 PM PDT 24
Finished Aug 10 05:24:05 PM PDT 24
Peak memory 200036 kb
Host smart-db53e554-d17f-4337-841a-36ede0c48fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159035757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_por_stretcher.3159035757
Directory /workspace/2.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/2.rstmgr_reset.3810113995
Short name T269
Test name
Test status
Simulation time 754292214 ps
CPU time 4.18 seconds
Started Aug 10 05:24:06 PM PDT 24
Finished Aug 10 05:24:10 PM PDT 24
Peak memory 200544 kb
Host smart-7edf727c-c1f0-4d5e-8147-9f192071e728
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810113995 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_reset.3810113995
Directory /workspace/2.rstmgr_reset/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm.2117958290
Short name T49
Test name
Test status
Simulation time 16785156209 ps
CPU time 24.88 seconds
Started Aug 10 05:24:09 PM PDT 24
Finished Aug 10 05:24:34 PM PDT 24
Peak memory 217616 kb
Host smart-71bff444-fb7e-4890-aede-c7f4f87a29bb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117958290 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm.2117958290
Directory /workspace/2.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/2.rstmgr_sec_cm_scan_intersig_mubi.2425256387
Short name T260
Test name
Test status
Simulation time 113323702 ps
CPU time 1.07 seconds
Started Aug 10 05:24:08 PM PDT 24
Finished Aug 10 05:24:10 PM PDT 24
Peak memory 200368 kb
Host smart-02c39175-51e0-4997-aee2-8678797e737d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425256387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sec_cm_scan_intersig_mubi.2425256387
Directory /workspace/2.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/2.rstmgr_smoke.2835991565
Short name T488
Test name
Test status
Simulation time 123992013 ps
CPU time 1.25 seconds
Started Aug 10 05:24:09 PM PDT 24
Finished Aug 10 05:24:10 PM PDT 24
Peak memory 200468 kb
Host smart-cbcab1f4-cfee-4d01-b0aa-a29120a09b1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835991565 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_smoke.2835991565
Directory /workspace/2.rstmgr_smoke/latest

Test location /workspace/coverage/default/2.rstmgr_stress_all.1570711403
Short name T286
Test name
Test status
Simulation time 6091253227 ps
CPU time 21.5 seconds
Started Aug 10 05:24:11 PM PDT 24
Finished Aug 10 05:24:33 PM PDT 24
Peak memory 208828 kb
Host smart-ca5d1957-4f1a-4754-a8fd-5c9bb30c2f07
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1570711403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_stress_all.1570711403
Directory /workspace/2.rstmgr_stress_all/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst.447711273
Short name T292
Test name
Test status
Simulation time 111452401 ps
CPU time 1.42 seconds
Started Aug 10 05:24:13 PM PDT 24
Finished Aug 10 05:24:15 PM PDT 24
Peak memory 200180 kb
Host smart-aedc41d4-a0ed-4501-832f-59804895f195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447711273 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst.447711273
Directory /workspace/2.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/2.rstmgr_sw_rst_reset_race.68254559
Short name T171
Test name
Test status
Simulation time 64823210 ps
CPU time 0.74 seconds
Started Aug 10 05:24:04 PM PDT 24
Finished Aug 10 05:24:05 PM PDT 24
Peak memory 200232 kb
Host smart-0cf4253e-6ac4-40c8-b864-751c51c05df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68254559 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.rstmgr_sw_rst_reset_race.68254559
Directory /workspace/2.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/20.rstmgr_alert_test.3644969534
Short name T382
Test name
Test status
Simulation time 67863748 ps
CPU time 0.74 seconds
Started Aug 10 05:24:44 PM PDT 24
Finished Aug 10 05:24:44 PM PDT 24
Peak memory 200152 kb
Host smart-3f23e46f-1033-4afe-8b02-73052318c9e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644969534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_alert_test.3644969534
Directory /workspace/20.rstmgr_alert_test/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_cnsty.3098794354
Short name T290
Test name
Test status
Simulation time 1224000949 ps
CPU time 5.81 seconds
Started Aug 10 05:24:30 PM PDT 24
Finished Aug 10 05:24:36 PM PDT 24
Peak memory 217740 kb
Host smart-c4a5c8c2-b545-40f1-9adc-f73bbbcf055a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098794354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_cnsty.3098794354
Directory /workspace/20.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/20.rstmgr_leaf_rst_shadow_attack.1172501306
Short name T230
Test name
Test status
Simulation time 244363548 ps
CPU time 1.06 seconds
Started Aug 10 05:24:31 PM PDT 24
Finished Aug 10 05:24:32 PM PDT 24
Peak memory 217448 kb
Host smart-6ae26afb-5a9e-4e03-ae88-bc6331220153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172501306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_leaf_rst_shadow_attack.1172501306
Directory /workspace/20.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/20.rstmgr_por_stretcher.348340601
Short name T14
Test name
Test status
Simulation time 155410041 ps
CPU time 0.84 seconds
Started Aug 10 05:24:46 PM PDT 24
Finished Aug 10 05:24:47 PM PDT 24
Peak memory 200344 kb
Host smart-5a90431c-a648-4624-8b40-9cbc72e85c74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348340601 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_por_stretcher.348340601
Directory /workspace/20.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/20.rstmgr_reset.429112868
Short name T264
Test name
Test status
Simulation time 840278960 ps
CPU time 4.17 seconds
Started Aug 10 05:24:30 PM PDT 24
Finished Aug 10 05:24:34 PM PDT 24
Peak memory 200556 kb
Host smart-4e26764a-59af-4248-8256-6558267f1085
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429112868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_reset.429112868
Directory /workspace/20.rstmgr_reset/latest

Test location /workspace/coverage/default/20.rstmgr_sec_cm_scan_intersig_mubi.2495562015
Short name T315
Test name
Test status
Simulation time 109249961 ps
CPU time 1.02 seconds
Started Aug 10 05:24:46 PM PDT 24
Finished Aug 10 05:24:47 PM PDT 24
Peak memory 200364 kb
Host smart-6b0a50ed-4595-43ea-a69b-6d2e0fcfdbe0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495562015 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sec_cm_scan_intersig_mubi.2495562015
Directory /workspace/20.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/20.rstmgr_smoke.802529779
Short name T500
Test name
Test status
Simulation time 190993555 ps
CPU time 1.45 seconds
Started Aug 10 05:24:28 PM PDT 24
Finished Aug 10 05:24:30 PM PDT 24
Peak memory 200376 kb
Host smart-b1ba8821-db5b-486a-98a3-c5c0313bae51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802529779 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_smoke.802529779
Directory /workspace/20.rstmgr_smoke/latest

Test location /workspace/coverage/default/20.rstmgr_stress_all.1143595156
Short name T71
Test name
Test status
Simulation time 2859880609 ps
CPU time 11.66 seconds
Started Aug 10 05:24:37 PM PDT 24
Finished Aug 10 05:24:49 PM PDT 24
Peak memory 200640 kb
Host smart-971abbe7-36f8-4162-8e3b-000f0dd596ba
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1143595156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_stress_all.1143595156
Directory /workspace/20.rstmgr_stress_all/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst.668947611
Short name T130
Test name
Test status
Simulation time 364031984 ps
CPU time 2.09 seconds
Started Aug 10 05:24:30 PM PDT 24
Finished Aug 10 05:24:32 PM PDT 24
Peak memory 200300 kb
Host smart-ce2e73fc-9445-46b9-aadc-6d9a8d09c3b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668947611 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst.668947611
Directory /workspace/20.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/20.rstmgr_sw_rst_reset_race.1452933648
Short name T215
Test name
Test status
Simulation time 234314834 ps
CPU time 1.37 seconds
Started Aug 10 05:24:34 PM PDT 24
Finished Aug 10 05:24:35 PM PDT 24
Peak memory 200244 kb
Host smart-528232d0-ccf8-4aa6-94e4-35cb2a1a07f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452933648 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.rstmgr_sw_rst_reset_race.1452933648
Directory /workspace/20.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/21.rstmgr_alert_test.1542369698
Short name T173
Test name
Test status
Simulation time 80789432 ps
CPU time 0.81 seconds
Started Aug 10 05:24:34 PM PDT 24
Finished Aug 10 05:24:35 PM PDT 24
Peak memory 200008 kb
Host smart-0031ba27-e72a-46d3-8697-36c78f8939e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542369698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_alert_test.1542369698
Directory /workspace/21.rstmgr_alert_test/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_cnsty.1461229714
Short name T283
Test name
Test status
Simulation time 2365216363 ps
CPU time 8.97 seconds
Started Aug 10 05:24:33 PM PDT 24
Finished Aug 10 05:24:43 PM PDT 24
Peak memory 217576 kb
Host smart-8d43c5f3-bfac-4219-a300-931296c4822f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1461229714 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_cnsty.1461229714
Directory /workspace/21.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/21.rstmgr_leaf_rst_shadow_attack.4108700535
Short name T233
Test name
Test status
Simulation time 244655598 ps
CPU time 1.12 seconds
Started Aug 10 05:24:34 PM PDT 24
Finished Aug 10 05:24:35 PM PDT 24
Peak memory 217520 kb
Host smart-9416b3ce-c08f-4f70-9dad-ef34d1df6dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4108700535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_leaf_rst_shadow_attack.4108700535
Directory /workspace/21.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/21.rstmgr_por_stretcher.2831410869
Short name T328
Test name
Test status
Simulation time 118036534 ps
CPU time 0.85 seconds
Started Aug 10 05:24:36 PM PDT 24
Finished Aug 10 05:24:37 PM PDT 24
Peak memory 200028 kb
Host smart-cdfc67ce-60c6-4e63-b4f8-82fd0e3f75d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831410869 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_por_stretcher.2831410869
Directory /workspace/21.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/21.rstmgr_reset.2154218026
Short name T190
Test name
Test status
Simulation time 907784092 ps
CPU time 4.3 seconds
Started Aug 10 05:24:33 PM PDT 24
Finished Aug 10 05:24:37 PM PDT 24
Peak memory 200616 kb
Host smart-b008a283-f9d0-468b-9ebc-0b26202fcce1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154218026 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_reset.2154218026
Directory /workspace/21.rstmgr_reset/latest

Test location /workspace/coverage/default/21.rstmgr_sec_cm_scan_intersig_mubi.3338070388
Short name T250
Test name
Test status
Simulation time 111359279 ps
CPU time 1.01 seconds
Started Aug 10 05:25:02 PM PDT 24
Finished Aug 10 05:25:03 PM PDT 24
Peak memory 200308 kb
Host smart-85359c34-04bc-41b8-b0d3-aaae13ad5f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3338070388 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sec_cm_scan_intersig_mubi.3338070388
Directory /workspace/21.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/21.rstmgr_smoke.3440953218
Short name T156
Test name
Test status
Simulation time 255580263 ps
CPU time 1.46 seconds
Started Aug 10 05:24:48 PM PDT 24
Finished Aug 10 05:24:49 PM PDT 24
Peak memory 200512 kb
Host smart-38f0d5e5-f8fc-409b-b293-fcc9a53f3a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440953218 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_smoke.3440953218
Directory /workspace/21.rstmgr_smoke/latest

Test location /workspace/coverage/default/21.rstmgr_stress_all.3144153548
Short name T532
Test name
Test status
Simulation time 1525843008 ps
CPU time 6.57 seconds
Started Aug 10 05:24:41 PM PDT 24
Finished Aug 10 05:24:48 PM PDT 24
Peak memory 200544 kb
Host smart-922e11fd-b3dd-4165-aeb7-7ab66a9bfaaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144153548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_stress_all.3144153548
Directory /workspace/21.rstmgr_stress_all/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst.2886585333
Short name T476
Test name
Test status
Simulation time 121406158 ps
CPU time 1.59 seconds
Started Aug 10 05:24:30 PM PDT 24
Finished Aug 10 05:24:32 PM PDT 24
Peak memory 208476 kb
Host smart-f1c9a0bc-c992-48c4-89e9-f38fc70ec4f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886585333 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst.2886585333
Directory /workspace/21.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/21.rstmgr_sw_rst_reset_race.1108330068
Short name T514
Test name
Test status
Simulation time 154858348 ps
CPU time 1.33 seconds
Started Aug 10 05:24:33 PM PDT 24
Finished Aug 10 05:24:35 PM PDT 24
Peak memory 200676 kb
Host smart-9b8ac7f4-0649-47f1-b143-943cbbb7d3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1108330068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.rstmgr_sw_rst_reset_race.1108330068
Directory /workspace/21.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/22.rstmgr_alert_test.654547293
Short name T338
Test name
Test status
Simulation time 76831092 ps
CPU time 0.79 seconds
Started Aug 10 05:24:35 PM PDT 24
Finished Aug 10 05:24:36 PM PDT 24
Peak memory 200148 kb
Host smart-36dedd25-4db4-4e87-a8f1-e3608d789a2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654547293 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_alert_test.654547293
Directory /workspace/22.rstmgr_alert_test/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_cnsty.2813405681
Short name T229
Test name
Test status
Simulation time 2393599194 ps
CPU time 8.45 seconds
Started Aug 10 05:24:53 PM PDT 24
Finished Aug 10 05:25:01 PM PDT 24
Peak memory 217524 kb
Host smart-c63d02f5-f2fb-4011-a5dd-7a3aca33b325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813405681 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_cnsty.2813405681
Directory /workspace/22.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/22.rstmgr_leaf_rst_shadow_attack.2831391802
Short name T167
Test name
Test status
Simulation time 244741054 ps
CPU time 1.05 seconds
Started Aug 10 05:24:30 PM PDT 24
Finished Aug 10 05:24:32 PM PDT 24
Peak memory 217524 kb
Host smart-8c045260-427b-4600-9960-9ae3eac77b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831391802 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_leaf_rst_shadow_attack.2831391802
Directory /workspace/22.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/22.rstmgr_por_stretcher.3448380657
Short name T150
Test name
Test status
Simulation time 220109036 ps
CPU time 0.93 seconds
Started Aug 10 05:24:29 PM PDT 24
Finished Aug 10 05:24:31 PM PDT 24
Peak memory 200148 kb
Host smart-6d7a66b2-7bc1-48a8-acdb-d8f836fe0111
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3448380657 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_por_stretcher.3448380657
Directory /workspace/22.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/22.rstmgr_reset.83133263
Short name T86
Test name
Test status
Simulation time 1007166137 ps
CPU time 4.29 seconds
Started Aug 10 05:24:36 PM PDT 24
Finished Aug 10 05:24:41 PM PDT 24
Peak memory 200508 kb
Host smart-a31c4940-d936-4f44-871b-d9544f93476d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83133263 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_reset.83133263
Directory /workspace/22.rstmgr_reset/latest

Test location /workspace/coverage/default/22.rstmgr_sec_cm_scan_intersig_mubi.117546045
Short name T302
Test name
Test status
Simulation time 152624460 ps
CPU time 1.08 seconds
Started Aug 10 05:24:33 PM PDT 24
Finished Aug 10 05:24:35 PM PDT 24
Peak memory 200108 kb
Host smart-c1499383-ddb5-455b-9928-5c0228976fe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117546045 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sec_cm_scan_intersig_mubi.117546045
Directory /workspace/22.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/22.rstmgr_smoke.1823999620
Short name T300
Test name
Test status
Simulation time 260946615 ps
CPU time 1.54 seconds
Started Aug 10 05:24:30 PM PDT 24
Finished Aug 10 05:24:32 PM PDT 24
Peak memory 200484 kb
Host smart-8fb0c9df-604f-4f4b-afa3-78d3195db412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823999620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_smoke.1823999620
Directory /workspace/22.rstmgr_smoke/latest

Test location /workspace/coverage/default/22.rstmgr_stress_all.777004215
Short name T166
Test name
Test status
Simulation time 7437849855 ps
CPU time 33.55 seconds
Started Aug 10 05:24:33 PM PDT 24
Finished Aug 10 05:25:07 PM PDT 24
Peak memory 200436 kb
Host smart-99bf764c-9ffd-4679-8250-e8bb3f817a1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777004215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_stress_all.777004215
Directory /workspace/22.rstmgr_stress_all/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst.1017859346
Short name T507
Test name
Test status
Simulation time 244950561 ps
CPU time 1.82 seconds
Started Aug 10 05:24:39 PM PDT 24
Finished Aug 10 05:24:41 PM PDT 24
Peak memory 200244 kb
Host smart-b5a89ed2-0109-498d-9178-4f7b1153d6a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1017859346 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst.1017859346
Directory /workspace/22.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/22.rstmgr_sw_rst_reset_race.906919446
Short name T124
Test name
Test status
Simulation time 136787355 ps
CPU time 1.07 seconds
Started Aug 10 05:24:33 PM PDT 24
Finished Aug 10 05:24:34 PM PDT 24
Peak memory 200356 kb
Host smart-8fe95fda-07c8-4e35-b87e-a85601c7ca7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906919446 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.rstmgr_sw_rst_reset_race.906919446
Directory /workspace/22.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/23.rstmgr_alert_test.2923676090
Short name T432
Test name
Test status
Simulation time 61110148 ps
CPU time 0.77 seconds
Started Aug 10 05:24:33 PM PDT 24
Finished Aug 10 05:24:34 PM PDT 24
Peak memory 199984 kb
Host smart-0673da01-ff9d-4dd0-880d-077c931dc984
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2923676090 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_alert_test.2923676090
Directory /workspace/23.rstmgr_alert_test/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_cnsty.3664714625
Short name T27
Test name
Test status
Simulation time 1894887562 ps
CPU time 7.75 seconds
Started Aug 10 05:24:46 PM PDT 24
Finished Aug 10 05:24:54 PM PDT 24
Peak memory 217404 kb
Host smart-2c36c45c-8569-48fd-a12a-7b52f8eb4a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664714625 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_cnsty.3664714625
Directory /workspace/23.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/23.rstmgr_leaf_rst_shadow_attack.3823432535
Short name T503
Test name
Test status
Simulation time 243406602 ps
CPU time 1.11 seconds
Started Aug 10 05:24:51 PM PDT 24
Finished Aug 10 05:24:52 PM PDT 24
Peak memory 217596 kb
Host smart-69fd86b0-9326-44a9-951f-04ccc771e0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823432535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_leaf_rst_shadow_attack.3823432535
Directory /workspace/23.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/23.rstmgr_por_stretcher.875744974
Short name T20
Test name
Test status
Simulation time 73540307 ps
CPU time 0.72 seconds
Started Aug 10 05:24:28 PM PDT 24
Finished Aug 10 05:24:29 PM PDT 24
Peak memory 199984 kb
Host smart-84198401-82df-4763-a653-31e0f3809f3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=875744974 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_por_stretcher.875744974
Directory /workspace/23.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/23.rstmgr_reset.2877831024
Short name T487
Test name
Test status
Simulation time 1140738593 ps
CPU time 4.83 seconds
Started Aug 10 05:24:40 PM PDT 24
Finished Aug 10 05:24:44 PM PDT 24
Peak memory 200400 kb
Host smart-1298a7ca-096e-49b8-ad02-949c8e5ec730
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877831024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_reset.2877831024
Directory /workspace/23.rstmgr_reset/latest

Test location /workspace/coverage/default/23.rstmgr_sec_cm_scan_intersig_mubi.1512298990
Short name T374
Test name
Test status
Simulation time 183788996 ps
CPU time 1.28 seconds
Started Aug 10 05:24:35 PM PDT 24
Finished Aug 10 05:24:36 PM PDT 24
Peak memory 200364 kb
Host smart-1b9d5c5f-fb7c-4e62-bc0e-bb451a62b7a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512298990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sec_cm_scan_intersig_mubi.1512298990
Directory /workspace/23.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/23.rstmgr_smoke.1239434765
Short name T183
Test name
Test status
Simulation time 246535951 ps
CPU time 1.63 seconds
Started Aug 10 05:24:33 PM PDT 24
Finished Aug 10 05:24:35 PM PDT 24
Peak memory 200472 kb
Host smart-3077e877-6cad-4851-a909-c7624a5d0fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239434765 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_smoke.1239434765
Directory /workspace/23.rstmgr_smoke/latest

Test location /workspace/coverage/default/23.rstmgr_stress_all.1446807591
Short name T169
Test name
Test status
Simulation time 2483382996 ps
CPU time 10.56 seconds
Started Aug 10 05:24:49 PM PDT 24
Finished Aug 10 05:25:00 PM PDT 24
Peak memory 209284 kb
Host smart-4232c93e-2786-4c06-b9a4-e75ddd155ab4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446807591 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_stress_all.1446807591
Directory /workspace/23.rstmgr_stress_all/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst.2823607656
Short name T287
Test name
Test status
Simulation time 129122291 ps
CPU time 1.57 seconds
Started Aug 10 05:24:30 PM PDT 24
Finished Aug 10 05:24:32 PM PDT 24
Peak memory 200148 kb
Host smart-fcc92bd3-9692-45d0-ada7-a462f38cb993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823607656 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst.2823607656
Directory /workspace/23.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/23.rstmgr_sw_rst_reset_race.957490614
Short name T254
Test name
Test status
Simulation time 243250006 ps
CPU time 1.46 seconds
Started Aug 10 05:24:37 PM PDT 24
Finished Aug 10 05:24:39 PM PDT 24
Peak memory 200388 kb
Host smart-76da640a-7aa4-419d-aa42-ce762af11da8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957490614 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.rstmgr_sw_rst_reset_race.957490614
Directory /workspace/23.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/24.rstmgr_alert_test.1268135052
Short name T284
Test name
Test status
Simulation time 79152402 ps
CPU time 0.76 seconds
Started Aug 10 05:24:31 PM PDT 24
Finished Aug 10 05:24:32 PM PDT 24
Peak memory 200156 kb
Host smart-3b6611fb-07e2-4c8e-91e3-8573d0ce4ff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1268135052 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_alert_test.1268135052
Directory /workspace/24.rstmgr_alert_test/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_cnsty.6092778
Short name T23
Test name
Test status
Simulation time 1218036280 ps
CPU time 5.56 seconds
Started Aug 10 05:24:48 PM PDT 24
Finished Aug 10 05:24:53 PM PDT 24
Peak memory 217748 kb
Host smart-a7bcce0f-bb71-4bae-b894-e1c9ec7654c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6092778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_cnsty.6092778
Directory /workspace/24.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/24.rstmgr_leaf_rst_shadow_attack.1230762592
Short name T359
Test name
Test status
Simulation time 243914336 ps
CPU time 1.12 seconds
Started Aug 10 05:24:35 PM PDT 24
Finished Aug 10 05:24:36 PM PDT 24
Peak memory 217524 kb
Host smart-88c2888b-0403-4276-b4ba-44d33b8116de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230762592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_leaf_rst_shadow_attack.1230762592
Directory /workspace/24.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/24.rstmgr_por_stretcher.2494837916
Short name T421
Test name
Test status
Simulation time 86826911 ps
CPU time 0.78 seconds
Started Aug 10 05:24:59 PM PDT 24
Finished Aug 10 05:24:59 PM PDT 24
Peak memory 200164 kb
Host smart-42a67b1f-6e30-4a1b-9bd7-c6c45fba75f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2494837916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_por_stretcher.2494837916
Directory /workspace/24.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/24.rstmgr_reset.4009715618
Short name T191
Test name
Test status
Simulation time 864044988 ps
CPU time 4.11 seconds
Started Aug 10 05:24:40 PM PDT 24
Finished Aug 10 05:24:44 PM PDT 24
Peak memory 200560 kb
Host smart-286c3887-86b1-43f9-a23e-4a5ddc343174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009715618 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_reset.4009715618
Directory /workspace/24.rstmgr_reset/latest

Test location /workspace/coverage/default/24.rstmgr_sec_cm_scan_intersig_mubi.583562985
Short name T377
Test name
Test status
Simulation time 104695718 ps
CPU time 1.09 seconds
Started Aug 10 05:24:56 PM PDT 24
Finished Aug 10 05:24:57 PM PDT 24
Peak memory 200304 kb
Host smart-5491aefc-1753-4d69-87e1-d1db4cbf39b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583562985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sec_cm_scan_intersig_mubi.583562985
Directory /workspace/24.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/24.rstmgr_smoke.1932906728
Short name T395
Test name
Test status
Simulation time 130080366 ps
CPU time 1.19 seconds
Started Aug 10 05:24:49 PM PDT 24
Finished Aug 10 05:24:50 PM PDT 24
Peak memory 200388 kb
Host smart-6ac75f27-c2c0-4081-b5a5-c2fc88dee3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932906728 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_smoke.1932906728
Directory /workspace/24.rstmgr_smoke/latest

Test location /workspace/coverage/default/24.rstmgr_stress_all.2287768734
Short name T449
Test name
Test status
Simulation time 814045395 ps
CPU time 3.32 seconds
Started Aug 10 05:24:35 PM PDT 24
Finished Aug 10 05:24:38 PM PDT 24
Peak memory 200548 kb
Host smart-5f45e1a4-3995-4858-bf25-e190fa2cba4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287768734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_stress_all.2287768734
Directory /workspace/24.rstmgr_stress_all/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst.3269102631
Short name T137
Test name
Test status
Simulation time 366160277 ps
CPU time 2.39 seconds
Started Aug 10 05:24:47 PM PDT 24
Finished Aug 10 05:24:50 PM PDT 24
Peak memory 200268 kb
Host smart-1c89a26a-eb81-42c9-8c20-72f1f280626a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3269102631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst.3269102631
Directory /workspace/24.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/24.rstmgr_sw_rst_reset_race.3363496534
Short name T199
Test name
Test status
Simulation time 164948984 ps
CPU time 1.17 seconds
Started Aug 10 05:24:36 PM PDT 24
Finished Aug 10 05:24:37 PM PDT 24
Peak memory 200320 kb
Host smart-bc55e599-c65d-4989-911f-6325824d2a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3363496534 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.rstmgr_sw_rst_reset_race.3363496534
Directory /workspace/24.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/25.rstmgr_alert_test.4223310921
Short name T142
Test name
Test status
Simulation time 75245989 ps
CPU time 0.78 seconds
Started Aug 10 05:24:50 PM PDT 24
Finished Aug 10 05:24:51 PM PDT 24
Peak memory 200164 kb
Host smart-3b3741c2-7f0b-42c3-8ef8-06a1ac8e651f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223310921 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_alert_test.4223310921
Directory /workspace/25.rstmgr_alert_test/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_cnsty.3390013508
Short name T29
Test name
Test status
Simulation time 1217748682 ps
CPU time 6.14 seconds
Started Aug 10 05:24:39 PM PDT 24
Finished Aug 10 05:24:45 PM PDT 24
Peak memory 217324 kb
Host smart-a75a60ac-0e45-4375-b410-158b74fd9852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390013508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_cnsty.3390013508
Directory /workspace/25.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/25.rstmgr_leaf_rst_shadow_attack.2867808011
Short name T140
Test name
Test status
Simulation time 243993581 ps
CPU time 1.06 seconds
Started Aug 10 05:24:39 PM PDT 24
Finished Aug 10 05:24:40 PM PDT 24
Peak memory 217584 kb
Host smart-dbe7d0a5-2f36-45c0-9519-dab56895123a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2867808011 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_leaf_rst_shadow_attack.2867808011
Directory /workspace/25.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/25.rstmgr_por_stretcher.918497404
Short name T16
Test name
Test status
Simulation time 199527773 ps
CPU time 0.9 seconds
Started Aug 10 05:24:37 PM PDT 24
Finished Aug 10 05:24:38 PM PDT 24
Peak memory 200172 kb
Host smart-da917cde-b45e-4b08-948c-75256f103f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=918497404 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_por_stretcher.918497404
Directory /workspace/25.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/25.rstmgr_reset.3488331442
Short name T534
Test name
Test status
Simulation time 1496087516 ps
CPU time 6.12 seconds
Started Aug 10 05:24:30 PM PDT 24
Finished Aug 10 05:24:36 PM PDT 24
Peak memory 200480 kb
Host smart-717d14d2-b99e-4d4c-b317-f929e488d99b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488331442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_reset.3488331442
Directory /workspace/25.rstmgr_reset/latest

Test location /workspace/coverage/default/25.rstmgr_sec_cm_scan_intersig_mubi.1714392457
Short name T57
Test name
Test status
Simulation time 174238545 ps
CPU time 1.31 seconds
Started Aug 10 05:25:07 PM PDT 24
Finished Aug 10 05:25:09 PM PDT 24
Peak memory 200352 kb
Host smart-70c8e398-5722-4cfa-ad3b-8b9a2bc5a132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714392457 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sec_cm_scan_intersig_mubi.1714392457
Directory /workspace/25.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/25.rstmgr_smoke.299009160
Short name T324
Test name
Test status
Simulation time 112242925 ps
CPU time 1.19 seconds
Started Aug 10 05:24:46 PM PDT 24
Finished Aug 10 05:24:48 PM PDT 24
Peak memory 200468 kb
Host smart-b2ef4211-f1ce-4e8d-a239-e9e491ad1d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299009160 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_smoke.299009160
Directory /workspace/25.rstmgr_smoke/latest

Test location /workspace/coverage/default/25.rstmgr_stress_all.2442118371
Short name T157
Test name
Test status
Simulation time 4097513718 ps
CPU time 15.61 seconds
Started Aug 10 05:24:52 PM PDT 24
Finished Aug 10 05:25:07 PM PDT 24
Peak memory 200632 kb
Host smart-13d358cf-d244-42a7-8641-917db6a7b1a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442118371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_stress_all.2442118371
Directory /workspace/25.rstmgr_stress_all/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst.2171161101
Short name T308
Test name
Test status
Simulation time 429572257 ps
CPU time 2.5 seconds
Started Aug 10 05:25:01 PM PDT 24
Finished Aug 10 05:25:04 PM PDT 24
Peak memory 208488 kb
Host smart-37b0c0bf-7747-4b3b-9efa-2857d4ae0363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171161101 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst.2171161101
Directory /workspace/25.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/25.rstmgr_sw_rst_reset_race.484824121
Short name T132
Test name
Test status
Simulation time 171120822 ps
CPU time 1.12 seconds
Started Aug 10 05:24:44 PM PDT 24
Finished Aug 10 05:24:45 PM PDT 24
Peak memory 200360 kb
Host smart-a0a695e4-756a-4c6a-8b52-41db638bd928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=484824121 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.rstmgr_sw_rst_reset_race.484824121
Directory /workspace/25.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/26.rstmgr_alert_test.2871490872
Short name T424
Test name
Test status
Simulation time 79540376 ps
CPU time 0.82 seconds
Started Aug 10 05:24:57 PM PDT 24
Finished Aug 10 05:24:58 PM PDT 24
Peak memory 200096 kb
Host smart-f3b927c8-bb64-45bd-a9ec-5e3e84cf225d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871490872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_alert_test.2871490872
Directory /workspace/26.rstmgr_alert_test/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_cnsty.1116470514
Short name T336
Test name
Test status
Simulation time 1886495591 ps
CPU time 7.46 seconds
Started Aug 10 05:24:57 PM PDT 24
Finished Aug 10 05:25:04 PM PDT 24
Peak memory 217704 kb
Host smart-84457d17-93cf-424e-a93c-f2b2c112d4e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116470514 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_cnsty.1116470514
Directory /workspace/26.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/26.rstmgr_leaf_rst_shadow_attack.3502150640
Short name T219
Test name
Test status
Simulation time 243745793 ps
CPU time 1.14 seconds
Started Aug 10 05:25:03 PM PDT 24
Finished Aug 10 05:25:04 PM PDT 24
Peak memory 217464 kb
Host smart-69cf1dd3-8b36-40cf-a935-d645ff8d17ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502150640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_leaf_rst_shadow_attack.3502150640
Directory /workspace/26.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/26.rstmgr_por_stretcher.3774916296
Short name T291
Test name
Test status
Simulation time 136197946 ps
CPU time 0.8 seconds
Started Aug 10 05:24:41 PM PDT 24
Finished Aug 10 05:24:42 PM PDT 24
Peak memory 200156 kb
Host smart-1a405ba2-cbfb-473e-9572-9b9421abb8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3774916296 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_por_stretcher.3774916296
Directory /workspace/26.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/26.rstmgr_reset.812615403
Short name T490
Test name
Test status
Simulation time 1439006241 ps
CPU time 5.08 seconds
Started Aug 10 05:24:58 PM PDT 24
Finished Aug 10 05:25:03 PM PDT 24
Peak memory 200488 kb
Host smart-0cb1e02d-01a7-4a1f-a26c-fb96180c7b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812615403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_reset.812615403
Directory /workspace/26.rstmgr_reset/latest

Test location /workspace/coverage/default/26.rstmgr_sec_cm_scan_intersig_mubi.1815261508
Short name T520
Test name
Test status
Simulation time 98947189 ps
CPU time 0.98 seconds
Started Aug 10 05:24:50 PM PDT 24
Finished Aug 10 05:24:51 PM PDT 24
Peak memory 200356 kb
Host smart-238c9b16-6e4a-4fab-80d4-62f8ad40402c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815261508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sec_cm_scan_intersig_mubi.1815261508
Directory /workspace/26.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/26.rstmgr_smoke.4000817985
Short name T362
Test name
Test status
Simulation time 117242016 ps
CPU time 1.19 seconds
Started Aug 10 05:24:37 PM PDT 24
Finished Aug 10 05:24:38 PM PDT 24
Peak memory 200364 kb
Host smart-b2d3010b-c547-433e-867f-05e02f9d9949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000817985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_smoke.4000817985
Directory /workspace/26.rstmgr_smoke/latest

Test location /workspace/coverage/default/26.rstmgr_stress_all.1831393895
Short name T541
Test name
Test status
Simulation time 3776677707 ps
CPU time 14.76 seconds
Started Aug 10 05:24:43 PM PDT 24
Finished Aug 10 05:25:03 PM PDT 24
Peak memory 208804 kb
Host smart-a1315372-e384-49ca-a8f9-87bff2c8027c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831393895 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_stress_all.1831393895
Directory /workspace/26.rstmgr_stress_all/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst.3640112019
Short name T275
Test name
Test status
Simulation time 128739936 ps
CPU time 1.6 seconds
Started Aug 10 05:24:45 PM PDT 24
Finished Aug 10 05:24:46 PM PDT 24
Peak memory 200224 kb
Host smart-643ab085-72c4-4afd-84aa-919ecba69c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640112019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst.3640112019
Directory /workspace/26.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/26.rstmgr_sw_rst_reset_race.2736707525
Short name T332
Test name
Test status
Simulation time 177615940 ps
CPU time 1.19 seconds
Started Aug 10 05:24:37 PM PDT 24
Finished Aug 10 05:24:38 PM PDT 24
Peak memory 200260 kb
Host smart-ca067de8-4fa6-46d7-ad9a-3527b95c20cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736707525 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.rstmgr_sw_rst_reset_race.2736707525
Directory /workspace/26.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/27.rstmgr_alert_test.2585785702
Short name T364
Test name
Test status
Simulation time 59314520 ps
CPU time 0.74 seconds
Started Aug 10 05:24:49 PM PDT 24
Finished Aug 10 05:24:50 PM PDT 24
Peak memory 200148 kb
Host smart-d7ae0ace-47f6-4252-a31b-e1d111daa30e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2585785702 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_alert_test.2585785702
Directory /workspace/27.rstmgr_alert_test/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_cnsty.961089193
Short name T281
Test name
Test status
Simulation time 1875751349 ps
CPU time 6.82 seconds
Started Aug 10 05:24:40 PM PDT 24
Finished Aug 10 05:24:47 PM PDT 24
Peak memory 217384 kb
Host smart-a575c58d-b09c-49ad-8bf8-94ec20ef32fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961089193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_cnsty.961089193
Directory /workspace/27.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/27.rstmgr_leaf_rst_shadow_attack.2788520211
Short name T154
Test name
Test status
Simulation time 244648201 ps
CPU time 1.04 seconds
Started Aug 10 05:24:47 PM PDT 24
Finished Aug 10 05:24:48 PM PDT 24
Peak memory 217544 kb
Host smart-780a7eba-c1d1-452d-9fe7-9b39620fc465
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788520211 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_leaf_rst_shadow_attack.2788520211
Directory /workspace/27.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/27.rstmgr_por_stretcher.899777286
Short name T19
Test name
Test status
Simulation time 153980503 ps
CPU time 0.83 seconds
Started Aug 10 05:24:54 PM PDT 24
Finished Aug 10 05:24:55 PM PDT 24
Peak memory 200024 kb
Host smart-7ba1601d-29e7-4be1-a079-a99faae4c047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899777286 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_por_stretcher.899777286
Directory /workspace/27.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/27.rstmgr_reset.734404066
Short name T339
Test name
Test status
Simulation time 1639051292 ps
CPU time 6.31 seconds
Started Aug 10 05:24:34 PM PDT 24
Finished Aug 10 05:24:40 PM PDT 24
Peak memory 200552 kb
Host smart-3f845ed8-3e20-4ad4-bb25-a5ba08da809e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=734404066 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_reset.734404066
Directory /workspace/27.rstmgr_reset/latest

Test location /workspace/coverage/default/27.rstmgr_sec_cm_scan_intersig_mubi.4023729546
Short name T194
Test name
Test status
Simulation time 100374280 ps
CPU time 0.96 seconds
Started Aug 10 05:24:34 PM PDT 24
Finished Aug 10 05:24:35 PM PDT 24
Peak memory 200364 kb
Host smart-696cc94b-1904-45d2-8854-77ddd741c039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023729546 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sec_cm_scan_intersig_mubi.4023729546
Directory /workspace/27.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/27.rstmgr_smoke.362985054
Short name T298
Test name
Test status
Simulation time 193497198 ps
CPU time 1.44 seconds
Started Aug 10 05:24:30 PM PDT 24
Finished Aug 10 05:24:31 PM PDT 24
Peak memory 200500 kb
Host smart-a1ee42b8-8bed-42d1-b660-486adc37d5de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362985054 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_smoke.362985054
Directory /workspace/27.rstmgr_smoke/latest

Test location /workspace/coverage/default/27.rstmgr_stress_all.3742827492
Short name T114
Test name
Test status
Simulation time 5542690167 ps
CPU time 18.78 seconds
Started Aug 10 05:24:32 PM PDT 24
Finished Aug 10 05:24:51 PM PDT 24
Peak memory 200640 kb
Host smart-9c24071a-1d8e-437e-aadb-30ffdf4ba6ec
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742827492 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_stress_all.3742827492
Directory /workspace/27.rstmgr_stress_all/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst.2066006670
Short name T223
Test name
Test status
Simulation time 541069415 ps
CPU time 3.14 seconds
Started Aug 10 05:24:28 PM PDT 24
Finished Aug 10 05:24:31 PM PDT 24
Peak memory 200308 kb
Host smart-4f15868e-d091-4b9f-8667-28b1510daa32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066006670 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst.2066006670
Directory /workspace/27.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/27.rstmgr_sw_rst_reset_race.4241223889
Short name T322
Test name
Test status
Simulation time 103538409 ps
CPU time 1.02 seconds
Started Aug 10 05:24:34 PM PDT 24
Finished Aug 10 05:24:35 PM PDT 24
Peak memory 200156 kb
Host smart-24a0bc04-a047-42e2-8523-bdf91013a7ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4241223889 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.rstmgr_sw_rst_reset_race.4241223889
Directory /workspace/27.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/28.rstmgr_alert_test.463203545
Short name T419
Test name
Test status
Simulation time 68731034 ps
CPU time 0.74 seconds
Started Aug 10 05:24:40 PM PDT 24
Finished Aug 10 05:24:41 PM PDT 24
Peak memory 200152 kb
Host smart-cc04b385-930f-4b5f-92d1-cf903a1e7b66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463203545 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_alert_test.463203545
Directory /workspace/28.rstmgr_alert_test/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_cnsty.3785694169
Short name T39
Test name
Test status
Simulation time 1890261404 ps
CPU time 7.65 seconds
Started Aug 10 05:24:49 PM PDT 24
Finished Aug 10 05:24:57 PM PDT 24
Peak memory 221656 kb
Host smart-96bbee2d-5e3d-47c3-aa2b-6dc053ef380a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785694169 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_cnsty.3785694169
Directory /workspace/28.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/28.rstmgr_leaf_rst_shadow_attack.3073354709
Short name T478
Test name
Test status
Simulation time 244615738 ps
CPU time 1.06 seconds
Started Aug 10 05:24:35 PM PDT 24
Finished Aug 10 05:24:36 PM PDT 24
Peak memory 217432 kb
Host smart-6db843d9-0668-48df-92c0-901945c6da03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3073354709 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_leaf_rst_shadow_attack.3073354709
Directory /workspace/28.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/28.rstmgr_por_stretcher.1032640756
Short name T451
Test name
Test status
Simulation time 90746383 ps
CPU time 0.75 seconds
Started Aug 10 05:24:35 PM PDT 24
Finished Aug 10 05:24:40 PM PDT 24
Peak memory 200100 kb
Host smart-42c43f8b-d4c5-4c4d-a1a5-647bada85f29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032640756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_por_stretcher.1032640756
Directory /workspace/28.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/28.rstmgr_reset.3343437856
Short name T125
Test name
Test status
Simulation time 1520417104 ps
CPU time 6.8 seconds
Started Aug 10 05:24:30 PM PDT 24
Finished Aug 10 05:24:37 PM PDT 24
Peak memory 200456 kb
Host smart-c92f4705-89da-4765-a919-ae64e6c9c5d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343437856 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_reset.3343437856
Directory /workspace/28.rstmgr_reset/latest

Test location /workspace/coverage/default/28.rstmgr_sec_cm_scan_intersig_mubi.1468550949
Short name T440
Test name
Test status
Simulation time 157746043 ps
CPU time 1.2 seconds
Started Aug 10 05:24:40 PM PDT 24
Finished Aug 10 05:24:41 PM PDT 24
Peak memory 200436 kb
Host smart-d8f4fef6-62b5-43d3-bfa5-a067f2e1e7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1468550949 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sec_cm_scan_intersig_mubi.1468550949
Directory /workspace/28.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/28.rstmgr_smoke.1797151205
Short name T234
Test name
Test status
Simulation time 256234243 ps
CPU time 1.44 seconds
Started Aug 10 05:24:35 PM PDT 24
Finished Aug 10 05:24:36 PM PDT 24
Peak memory 200500 kb
Host smart-221d7c7c-47a2-4c86-9216-da572459e70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1797151205 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_smoke.1797151205
Directory /workspace/28.rstmgr_smoke/latest

Test location /workspace/coverage/default/28.rstmgr_stress_all.226255299
Short name T159
Test name
Test status
Simulation time 7888682393 ps
CPU time 26.77 seconds
Started Aug 10 05:24:54 PM PDT 24
Finished Aug 10 05:25:21 PM PDT 24
Peak memory 200620 kb
Host smart-99ba61fe-1aa4-4787-a6d8-b0f20f276903
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=226255299 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_stress_all.226255299
Directory /workspace/28.rstmgr_stress_all/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst.62942019
Short name T462
Test name
Test status
Simulation time 133022358 ps
CPU time 1.69 seconds
Started Aug 10 05:24:34 PM PDT 24
Finished Aug 10 05:24:36 PM PDT 24
Peak memory 208428 kb
Host smart-97eed179-2ab5-4b58-a013-e4c56eebe905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=62942019 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst.62942019
Directory /workspace/28.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/28.rstmgr_sw_rst_reset_race.5664729
Short name T344
Test name
Test status
Simulation time 221024064 ps
CPU time 1.24 seconds
Started Aug 10 05:24:34 PM PDT 24
Finished Aug 10 05:24:36 PM PDT 24
Peak memory 200196 kb
Host smart-25426fb5-a2a3-40bc-b442-24bb9eaee808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5664729 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.rstmgr_sw_rst_reset_race.5664729
Directory /workspace/28.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/29.rstmgr_alert_test.4034105451
Short name T224
Test name
Test status
Simulation time 54163695 ps
CPU time 0.76 seconds
Started Aug 10 05:24:40 PM PDT 24
Finished Aug 10 05:24:41 PM PDT 24
Peak memory 200152 kb
Host smart-67890f30-d3fd-40a5-b05e-dcffd1718ea6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034105451 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_alert_test.4034105451
Directory /workspace/29.rstmgr_alert_test/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_cnsty.2522193639
Short name T465
Test name
Test status
Simulation time 2175007931 ps
CPU time 8.47 seconds
Started Aug 10 05:24:54 PM PDT 24
Finished Aug 10 05:25:02 PM PDT 24
Peak memory 217812 kb
Host smart-b562b324-8ea8-4150-980e-4454a54d8d56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522193639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_cnsty.2522193639
Directory /workspace/29.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/29.rstmgr_leaf_rst_shadow_attack.2561966493
Short name T444
Test name
Test status
Simulation time 244125264 ps
CPU time 1.11 seconds
Started Aug 10 05:24:47 PM PDT 24
Finished Aug 10 05:24:48 PM PDT 24
Peak memory 217492 kb
Host smart-3b7b14a1-10bc-47e6-978d-205e9837d535
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561966493 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_leaf_rst_shadow_attack.2561966493
Directory /workspace/29.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/29.rstmgr_por_stretcher.3971690201
Short name T136
Test name
Test status
Simulation time 151497690 ps
CPU time 0.79 seconds
Started Aug 10 05:24:57 PM PDT 24
Finished Aug 10 05:24:58 PM PDT 24
Peak memory 200168 kb
Host smart-4e5d8ad0-563b-4916-8b9c-08cdb5c204ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971690201 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_por_stretcher.3971690201
Directory /workspace/29.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/29.rstmgr_reset.3064239473
Short name T268
Test name
Test status
Simulation time 1107406141 ps
CPU time 4.64 seconds
Started Aug 10 05:25:06 PM PDT 24
Finished Aug 10 05:25:11 PM PDT 24
Peak memory 200548 kb
Host smart-6e815eb7-dba1-475e-a881-dc80ea5d6500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3064239473 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_reset.3064239473
Directory /workspace/29.rstmgr_reset/latest

Test location /workspace/coverage/default/29.rstmgr_sec_cm_scan_intersig_mubi.2847485606
Short name T519
Test name
Test status
Simulation time 151865560 ps
CPU time 1.22 seconds
Started Aug 10 05:24:35 PM PDT 24
Finished Aug 10 05:24:36 PM PDT 24
Peak memory 200368 kb
Host smart-648d4f8e-ecb9-487a-8926-b47877a5d9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2847485606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sec_cm_scan_intersig_mubi.2847485606
Directory /workspace/29.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/29.rstmgr_smoke.2985097764
Short name T180
Test name
Test status
Simulation time 116701073 ps
CPU time 1.15 seconds
Started Aug 10 05:24:42 PM PDT 24
Finished Aug 10 05:24:43 PM PDT 24
Peak memory 200448 kb
Host smart-b3ec4db7-6c0f-4c61-a17f-b1fbf8652571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985097764 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_smoke.2985097764
Directory /workspace/29.rstmgr_smoke/latest

Test location /workspace/coverage/default/29.rstmgr_stress_all.3912836990
Short name T282
Test name
Test status
Simulation time 6622383405 ps
CPU time 25.59 seconds
Started Aug 10 05:24:37 PM PDT 24
Finished Aug 10 05:25:03 PM PDT 24
Peak memory 208724 kb
Host smart-63a8d3c4-a880-456c-b2d3-5c700225625b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912836990 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_stress_all.3912836990
Directory /workspace/29.rstmgr_stress_all/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst.3605405240
Short name T347
Test name
Test status
Simulation time 368276077 ps
CPU time 2.35 seconds
Started Aug 10 05:24:56 PM PDT 24
Finished Aug 10 05:24:59 PM PDT 24
Peak memory 200248 kb
Host smart-8377bcd1-b8ac-4d4e-9f1f-aa0d0ee7b215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605405240 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst.3605405240
Directory /workspace/29.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/29.rstmgr_sw_rst_reset_race.2580382143
Short name T416
Test name
Test status
Simulation time 135165257 ps
CPU time 1.05 seconds
Started Aug 10 05:24:59 PM PDT 24
Finished Aug 10 05:25:00 PM PDT 24
Peak memory 200340 kb
Host smart-c7bcc154-f996-4d61-bf9d-ceab97bd98b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580382143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.rstmgr_sw_rst_reset_race.2580382143
Directory /workspace/29.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/3.rstmgr_alert_test.1527392994
Short name T163
Test name
Test status
Simulation time 70981202 ps
CPU time 0.81 seconds
Started Aug 10 05:24:27 PM PDT 24
Finished Aug 10 05:24:28 PM PDT 24
Peak memory 200152 kb
Host smart-c35a7249-fec5-43bf-84ec-e47a0b0392d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527392994 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_alert_test.1527392994
Directory /workspace/3.rstmgr_alert_test/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_cnsty.1383061578
Short name T372
Test name
Test status
Simulation time 1884786610 ps
CPU time 7.27 seconds
Started Aug 10 05:24:19 PM PDT 24
Finished Aug 10 05:24:26 PM PDT 24
Peak memory 221652 kb
Host smart-d86effe8-9ad0-4f30-b17e-3475669fdfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1383061578 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_cnsty.1383061578
Directory /workspace/3.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/3.rstmgr_leaf_rst_shadow_attack.4159150612
Short name T469
Test name
Test status
Simulation time 243993824 ps
CPU time 1.14 seconds
Started Aug 10 05:24:19 PM PDT 24
Finished Aug 10 05:24:20 PM PDT 24
Peak memory 217488 kb
Host smart-bb02bf0f-203b-4589-9842-8daf757bee41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4159150612 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_leaf_rst_shadow_attack.4159150612
Directory /workspace/3.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/3.rstmgr_por_stretcher.2583797916
Short name T389
Test name
Test status
Simulation time 176574380 ps
CPU time 0.87 seconds
Started Aug 10 05:24:13 PM PDT 24
Finished Aug 10 05:24:14 PM PDT 24
Peak memory 200036 kb
Host smart-1f10cd8d-7b23-4582-842b-3b8d1d99ed5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583797916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_por_stretcher.2583797916
Directory /workspace/3.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/3.rstmgr_reset.2541183878
Short name T66
Test name
Test status
Simulation time 2150297688 ps
CPU time 8.78 seconds
Started Aug 10 05:24:13 PM PDT 24
Finished Aug 10 05:24:22 PM PDT 24
Peak memory 200632 kb
Host smart-5ebe23ba-4df1-441f-8a68-e0bac49ae155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541183878 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_reset.2541183878
Directory /workspace/3.rstmgr_reset/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm.3414640885
Short name T50
Test name
Test status
Simulation time 16630071992 ps
CPU time 24.88 seconds
Started Aug 10 05:24:27 PM PDT 24
Finished Aug 10 05:24:52 PM PDT 24
Peak memory 217312 kb
Host smart-7c685131-2b87-4657-9d87-6705bd171e10
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3414640885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm.3414640885
Directory /workspace/3.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/3.rstmgr_sec_cm_scan_intersig_mubi.2560692188
Short name T481
Test name
Test status
Simulation time 156829649 ps
CPU time 1.19 seconds
Started Aug 10 05:24:22 PM PDT 24
Finished Aug 10 05:24:23 PM PDT 24
Peak memory 200304 kb
Host smart-9d576e38-73d9-417b-9be1-66aadcb4c452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560692188 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sec_cm_scan_intersig_mubi.2560692188
Directory /workspace/3.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/3.rstmgr_smoke.2176741866
Short name T197
Test name
Test status
Simulation time 124990490 ps
CPU time 1.15 seconds
Started Aug 10 05:24:10 PM PDT 24
Finished Aug 10 05:24:12 PM PDT 24
Peak memory 200340 kb
Host smart-787a0e8f-c378-4ae8-ad2b-bfe79645a364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176741866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_smoke.2176741866
Directory /workspace/3.rstmgr_smoke/latest

Test location /workspace/coverage/default/3.rstmgr_stress_all.830347452
Short name T73
Test name
Test status
Simulation time 8650595470 ps
CPU time 28.41 seconds
Started Aug 10 05:24:25 PM PDT 24
Finished Aug 10 05:24:54 PM PDT 24
Peak memory 200572 kb
Host smart-3000e2da-5e25-4197-b9ee-964e2d458e67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830347452 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_stress_all.830347452
Directory /workspace/3.rstmgr_stress_all/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst.2888215231
Short name T74
Test name
Test status
Simulation time 305033595 ps
CPU time 2.03 seconds
Started Aug 10 05:24:18 PM PDT 24
Finished Aug 10 05:24:20 PM PDT 24
Peak memory 208528 kb
Host smart-5aa56056-dc5d-4fb3-bcec-69ab1d485abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888215231 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst.2888215231
Directory /workspace/3.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/3.rstmgr_sw_rst_reset_race.828639463
Short name T70
Test name
Test status
Simulation time 132357355 ps
CPU time 1.14 seconds
Started Aug 10 05:24:20 PM PDT 24
Finished Aug 10 05:24:21 PM PDT 24
Peak memory 200264 kb
Host smart-5de53709-c53e-4001-8097-cc62d477f504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828639463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.rstmgr_sw_rst_reset_race.828639463
Directory /workspace/3.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/30.rstmgr_alert_test.1431801781
Short name T277
Test name
Test status
Simulation time 80024095 ps
CPU time 0.75 seconds
Started Aug 10 05:24:41 PM PDT 24
Finished Aug 10 05:24:42 PM PDT 24
Peak memory 200000 kb
Host smart-d24b5ca4-33d5-41bd-b663-701ee309618c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431801781 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_alert_test.1431801781
Directory /workspace/30.rstmgr_alert_test/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_cnsty.2649431371
Short name T312
Test name
Test status
Simulation time 1899042540 ps
CPU time 7.09 seconds
Started Aug 10 05:24:54 PM PDT 24
Finished Aug 10 05:25:01 PM PDT 24
Peak memory 217800 kb
Host smart-a1afc47a-eb16-414a-bcc4-dd70830f16c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649431371 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_cnsty.2649431371
Directory /workspace/30.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/30.rstmgr_leaf_rst_shadow_attack.1989691145
Short name T13
Test name
Test status
Simulation time 243981953 ps
CPU time 1.06 seconds
Started Aug 10 05:24:37 PM PDT 24
Finished Aug 10 05:24:38 PM PDT 24
Peak memory 217508 kb
Host smart-8d1ff602-7835-4c24-be37-982a15a0f7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989691145 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_leaf_rst_shadow_attack.1989691145
Directory /workspace/30.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/30.rstmgr_por_stretcher.665161434
Short name T4
Test name
Test status
Simulation time 201567270 ps
CPU time 1.06 seconds
Started Aug 10 05:25:10 PM PDT 24
Finished Aug 10 05:25:11 PM PDT 24
Peak memory 200172 kb
Host smart-5e4ea0be-32e4-4309-8901-f0a16dacd8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=665161434 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_por_stretcher.665161434
Directory /workspace/30.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/30.rstmgr_reset.1553927849
Short name T200
Test name
Test status
Simulation time 1372624566 ps
CPU time 5.47 seconds
Started Aug 10 05:25:01 PM PDT 24
Finished Aug 10 05:25:07 PM PDT 24
Peak memory 200568 kb
Host smart-7aaae8e7-5ee2-4a17-8155-c270bc5deffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1553927849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_reset.1553927849
Directory /workspace/30.rstmgr_reset/latest

Test location /workspace/coverage/default/30.rstmgr_sec_cm_scan_intersig_mubi.446078187
Short name T201
Test name
Test status
Simulation time 143899887 ps
CPU time 1.05 seconds
Started Aug 10 05:24:36 PM PDT 24
Finished Aug 10 05:24:43 PM PDT 24
Peak memory 200376 kb
Host smart-55afee51-c457-4cc9-aa26-958da553e230
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446078187 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sec_cm_scan_intersig_mubi.446078187
Directory /workspace/30.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/30.rstmgr_smoke.525732294
Short name T422
Test name
Test status
Simulation time 255366628 ps
CPU time 1.56 seconds
Started Aug 10 05:24:57 PM PDT 24
Finished Aug 10 05:24:59 PM PDT 24
Peak memory 200424 kb
Host smart-7be15387-4639-4118-9d9e-e324bb1f0f51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525732294 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_smoke.525732294
Directory /workspace/30.rstmgr_smoke/latest

Test location /workspace/coverage/default/30.rstmgr_stress_all.4258168870
Short name T407
Test name
Test status
Simulation time 9824740430 ps
CPU time 43.19 seconds
Started Aug 10 05:24:52 PM PDT 24
Finished Aug 10 05:25:35 PM PDT 24
Peak memory 200620 kb
Host smart-f76b9f64-3e0c-44dd-994c-db0e02a20e6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258168870 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_stress_all.4258168870
Directory /workspace/30.rstmgr_stress_all/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst.2868130131
Short name T77
Test name
Test status
Simulation time 135897611 ps
CPU time 1.65 seconds
Started Aug 10 05:25:02 PM PDT 24
Finished Aug 10 05:25:03 PM PDT 24
Peak memory 200336 kb
Host smart-5fe339b2-f240-4ef9-abb0-2bd7d50cb78d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868130131 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst.2868130131
Directory /workspace/30.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/30.rstmgr_sw_rst_reset_race.2246788731
Short name T158
Test name
Test status
Simulation time 129397050 ps
CPU time 0.97 seconds
Started Aug 10 05:24:37 PM PDT 24
Finished Aug 10 05:24:38 PM PDT 24
Peak memory 200188 kb
Host smart-bde20cc9-ab2e-435e-bf76-ea0827cbf637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246788731 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.rstmgr_sw_rst_reset_race.2246788731
Directory /workspace/30.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/31.rstmgr_alert_test.4087115606
Short name T425
Test name
Test status
Simulation time 77871101 ps
CPU time 0.83 seconds
Started Aug 10 05:25:07 PM PDT 24
Finished Aug 10 05:25:08 PM PDT 24
Peak memory 200120 kb
Host smart-1164d168-ee2e-46f9-830e-bf5394352394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087115606 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_alert_test.4087115606
Directory /workspace/31.rstmgr_alert_test/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_cnsty.682326068
Short name T34
Test name
Test status
Simulation time 1221041076 ps
CPU time 5.66 seconds
Started Aug 10 05:24:56 PM PDT 24
Finished Aug 10 05:25:02 PM PDT 24
Peak memory 217356 kb
Host smart-53fc59a7-5a1e-4bad-ae8c-14ddf3891101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=682326068 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_cnsty.682326068
Directory /workspace/31.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/31.rstmgr_leaf_rst_shadow_attack.1127139354
Short name T349
Test name
Test status
Simulation time 244152799 ps
CPU time 1.15 seconds
Started Aug 10 05:24:42 PM PDT 24
Finished Aug 10 05:24:43 PM PDT 24
Peak memory 217416 kb
Host smart-271d8ecb-d80e-405a-b8c8-7d4f3c62f49f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127139354 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_leaf_rst_shadow_attack.1127139354
Directory /workspace/31.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/31.rstmgr_por_stretcher.743035789
Short name T244
Test name
Test status
Simulation time 124370497 ps
CPU time 0.82 seconds
Started Aug 10 05:24:54 PM PDT 24
Finished Aug 10 05:24:55 PM PDT 24
Peak memory 200148 kb
Host smart-5e712b1f-3a8e-4532-b245-af8f7a36b636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743035789 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_por_stretcher.743035789
Directory /workspace/31.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/31.rstmgr_reset.360946965
Short name T498
Test name
Test status
Simulation time 1007162915 ps
CPU time 5.11 seconds
Started Aug 10 05:24:56 PM PDT 24
Finished Aug 10 05:25:01 PM PDT 24
Peak memory 200452 kb
Host smart-5d0b970d-876d-4033-af7a-ed59d4899fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=360946965 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_reset.360946965
Directory /workspace/31.rstmgr_reset/latest

Test location /workspace/coverage/default/31.rstmgr_sec_cm_scan_intersig_mubi.3904020933
Short name T335
Test name
Test status
Simulation time 140164250 ps
CPU time 1.13 seconds
Started Aug 10 05:24:38 PM PDT 24
Finished Aug 10 05:24:39 PM PDT 24
Peak memory 200392 kb
Host smart-9c38ff9c-2026-4dbb-a5a7-50303bad7a6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904020933 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sec_cm_scan_intersig_mubi.3904020933
Directory /workspace/31.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/31.rstmgr_smoke.2072226100
Short name T327
Test name
Test status
Simulation time 182952651 ps
CPU time 1.42 seconds
Started Aug 10 05:24:52 PM PDT 24
Finished Aug 10 05:24:54 PM PDT 24
Peak memory 200468 kb
Host smart-427588f4-0bd7-4080-906e-2b8af516477a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072226100 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_smoke.2072226100
Directory /workspace/31.rstmgr_smoke/latest

Test location /workspace/coverage/default/31.rstmgr_stress_all.3097967928
Short name T530
Test name
Test status
Simulation time 2821228149 ps
CPU time 13.02 seconds
Started Aug 10 05:24:36 PM PDT 24
Finished Aug 10 05:24:49 PM PDT 24
Peak memory 200676 kb
Host smart-6e0819c0-6d8b-4b1a-8067-1d12d20bc445
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097967928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_stress_all.3097967928
Directory /workspace/31.rstmgr_stress_all/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst.3076140441
Short name T261
Test name
Test status
Simulation time 297412877 ps
CPU time 2 seconds
Started Aug 10 05:24:49 PM PDT 24
Finished Aug 10 05:24:52 PM PDT 24
Peak memory 208380 kb
Host smart-8e510d87-36f0-4f06-b08b-987faeca8936
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076140441 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst.3076140441
Directory /workspace/31.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/31.rstmgr_sw_rst_reset_race.3437650757
Short name T393
Test name
Test status
Simulation time 171203792 ps
CPU time 1.35 seconds
Started Aug 10 05:24:46 PM PDT 24
Finished Aug 10 05:24:52 PM PDT 24
Peak memory 200504 kb
Host smart-553f0202-87d0-4e0d-a9d2-0a14ce4cacc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437650757 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.rstmgr_sw_rst_reset_race.3437650757
Directory /workspace/31.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/32.rstmgr_alert_test.1878500436
Short name T306
Test name
Test status
Simulation time 74408139 ps
CPU time 0.77 seconds
Started Aug 10 05:24:41 PM PDT 24
Finished Aug 10 05:24:42 PM PDT 24
Peak memory 200156 kb
Host smart-beda5d9c-148e-4422-ada5-e2cc83d78d5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1878500436 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_alert_test.1878500436
Directory /workspace/32.rstmgr_alert_test/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_cnsty.3361060806
Short name T360
Test name
Test status
Simulation time 1912347410 ps
CPU time 7.32 seconds
Started Aug 10 05:24:38 PM PDT 24
Finished Aug 10 05:24:45 PM PDT 24
Peak memory 221600 kb
Host smart-18e91833-76cc-4235-bb53-b6d1550c3471
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361060806 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_cnsty.3361060806
Directory /workspace/32.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/32.rstmgr_leaf_rst_shadow_attack.4051111004
Short name T299
Test name
Test status
Simulation time 244162235 ps
CPU time 1.11 seconds
Started Aug 10 05:24:41 PM PDT 24
Finished Aug 10 05:24:43 PM PDT 24
Peak memory 217528 kb
Host smart-b1009a17-ecfa-4138-95eb-cabc1b174bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051111004 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_leaf_rst_shadow_attack.4051111004
Directory /workspace/32.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/32.rstmgr_por_stretcher.3420668645
Short name T384
Test name
Test status
Simulation time 97607205 ps
CPU time 0.82 seconds
Started Aug 10 05:24:38 PM PDT 24
Finished Aug 10 05:24:39 PM PDT 24
Peak memory 200196 kb
Host smart-662012ce-8b51-449d-9c4b-1ef619538a96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420668645 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_por_stretcher.3420668645
Directory /workspace/32.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/32.rstmgr_reset.306745138
Short name T483
Test name
Test status
Simulation time 1409249962 ps
CPU time 5.96 seconds
Started Aug 10 05:24:54 PM PDT 24
Finished Aug 10 05:25:00 PM PDT 24
Peak memory 200508 kb
Host smart-106982a8-411e-4f0a-a358-5576256622bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306745138 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_reset.306745138
Directory /workspace/32.rstmgr_reset/latest

Test location /workspace/coverage/default/32.rstmgr_sec_cm_scan_intersig_mubi.4052794574
Short name T122
Test name
Test status
Simulation time 101872786 ps
CPU time 0.95 seconds
Started Aug 10 05:25:07 PM PDT 24
Finished Aug 10 05:25:08 PM PDT 24
Peak memory 200356 kb
Host smart-4319b296-b6bd-4f86-b601-1b294e938645
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052794574 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sec_cm_scan_intersig_mubi.4052794574
Directory /workspace/32.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/32.rstmgr_smoke.2944698563
Short name T323
Test name
Test status
Simulation time 245914137 ps
CPU time 1.45 seconds
Started Aug 10 05:25:02 PM PDT 24
Finished Aug 10 05:25:09 PM PDT 24
Peak memory 200552 kb
Host smart-785ba415-fc01-4202-9855-4c84271fc43a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944698563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_smoke.2944698563
Directory /workspace/32.rstmgr_smoke/latest

Test location /workspace/coverage/default/32.rstmgr_stress_all.2319797229
Short name T434
Test name
Test status
Simulation time 480863446 ps
CPU time 2.6 seconds
Started Aug 10 05:24:40 PM PDT 24
Finished Aug 10 05:24:43 PM PDT 24
Peak memory 200316 kb
Host smart-fabb4977-b09f-41ab-9048-93eecca15be3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319797229 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_stress_all.2319797229
Directory /workspace/32.rstmgr_stress_all/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst.1045305456
Short name T325
Test name
Test status
Simulation time 258066186 ps
CPU time 1.72 seconds
Started Aug 10 05:24:47 PM PDT 24
Finished Aug 10 05:24:49 PM PDT 24
Peak memory 200344 kb
Host smart-3282c878-a02e-439e-ae66-00bb31a3d04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045305456 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst.1045305456
Directory /workspace/32.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/32.rstmgr_sw_rst_reset_race.917719734
Short name T304
Test name
Test status
Simulation time 113284846 ps
CPU time 0.91 seconds
Started Aug 10 05:24:49 PM PDT 24
Finished Aug 10 05:24:50 PM PDT 24
Peak memory 200352 kb
Host smart-75de2c29-8dd1-4776-b2a5-bc91b8348d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=917719734 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.rstmgr_sw_rst_reset_race.917719734
Directory /workspace/32.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/33.rstmgr_alert_test.1915864941
Short name T343
Test name
Test status
Simulation time 73654174 ps
CPU time 0.8 seconds
Started Aug 10 05:24:49 PM PDT 24
Finished Aug 10 05:24:50 PM PDT 24
Peak memory 199980 kb
Host smart-cabef780-5c2d-42d3-b55f-b3b6dec2c8a4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1915864941 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_alert_test.1915864941
Directory /workspace/33.rstmgr_alert_test/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_cnsty.3439799529
Short name T247
Test name
Test status
Simulation time 1909330695 ps
CPU time 6.86 seconds
Started Aug 10 05:24:42 PM PDT 24
Finished Aug 10 05:24:50 PM PDT 24
Peak memory 217756 kb
Host smart-76c240ef-4dc4-45b8-96a8-17f2525f39a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3439799529 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_cnsty.3439799529
Directory /workspace/33.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/33.rstmgr_leaf_rst_shadow_attack.3824485758
Short name T179
Test name
Test status
Simulation time 244203296 ps
CPU time 1.12 seconds
Started Aug 10 05:24:36 PM PDT 24
Finished Aug 10 05:24:37 PM PDT 24
Peak memory 217532 kb
Host smart-28ac7171-b4b5-4a3f-b041-ebed79bf3166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824485758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_leaf_rst_shadow_attack.3824485758
Directory /workspace/33.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/33.rstmgr_por_stretcher.3502310216
Short name T21
Test name
Test status
Simulation time 97783306 ps
CPU time 0.82 seconds
Started Aug 10 05:24:42 PM PDT 24
Finished Aug 10 05:24:43 PM PDT 24
Peak memory 200160 kb
Host smart-4a3ae0ef-7570-43c2-9e3c-e111ffd7106f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502310216 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_por_stretcher.3502310216
Directory /workspace/33.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/33.rstmgr_reset.1928268930
Short name T67
Test name
Test status
Simulation time 1368339145 ps
CPU time 5.54 seconds
Started Aug 10 05:24:42 PM PDT 24
Finished Aug 10 05:24:48 PM PDT 24
Peak memory 200552 kb
Host smart-4e9246c8-3861-4613-b96a-ead83b754064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928268930 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_reset.1928268930
Directory /workspace/33.rstmgr_reset/latest

Test location /workspace/coverage/default/33.rstmgr_sec_cm_scan_intersig_mubi.2215825176
Short name T522
Test name
Test status
Simulation time 98197020 ps
CPU time 0.98 seconds
Started Aug 10 05:24:50 PM PDT 24
Finished Aug 10 05:24:52 PM PDT 24
Peak memory 200244 kb
Host smart-a16afb89-89eb-44f8-a353-c0677e3a9e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2215825176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sec_cm_scan_intersig_mubi.2215825176
Directory /workspace/33.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/33.rstmgr_smoke.1968809489
Short name T329
Test name
Test status
Simulation time 119983508 ps
CPU time 1.27 seconds
Started Aug 10 05:24:43 PM PDT 24
Finished Aug 10 05:24:44 PM PDT 24
Peak memory 200528 kb
Host smart-5b0e321e-0257-45e2-83fa-55d59f19053c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968809489 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_smoke.1968809489
Directory /workspace/33.rstmgr_smoke/latest

Test location /workspace/coverage/default/33.rstmgr_stress_all.1701085083
Short name T257
Test name
Test status
Simulation time 873820652 ps
CPU time 3.92 seconds
Started Aug 10 05:25:01 PM PDT 24
Finished Aug 10 05:25:05 PM PDT 24
Peak memory 200448 kb
Host smart-51c1b068-5380-4430-bed0-1ea1c5fc72f5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1701085083 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_stress_all.1701085083
Directory /workspace/33.rstmgr_stress_all/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst.1099568005
Short name T531
Test name
Test status
Simulation time 114369826 ps
CPU time 1.42 seconds
Started Aug 10 05:24:40 PM PDT 24
Finished Aug 10 05:24:42 PM PDT 24
Peak memory 200308 kb
Host smart-d92e0db7-44e6-417a-ab61-094368777a4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1099568005 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst.1099568005
Directory /workspace/33.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/33.rstmgr_sw_rst_reset_race.1707991914
Short name T489
Test name
Test status
Simulation time 258660975 ps
CPU time 1.45 seconds
Started Aug 10 05:24:36 PM PDT 24
Finished Aug 10 05:24:38 PM PDT 24
Peak memory 200348 kb
Host smart-8ca0db70-a1f3-40a9-8b28-b0c854438bdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707991914 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.rstmgr_sw_rst_reset_race.1707991914
Directory /workspace/33.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/34.rstmgr_alert_test.2029985744
Short name T523
Test name
Test status
Simulation time 64274189 ps
CPU time 0.82 seconds
Started Aug 10 05:25:01 PM PDT 24
Finished Aug 10 05:25:01 PM PDT 24
Peak memory 200168 kb
Host smart-cba0b569-9020-4894-b693-7853a2221a48
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029985744 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_alert_test.2029985744
Directory /workspace/34.rstmgr_alert_test/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_cnsty.1908220505
Short name T404
Test name
Test status
Simulation time 1220089311 ps
CPU time 5.37 seconds
Started Aug 10 05:24:53 PM PDT 24
Finished Aug 10 05:24:59 PM PDT 24
Peak memory 217684 kb
Host smart-9f3acb61-2c62-4e68-b21c-fcc65b6516b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1908220505 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_cnsty.1908220505
Directory /workspace/34.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/34.rstmgr_leaf_rst_shadow_attack.3851819154
Short name T363
Test name
Test status
Simulation time 243742434 ps
CPU time 1 seconds
Started Aug 10 05:24:56 PM PDT 24
Finished Aug 10 05:24:57 PM PDT 24
Peak memory 217512 kb
Host smart-ea60d2b5-5329-45b8-8d16-8d249084006c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3851819154 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_leaf_rst_shadow_attack.3851819154
Directory /workspace/34.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/34.rstmgr_por_stretcher.2607337413
Short name T141
Test name
Test status
Simulation time 110360216 ps
CPU time 0.82 seconds
Started Aug 10 05:25:01 PM PDT 24
Finished Aug 10 05:25:02 PM PDT 24
Peak memory 200080 kb
Host smart-e99a9a04-3be2-41fe-bff7-bf4d7782bb60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607337413 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_por_stretcher.2607337413
Directory /workspace/34.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/34.rstmgr_reset.3936605113
Short name T409
Test name
Test status
Simulation time 1691465075 ps
CPU time 6.21 seconds
Started Aug 10 05:24:43 PM PDT 24
Finished Aug 10 05:24:54 PM PDT 24
Peak memory 200204 kb
Host smart-dac7675c-87e3-4f16-87ff-569e92ee5161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936605113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_reset.3936605113
Directory /workspace/34.rstmgr_reset/latest

Test location /workspace/coverage/default/34.rstmgr_sec_cm_scan_intersig_mubi.965836782
Short name T232
Test name
Test status
Simulation time 98741939 ps
CPU time 0.95 seconds
Started Aug 10 05:24:50 PM PDT 24
Finished Aug 10 05:24:52 PM PDT 24
Peak memory 200328 kb
Host smart-d580e46b-bade-4564-9cc8-4bf71cb45f5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965836782 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sec_cm_scan_intersig_mubi.965836782
Directory /workspace/34.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/34.rstmgr_smoke.1127214465
Short name T475
Test name
Test status
Simulation time 248233822 ps
CPU time 1.56 seconds
Started Aug 10 05:24:41 PM PDT 24
Finished Aug 10 05:24:42 PM PDT 24
Peak memory 200360 kb
Host smart-db7b7f71-e1e1-40da-9c9e-4c7971f1ab71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127214465 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_smoke.1127214465
Directory /workspace/34.rstmgr_smoke/latest

Test location /workspace/coverage/default/34.rstmgr_stress_all.3468269375
Short name T411
Test name
Test status
Simulation time 3388061720 ps
CPU time 17.68 seconds
Started Aug 10 05:24:49 PM PDT 24
Finished Aug 10 05:25:07 PM PDT 24
Peak memory 208712 kb
Host smart-ae16dfb7-31e1-4e17-b3ef-7822e45c0450
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468269375 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_stress_all.3468269375
Directory /workspace/34.rstmgr_stress_all/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst.1837787470
Short name T450
Test name
Test status
Simulation time 374690766 ps
CPU time 2.18 seconds
Started Aug 10 05:24:43 PM PDT 24
Finished Aug 10 05:24:50 PM PDT 24
Peak memory 200276 kb
Host smart-e18beb58-fbb1-4f26-825f-5f2caddb3df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837787470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst.1837787470
Directory /workspace/34.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/34.rstmgr_sw_rst_reset_race.1057581704
Short name T388
Test name
Test status
Simulation time 269238313 ps
CPU time 1.57 seconds
Started Aug 10 05:24:53 PM PDT 24
Finished Aug 10 05:24:55 PM PDT 24
Peak memory 200388 kb
Host smart-a725147a-b732-469b-a92e-df7899f6def0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057581704 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.rstmgr_sw_rst_reset_race.1057581704
Directory /workspace/34.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/35.rstmgr_alert_test.3315798387
Short name T217
Test name
Test status
Simulation time 74689786 ps
CPU time 0.78 seconds
Started Aug 10 05:24:41 PM PDT 24
Finished Aug 10 05:24:42 PM PDT 24
Peak memory 200132 kb
Host smart-567ab8b7-fe05-43a3-83fe-76b6efcd9b16
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315798387 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_alert_test.3315798387
Directory /workspace/35.rstmgr_alert_test/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_cnsty.4236742173
Short name T471
Test name
Test status
Simulation time 2165166034 ps
CPU time 8.76 seconds
Started Aug 10 05:24:49 PM PDT 24
Finished Aug 10 05:24:58 PM PDT 24
Peak memory 217808 kb
Host smart-51798acf-3c6f-410e-942c-6dce6b5290ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4236742173 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_cnsty.4236742173
Directory /workspace/35.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/35.rstmgr_leaf_rst_shadow_attack.4219219851
Short name T399
Test name
Test status
Simulation time 249282697 ps
CPU time 1.03 seconds
Started Aug 10 05:24:51 PM PDT 24
Finished Aug 10 05:24:52 PM PDT 24
Peak memory 217444 kb
Host smart-1c3ca93b-9b7a-4db7-91ff-cf0a2e25c759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219219851 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_leaf_rst_shadow_attack.4219219851
Directory /workspace/35.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/35.rstmgr_por_stretcher.4275495938
Short name T255
Test name
Test status
Simulation time 180734440 ps
CPU time 0.89 seconds
Started Aug 10 05:25:01 PM PDT 24
Finished Aug 10 05:25:02 PM PDT 24
Peak memory 200136 kb
Host smart-69b95223-653e-4330-80ce-200290b717a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4275495938 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_por_stretcher.4275495938
Directory /workspace/35.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/35.rstmgr_reset.2803631758
Short name T164
Test name
Test status
Simulation time 1350324432 ps
CPU time 5.6 seconds
Started Aug 10 05:25:16 PM PDT 24
Finished Aug 10 05:25:22 PM PDT 24
Peak memory 200600 kb
Host smart-68ee50c0-5ce6-4264-893a-da26295e2d97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803631758 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_reset.2803631758
Directory /workspace/35.rstmgr_reset/latest

Test location /workspace/coverage/default/35.rstmgr_sec_cm_scan_intersig_mubi.803300159
Short name T484
Test name
Test status
Simulation time 99698348 ps
CPU time 1 seconds
Started Aug 10 05:24:45 PM PDT 24
Finished Aug 10 05:24:46 PM PDT 24
Peak memory 200328 kb
Host smart-ecfddd43-958b-401a-890a-58455da17039
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803300159 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sec_cm_scan_intersig_mubi.803300159
Directory /workspace/35.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/35.rstmgr_smoke.1404956570
Short name T76
Test name
Test status
Simulation time 255278248 ps
CPU time 1.59 seconds
Started Aug 10 05:24:43 PM PDT 24
Finished Aug 10 05:24:45 PM PDT 24
Peak memory 200544 kb
Host smart-4c819530-3c83-4e14-a799-e1292c0470a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1404956570 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_smoke.1404956570
Directory /workspace/35.rstmgr_smoke/latest

Test location /workspace/coverage/default/35.rstmgr_stress_all.1744834713
Short name T92
Test name
Test status
Simulation time 3881013474 ps
CPU time 12.39 seconds
Started Aug 10 05:25:11 PM PDT 24
Finished Aug 10 05:25:24 PM PDT 24
Peak memory 200556 kb
Host smart-4897af8c-02a7-4b4a-b3ac-5788fd926784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744834713 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_stress_all.1744834713
Directory /workspace/35.rstmgr_stress_all/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst.4019867342
Short name T248
Test name
Test status
Simulation time 388990141 ps
CPU time 2.52 seconds
Started Aug 10 05:25:00 PM PDT 24
Finished Aug 10 05:25:03 PM PDT 24
Peak memory 200172 kb
Host smart-3d133b84-c39a-4aae-93ee-7d59e398359b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019867342 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst.4019867342
Directory /workspace/35.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/35.rstmgr_sw_rst_reset_race.2600324395
Short name T406
Test name
Test status
Simulation time 122534257 ps
CPU time 1.01 seconds
Started Aug 10 05:24:49 PM PDT 24
Finished Aug 10 05:24:50 PM PDT 24
Peak memory 200248 kb
Host smart-45d9c1ee-9c8d-465f-8d61-28799b54bc14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2600324395 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.rstmgr_sw_rst_reset_race.2600324395
Directory /workspace/35.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/36.rstmgr_alert_test.3477122125
Short name T52
Test name
Test status
Simulation time 62606461 ps
CPU time 0.77 seconds
Started Aug 10 05:24:49 PM PDT 24
Finished Aug 10 05:24:50 PM PDT 24
Peak memory 200112 kb
Host smart-ab686796-328c-4e21-907f-c619d8a5cdc1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477122125 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_alert_test.3477122125
Directory /workspace/36.rstmgr_alert_test/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_cnsty.1829327003
Short name T318
Test name
Test status
Simulation time 1227531223 ps
CPU time 5.73 seconds
Started Aug 10 05:25:07 PM PDT 24
Finished Aug 10 05:25:13 PM PDT 24
Peak memory 217736 kb
Host smart-72904d75-486a-4d4b-acc1-8aa5d2fcf973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829327003 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_cnsty.1829327003
Directory /workspace/36.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/36.rstmgr_leaf_rst_shadow_attack.2812931185
Short name T330
Test name
Test status
Simulation time 244623306 ps
CPU time 1.07 seconds
Started Aug 10 05:25:06 PM PDT 24
Finished Aug 10 05:25:07 PM PDT 24
Peak memory 217536 kb
Host smart-70e48a47-4a55-4e83-93a7-a4ae995143a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812931185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_leaf_rst_shadow_attack.2812931185
Directory /workspace/36.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/36.rstmgr_por_stretcher.2553113631
Short name T155
Test name
Test status
Simulation time 166249269 ps
CPU time 0.87 seconds
Started Aug 10 05:25:06 PM PDT 24
Finished Aug 10 05:25:07 PM PDT 24
Peak memory 200036 kb
Host smart-4dda58a4-38b9-4c5c-9bd5-e96cf6fa32cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553113631 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_por_stretcher.2553113631
Directory /workspace/36.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/36.rstmgr_reset.366081309
Short name T37
Test name
Test status
Simulation time 850659572 ps
CPU time 3.92 seconds
Started Aug 10 05:25:06 PM PDT 24
Finished Aug 10 05:25:10 PM PDT 24
Peak memory 200436 kb
Host smart-cc221fd3-93db-4eac-a928-9dbb71fe1e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366081309 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_reset.366081309
Directory /workspace/36.rstmgr_reset/latest

Test location /workspace/coverage/default/36.rstmgr_sec_cm_scan_intersig_mubi.1240854652
Short name T326
Test name
Test status
Simulation time 111249546 ps
CPU time 0.98 seconds
Started Aug 10 05:24:58 PM PDT 24
Finished Aug 10 05:24:59 PM PDT 24
Peak memory 200232 kb
Host smart-3f840df0-0ef8-4065-ae77-7f1885420068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240854652 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sec_cm_scan_intersig_mubi.1240854652
Directory /workspace/36.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/36.rstmgr_smoke.3974659196
Short name T75
Test name
Test status
Simulation time 109579321 ps
CPU time 1.24 seconds
Started Aug 10 05:24:59 PM PDT 24
Finished Aug 10 05:25:00 PM PDT 24
Peak memory 200372 kb
Host smart-99c1509b-2cce-4a06-b09e-9131165e3c4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974659196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_smoke.3974659196
Directory /workspace/36.rstmgr_smoke/latest

Test location /workspace/coverage/default/36.rstmgr_stress_all.3224852122
Short name T198
Test name
Test status
Simulation time 13658261794 ps
CPU time 49.26 seconds
Started Aug 10 05:25:13 PM PDT 24
Finished Aug 10 05:26:02 PM PDT 24
Peak memory 208844 kb
Host smart-9a94c4ba-78ad-4522-bc18-a5904b116413
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224852122 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_stress_all.3224852122
Directory /workspace/36.rstmgr_stress_all/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst.1390191563
Short name T540
Test name
Test status
Simulation time 446625688 ps
CPU time 2.61 seconds
Started Aug 10 05:24:50 PM PDT 24
Finished Aug 10 05:24:53 PM PDT 24
Peak memory 200220 kb
Host smart-2ca9c816-372c-406e-b37a-3a2887f872e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390191563 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst.1390191563
Directory /workspace/36.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/36.rstmgr_sw_rst_reset_race.1518996726
Short name T480
Test name
Test status
Simulation time 76860205 ps
CPU time 0.86 seconds
Started Aug 10 05:25:11 PM PDT 24
Finished Aug 10 05:25:12 PM PDT 24
Peak memory 200328 kb
Host smart-26d835d6-233b-42fe-8956-0ce84eb143d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1518996726 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.rstmgr_sw_rst_reset_race.1518996726
Directory /workspace/36.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/37.rstmgr_alert_test.3673523369
Short name T420
Test name
Test status
Simulation time 99618760 ps
CPU time 0.85 seconds
Started Aug 10 05:25:01 PM PDT 24
Finished Aug 10 05:25:02 PM PDT 24
Peak memory 200152 kb
Host smart-153ce807-4057-4283-847f-2758888cdebe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673523369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_alert_test.3673523369
Directory /workspace/37.rstmgr_alert_test/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_cnsty.2241960157
Short name T258
Test name
Test status
Simulation time 1232325380 ps
CPU time 5.73 seconds
Started Aug 10 05:25:04 PM PDT 24
Finished Aug 10 05:25:10 PM PDT 24
Peak memory 217736 kb
Host smart-738876c9-aac4-4db7-b144-786eca698b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241960157 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_cnsty.2241960157
Directory /workspace/37.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/37.rstmgr_leaf_rst_shadow_attack.1654435442
Short name T392
Test name
Test status
Simulation time 244608996 ps
CPU time 1.05 seconds
Started Aug 10 05:24:57 PM PDT 24
Finished Aug 10 05:24:58 PM PDT 24
Peak memory 217404 kb
Host smart-5f7da8f4-67bf-44a8-9dcd-d2c7cf14a898
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654435442 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_leaf_rst_shadow_attack.1654435442
Directory /workspace/37.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/37.rstmgr_por_stretcher.477290147
Short name T18
Test name
Test status
Simulation time 122777939 ps
CPU time 0.8 seconds
Started Aug 10 05:24:58 PM PDT 24
Finished Aug 10 05:24:59 PM PDT 24
Peak memory 200148 kb
Host smart-aa700c5b-e957-4b17-9a79-45a5c9660c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=477290147 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_por_stretcher.477290147
Directory /workspace/37.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/37.rstmgr_reset.2865180215
Short name T438
Test name
Test status
Simulation time 1826454300 ps
CPU time 6.47 seconds
Started Aug 10 05:25:06 PM PDT 24
Finished Aug 10 05:25:13 PM PDT 24
Peak memory 200528 kb
Host smart-71061c15-8043-4159-b086-993ffea03a92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2865180215 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_reset.2865180215
Directory /workspace/37.rstmgr_reset/latest

Test location /workspace/coverage/default/37.rstmgr_sec_cm_scan_intersig_mubi.4093834508
Short name T428
Test name
Test status
Simulation time 149739712 ps
CPU time 1.16 seconds
Started Aug 10 05:24:58 PM PDT 24
Finished Aug 10 05:25:00 PM PDT 24
Peak memory 200340 kb
Host smart-e5cf041e-91c4-4e3c-991b-f778d09d83f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093834508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sec_cm_scan_intersig_mubi.4093834508
Directory /workspace/37.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/37.rstmgr_smoke.146744028
Short name T65
Test name
Test status
Simulation time 203523035 ps
CPU time 1.39 seconds
Started Aug 10 05:25:05 PM PDT 24
Finished Aug 10 05:25:07 PM PDT 24
Peak memory 200460 kb
Host smart-46e00f7a-d344-460e-b913-e5dfa8bb4455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146744028 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_smoke.146744028
Directory /workspace/37.rstmgr_smoke/latest

Test location /workspace/coverage/default/37.rstmgr_stress_all.756275746
Short name T317
Test name
Test status
Simulation time 3719776087 ps
CPU time 12.26 seconds
Started Aug 10 05:24:56 PM PDT 24
Finished Aug 10 05:25:08 PM PDT 24
Peak memory 200588 kb
Host smart-acebaa1a-9e20-4734-921d-055056e09c91
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756275746 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_stress_all.756275746
Directory /workspace/37.rstmgr_stress_all/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst.3664942885
Short name T333
Test name
Test status
Simulation time 382000337 ps
CPU time 2.22 seconds
Started Aug 10 05:24:52 PM PDT 24
Finished Aug 10 05:24:54 PM PDT 24
Peak memory 200308 kb
Host smart-2d8a3f42-c643-4107-b36f-a80603b5cd2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3664942885 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst.3664942885
Directory /workspace/37.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/37.rstmgr_sw_rst_reset_race.1587975435
Short name T413
Test name
Test status
Simulation time 161571705 ps
CPU time 1.21 seconds
Started Aug 10 05:25:11 PM PDT 24
Finished Aug 10 05:25:12 PM PDT 24
Peak memory 200372 kb
Host smart-8ede4f8b-5893-4ae2-be91-ff46ac249b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587975435 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.rstmgr_sw_rst_reset_race.1587975435
Directory /workspace/37.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/38.rstmgr_alert_test.3073026620
Short name T430
Test name
Test status
Simulation time 74234118 ps
CPU time 0.73 seconds
Started Aug 10 05:25:08 PM PDT 24
Finished Aug 10 05:25:09 PM PDT 24
Peak memory 200044 kb
Host smart-f9216aeb-2e41-4d91-a94c-a70ee55a247b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073026620 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_alert_test.3073026620
Directory /workspace/38.rstmgr_alert_test/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_cnsty.2922473108
Short name T2
Test name
Test status
Simulation time 2172088628 ps
CPU time 7.46 seconds
Started Aug 10 05:25:13 PM PDT 24
Finished Aug 10 05:25:21 PM PDT 24
Peak memory 217796 kb
Host smart-a9de176b-3ef1-4efe-a751-bf5e1f2ec12b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922473108 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_cnsty.2922473108
Directory /workspace/38.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/38.rstmgr_leaf_rst_shadow_attack.555925689
Short name T63
Test name
Test status
Simulation time 243956804 ps
CPU time 1.05 seconds
Started Aug 10 05:25:11 PM PDT 24
Finished Aug 10 05:25:12 PM PDT 24
Peak memory 217436 kb
Host smart-6b572387-ad7e-43ab-a3eb-6fbd5607c5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555925689 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_leaf_rst_shadow_attack.555925689
Directory /workspace/38.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/38.rstmgr_por_stretcher.2554108041
Short name T5
Test name
Test status
Simulation time 138988859 ps
CPU time 0.8 seconds
Started Aug 10 05:25:00 PM PDT 24
Finished Aug 10 05:25:01 PM PDT 24
Peak memory 200168 kb
Host smart-ef2cf309-5891-4de1-815d-976a9a7eee05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554108041 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_por_stretcher.2554108041
Directory /workspace/38.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/38.rstmgr_reset.3304471516
Short name T439
Test name
Test status
Simulation time 1375418930 ps
CPU time 5.59 seconds
Started Aug 10 05:24:59 PM PDT 24
Finished Aug 10 05:25:05 PM PDT 24
Peak memory 200568 kb
Host smart-b37e3188-e0af-4131-a9c8-a9850153c430
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3304471516 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_reset.3304471516
Directory /workspace/38.rstmgr_reset/latest

Test location /workspace/coverage/default/38.rstmgr_sec_cm_scan_intersig_mubi.957996195
Short name T62
Test name
Test status
Simulation time 141529749 ps
CPU time 1.1 seconds
Started Aug 10 05:25:05 PM PDT 24
Finished Aug 10 05:25:07 PM PDT 24
Peak memory 200388 kb
Host smart-1b8cbc60-09ae-4200-9d91-e2829dff9153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=957996195 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sec_cm_scan_intersig_mubi.957996195
Directory /workspace/38.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/38.rstmgr_smoke.3122893484
Short name T127
Test name
Test status
Simulation time 124159854 ps
CPU time 1.19 seconds
Started Aug 10 05:25:03 PM PDT 24
Finished Aug 10 05:25:09 PM PDT 24
Peak memory 200428 kb
Host smart-b0631451-233b-4293-aee1-a452bcea0e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3122893484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_smoke.3122893484
Directory /workspace/38.rstmgr_smoke/latest

Test location /workspace/coverage/default/38.rstmgr_stress_all.3839396093
Short name T38
Test name
Test status
Simulation time 4644901091 ps
CPU time 20.55 seconds
Started Aug 10 05:24:56 PM PDT 24
Finished Aug 10 05:25:16 PM PDT 24
Peak memory 200436 kb
Host smart-bd64ddac-e247-4969-8896-d542208c9856
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3839396093 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_stress_all.3839396093
Directory /workspace/38.rstmgr_stress_all/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst.3397187416
Short name T526
Test name
Test status
Simulation time 389497552 ps
CPU time 2.18 seconds
Started Aug 10 05:25:04 PM PDT 24
Finished Aug 10 05:25:06 PM PDT 24
Peak memory 208496 kb
Host smart-48665214-1321-4047-b87c-fc60e8df04de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3397187416 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst.3397187416
Directory /workspace/38.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/38.rstmgr_sw_rst_reset_race.1300573143
Short name T161
Test name
Test status
Simulation time 235872409 ps
CPU time 1.35 seconds
Started Aug 10 05:25:04 PM PDT 24
Finished Aug 10 05:25:05 PM PDT 24
Peak memory 200364 kb
Host smart-69402269-c3c3-422a-a616-03d853160970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300573143 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.rstmgr_sw_rst_reset_race.1300573143
Directory /workspace/38.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/39.rstmgr_alert_test.1381845177
Short name T151
Test name
Test status
Simulation time 71444759 ps
CPU time 0.76 seconds
Started Aug 10 05:24:52 PM PDT 24
Finished Aug 10 05:24:53 PM PDT 24
Peak memory 200004 kb
Host smart-72944727-6f47-4632-88c2-ec83aa312265
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1381845177 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_alert_test.1381845177
Directory /workspace/39.rstmgr_alert_test/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_cnsty.84468532
Short name T309
Test name
Test status
Simulation time 1908427419 ps
CPU time 6.73 seconds
Started Aug 10 05:24:52 PM PDT 24
Finished Aug 10 05:24:58 PM PDT 24
Peak memory 216936 kb
Host smart-a40ff9e1-a0f3-491d-aa4d-43e8235d1b3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=84468532 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_cnsty.84468532
Directory /workspace/39.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/39.rstmgr_leaf_rst_shadow_attack.428778488
Short name T311
Test name
Test status
Simulation time 243616720 ps
CPU time 1.07 seconds
Started Aug 10 05:25:07 PM PDT 24
Finished Aug 10 05:25:08 PM PDT 24
Peak memory 217496 kb
Host smart-43b363da-7a27-4489-a851-b802213e36c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428778488 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_leaf_rst_shadow_attack.428778488
Directory /workspace/39.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/39.rstmgr_por_stretcher.1722463383
Short name T143
Test name
Test status
Simulation time 261949182 ps
CPU time 1.12 seconds
Started Aug 10 05:25:17 PM PDT 24
Finished Aug 10 05:25:19 PM PDT 24
Peak memory 200144 kb
Host smart-d4e7249e-665f-4468-a335-343495c42944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722463383 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_por_stretcher.1722463383
Directory /workspace/39.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/39.rstmgr_reset.3452530954
Short name T456
Test name
Test status
Simulation time 1699179385 ps
CPU time 6.7 seconds
Started Aug 10 05:25:14 PM PDT 24
Finished Aug 10 05:25:21 PM PDT 24
Peak memory 200552 kb
Host smart-af1d1f9e-88dd-48d3-98ea-0f44c2223641
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452530954 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_reset.3452530954
Directory /workspace/39.rstmgr_reset/latest

Test location /workspace/coverage/default/39.rstmgr_sec_cm_scan_intersig_mubi.3121763732
Short name T279
Test name
Test status
Simulation time 152452672 ps
CPU time 1.12 seconds
Started Aug 10 05:25:03 PM PDT 24
Finished Aug 10 05:25:04 PM PDT 24
Peak memory 200192 kb
Host smart-4f4eb631-fe87-48ee-9c6f-2fef8e53f731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121763732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sec_cm_scan_intersig_mubi.3121763732
Directory /workspace/39.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/39.rstmgr_smoke.138812483
Short name T64
Test name
Test status
Simulation time 231860223 ps
CPU time 1.46 seconds
Started Aug 10 05:25:01 PM PDT 24
Finished Aug 10 05:25:03 PM PDT 24
Peak memory 200524 kb
Host smart-885c3797-c831-4455-9295-0aa0bb1852c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138812483 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_smoke.138812483
Directory /workspace/39.rstmgr_smoke/latest

Test location /workspace/coverage/default/39.rstmgr_stress_all.500093109
Short name T521
Test name
Test status
Simulation time 10219198751 ps
CPU time 34.43 seconds
Started Aug 10 05:25:01 PM PDT 24
Finished Aug 10 05:25:35 PM PDT 24
Peak memory 200600 kb
Host smart-c5d757f5-2b93-42a7-942f-3539820dcce5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500093109 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_stress_all.500093109
Directory /workspace/39.rstmgr_stress_all/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst.2717676727
Short name T195
Test name
Test status
Simulation time 348872661 ps
CPU time 2.29 seconds
Started Aug 10 05:25:16 PM PDT 24
Finished Aug 10 05:25:18 PM PDT 24
Peak memory 200272 kb
Host smart-a2363bcc-c662-4d11-82ab-b7da69d47d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717676727 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst.2717676727
Directory /workspace/39.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/39.rstmgr_sw_rst_reset_race.2986922716
Short name T1
Test name
Test status
Simulation time 132912210 ps
CPU time 1.03 seconds
Started Aug 10 05:25:09 PM PDT 24
Finished Aug 10 05:25:10 PM PDT 24
Peak memory 200296 kb
Host smart-d4ac934e-9c5b-4c52-94bd-d1b59581fc9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986922716 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.rstmgr_sw_rst_reset_race.2986922716
Directory /workspace/39.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/4.rstmgr_alert_test.367684403
Short name T458
Test name
Test status
Simulation time 58993508 ps
CPU time 0.74 seconds
Started Aug 10 05:24:31 PM PDT 24
Finished Aug 10 05:24:31 PM PDT 24
Peak memory 199996 kb
Host smart-13e54e3b-23ed-4985-865b-6bc75329b2f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367684403 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_alert_test.367684403
Directory /workspace/4.rstmgr_alert_test/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_cnsty.2346002603
Short name T35
Test name
Test status
Simulation time 2363762865 ps
CPU time 8.87 seconds
Started Aug 10 05:24:16 PM PDT 24
Finished Aug 10 05:24:25 PM PDT 24
Peak memory 217868 kb
Host smart-322d9386-b2b1-4573-bc12-1053a408446e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346002603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_cnsty.2346002603
Directory /workspace/4.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/4.rstmgr_leaf_rst_shadow_attack.1107359868
Short name T457
Test name
Test status
Simulation time 244691181 ps
CPU time 1.07 seconds
Started Aug 10 05:24:23 PM PDT 24
Finished Aug 10 05:24:25 PM PDT 24
Peak memory 217488 kb
Host smart-26141281-ff45-4bdb-b101-3c2138b740e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1107359868 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_leaf_rst_shadow_attack.1107359868
Directory /workspace/4.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/4.rstmgr_por_stretcher.2572623334
Short name T342
Test name
Test status
Simulation time 185289011 ps
CPU time 0.88 seconds
Started Aug 10 05:24:35 PM PDT 24
Finished Aug 10 05:24:36 PM PDT 24
Peak memory 200108 kb
Host smart-8aab0258-d9f2-41b9-9f68-e27efc683857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572623334 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_por_stretcher.2572623334
Directory /workspace/4.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/4.rstmgr_reset.4035416947
Short name T184
Test name
Test status
Simulation time 2074304392 ps
CPU time 7.58 seconds
Started Aug 10 05:24:30 PM PDT 24
Finished Aug 10 05:24:38 PM PDT 24
Peak memory 200660 kb
Host smart-7533186c-5b31-4702-9dd1-2b188384db2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035416947 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_reset.4035416947
Directory /workspace/4.rstmgr_reset/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm.2092641453
Short name T56
Test name
Test status
Simulation time 16643209913 ps
CPU time 25.72 seconds
Started Aug 10 05:24:25 PM PDT 24
Finished Aug 10 05:24:50 PM PDT 24
Peak memory 218292 kb
Host smart-b21ded13-8e21-4f19-aec2-987c95b10197
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092641453 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm.2092641453
Directory /workspace/4.rstmgr_sec_cm/latest

Test location /workspace/coverage/default/4.rstmgr_sec_cm_scan_intersig_mubi.1218031204
Short name T319
Test name
Test status
Simulation time 112360370 ps
CPU time 1.04 seconds
Started Aug 10 05:24:12 PM PDT 24
Finished Aug 10 05:24:13 PM PDT 24
Peak memory 200304 kb
Host smart-0a0d574f-dac0-44a6-81b4-d3bfb5ca147b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218031204 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sec_cm_scan_intersig_mubi.1218031204
Directory /workspace/4.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/4.rstmgr_smoke.2557093582
Short name T22
Test name
Test status
Simulation time 109657422 ps
CPU time 1.17 seconds
Started Aug 10 05:24:13 PM PDT 24
Finished Aug 10 05:24:15 PM PDT 24
Peak memory 200544 kb
Host smart-36728889-fa35-4216-bd70-c7121c341b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557093582 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_smoke.2557093582
Directory /workspace/4.rstmgr_smoke/latest

Test location /workspace/coverage/default/4.rstmgr_stress_all.3696819310
Short name T78
Test name
Test status
Simulation time 4381572006 ps
CPU time 21.32 seconds
Started Aug 10 05:24:16 PM PDT 24
Finished Aug 10 05:24:38 PM PDT 24
Peak memory 208844 kb
Host smart-d26511fe-e8f5-40d2-9e6b-c6de99e01b5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696819310 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_stress_all.3696819310
Directory /workspace/4.rstmgr_stress_all/latest

Test location /workspace/coverage/default/4.rstmgr_sw_rst_reset_race.3849948313
Short name T542
Test name
Test status
Simulation time 79320611 ps
CPU time 0.83 seconds
Started Aug 10 05:24:14 PM PDT 24
Finished Aug 10 05:24:15 PM PDT 24
Peak memory 200360 kb
Host smart-e06640a7-7f2c-41c9-84d9-dd8302bfddbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849948313 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.rstmgr_sw_rst_reset_race.3849948313
Directory /workspace/4.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/40.rstmgr_alert_test.1979788826
Short name T187
Test name
Test status
Simulation time 103070413 ps
CPU time 0.86 seconds
Started Aug 10 05:25:23 PM PDT 24
Finished Aug 10 05:25:24 PM PDT 24
Peak memory 200176 kb
Host smart-375932e7-08db-42b5-bb28-bb4010aeae65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979788826 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_alert_test.1979788826
Directory /workspace/40.rstmgr_alert_test/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_cnsty.2691350323
Short name T524
Test name
Test status
Simulation time 2352219513 ps
CPU time 8.04 seconds
Started Aug 10 05:25:16 PM PDT 24
Finished Aug 10 05:25:24 PM PDT 24
Peak memory 221672 kb
Host smart-53389a76-9156-4e12-8c24-a2129528907f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691350323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_cnsty.2691350323
Directory /workspace/40.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/40.rstmgr_leaf_rst_shadow_attack.3511091046
Short name T235
Test name
Test status
Simulation time 245650263 ps
CPU time 1.08 seconds
Started Aug 10 05:25:16 PM PDT 24
Finished Aug 10 05:25:17 PM PDT 24
Peak memory 217484 kb
Host smart-2b11bfba-4d79-4bae-9866-c00349baa808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511091046 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_leaf_rst_shadow_attack.3511091046
Directory /workspace/40.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/40.rstmgr_por_stretcher.1858984400
Short name T527
Test name
Test status
Simulation time 182858712 ps
CPU time 0.94 seconds
Started Aug 10 05:25:05 PM PDT 24
Finished Aug 10 05:25:06 PM PDT 24
Peak memory 200188 kb
Host smart-09c493ad-af4b-443a-9083-952f5d914fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858984400 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_por_stretcher.1858984400
Directory /workspace/40.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/40.rstmgr_reset.410301698
Short name T246
Test name
Test status
Simulation time 1705804029 ps
CPU time 6.57 seconds
Started Aug 10 05:25:05 PM PDT 24
Finished Aug 10 05:25:12 PM PDT 24
Peak memory 200568 kb
Host smart-9ef35c63-2f9c-4c98-9e34-741ea95939b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410301698 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_reset.410301698
Directory /workspace/40.rstmgr_reset/latest

Test location /workspace/coverage/default/40.rstmgr_sec_cm_scan_intersig_mubi.615529562
Short name T509
Test name
Test status
Simulation time 97739362 ps
CPU time 1.02 seconds
Started Aug 10 05:25:29 PM PDT 24
Finished Aug 10 05:25:30 PM PDT 24
Peak memory 200364 kb
Host smart-fe00ea81-c7eb-4ddd-8ee2-96b2ef8b9cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615529562 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sec_cm_scan_intersig_mubi.615529562
Directory /workspace/40.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/40.rstmgr_smoke.4164940127
Short name T357
Test name
Test status
Simulation time 207903499 ps
CPU time 1.35 seconds
Started Aug 10 05:25:03 PM PDT 24
Finished Aug 10 05:25:04 PM PDT 24
Peak memory 200492 kb
Host smart-c26f7a89-5db7-4577-a411-89ecf8c8a1a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164940127 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_smoke.4164940127
Directory /workspace/40.rstmgr_smoke/latest

Test location /workspace/coverage/default/40.rstmgr_stress_all.1022014470
Short name T280
Test name
Test status
Simulation time 2533336212 ps
CPU time 9.76 seconds
Started Aug 10 05:25:30 PM PDT 24
Finished Aug 10 05:25:40 PM PDT 24
Peak memory 216700 kb
Host smart-abaf3d2d-04ea-4041-bd1f-c226877cff21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022014470 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_stress_all.1022014470
Directory /workspace/40.rstmgr_stress_all/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst.1245660271
Short name T216
Test name
Test status
Simulation time 309571445 ps
CPU time 1.97 seconds
Started Aug 10 05:25:05 PM PDT 24
Finished Aug 10 05:25:07 PM PDT 24
Peak memory 208444 kb
Host smart-f04030f9-bd6b-4d8c-973f-57ae2afe7504
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245660271 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst.1245660271
Directory /workspace/40.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/40.rstmgr_sw_rst_reset_race.3035494628
Short name T441
Test name
Test status
Simulation time 147031334 ps
CPU time 1.18 seconds
Started Aug 10 05:25:05 PM PDT 24
Finished Aug 10 05:25:07 PM PDT 24
Peak memory 200340 kb
Host smart-f24d0097-022c-434c-80d8-c8ff45b8f7d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035494628 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.rstmgr_sw_rst_reset_race.3035494628
Directory /workspace/40.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/41.rstmgr_alert_test.1642975176
Short name T348
Test name
Test status
Simulation time 79076755 ps
CPU time 0.79 seconds
Started Aug 10 05:25:13 PM PDT 24
Finished Aug 10 05:25:14 PM PDT 24
Peak memory 200176 kb
Host smart-5eded979-04dc-4e58-a120-d9685ce215d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642975176 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_alert_test.1642975176
Directory /workspace/41.rstmgr_alert_test/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_cnsty.1496437137
Short name T25
Test name
Test status
Simulation time 1225408511 ps
CPU time 5.75 seconds
Started Aug 10 05:25:11 PM PDT 24
Finished Aug 10 05:25:17 PM PDT 24
Peak memory 221732 kb
Host smart-8aa9e3dc-68f5-406f-9a15-48096a6e6a87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496437137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_cnsty.1496437137
Directory /workspace/41.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/41.rstmgr_leaf_rst_shadow_attack.4099175916
Short name T423
Test name
Test status
Simulation time 244707227 ps
CPU time 1.01 seconds
Started Aug 10 05:25:07 PM PDT 24
Finished Aug 10 05:25:13 PM PDT 24
Peak memory 217512 kb
Host smart-6b6312c0-4e81-4710-8da8-3937d611ef14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099175916 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_leaf_rst_shadow_attack.4099175916
Directory /workspace/41.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/41.rstmgr_por_stretcher.2158139555
Short name T371
Test name
Test status
Simulation time 192541010 ps
CPU time 0.86 seconds
Started Aug 10 05:25:14 PM PDT 24
Finished Aug 10 05:25:14 PM PDT 24
Peak memory 200048 kb
Host smart-b7e62ec2-80bd-4038-ba43-9de7f453d6ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158139555 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_por_stretcher.2158139555
Directory /workspace/41.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/41.rstmgr_reset.1956520133
Short name T482
Test name
Test status
Simulation time 1001909261 ps
CPU time 5.19 seconds
Started Aug 10 05:25:12 PM PDT 24
Finished Aug 10 05:25:17 PM PDT 24
Peak memory 200744 kb
Host smart-52d54f58-8b80-4795-bc79-26b3f26e6d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956520133 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_reset.1956520133
Directory /workspace/41.rstmgr_reset/latest

Test location /workspace/coverage/default/41.rstmgr_sec_cm_scan_intersig_mubi.2968073200
Short name T405
Test name
Test status
Simulation time 108028677 ps
CPU time 1 seconds
Started Aug 10 05:25:05 PM PDT 24
Finished Aug 10 05:25:06 PM PDT 24
Peak memory 200372 kb
Host smart-ae48aa9d-ee87-45b1-abfd-d063792dfc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2968073200 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sec_cm_scan_intersig_mubi.2968073200
Directory /workspace/41.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/41.rstmgr_smoke.2445932508
Short name T301
Test name
Test status
Simulation time 253291141 ps
CPU time 1.53 seconds
Started Aug 10 05:25:12 PM PDT 24
Finished Aug 10 05:25:13 PM PDT 24
Peak memory 200484 kb
Host smart-ed4dd828-d947-4614-928f-632804b68cfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2445932508 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_smoke.2445932508
Directory /workspace/41.rstmgr_smoke/latest

Test location /workspace/coverage/default/41.rstmgr_stress_all.1678718922
Short name T427
Test name
Test status
Simulation time 2791044276 ps
CPU time 13.6 seconds
Started Aug 10 05:25:12 PM PDT 24
Finished Aug 10 05:25:25 PM PDT 24
Peak memory 208700 kb
Host smart-8f4ac914-5715-4ba0-ba9b-d3cc9d90121a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678718922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_stress_all.1678718922
Directory /workspace/41.rstmgr_stress_all/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst.1304432732
Short name T387
Test name
Test status
Simulation time 553153654 ps
CPU time 2.67 seconds
Started Aug 10 05:25:17 PM PDT 24
Finished Aug 10 05:25:20 PM PDT 24
Peak memory 200308 kb
Host smart-a90309cd-e11b-44c2-97b3-570c79eb0334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1304432732 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst.1304432732
Directory /workspace/41.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/41.rstmgr_sw_rst_reset_race.3093658588
Short name T365
Test name
Test status
Simulation time 259024925 ps
CPU time 1.39 seconds
Started Aug 10 05:25:11 PM PDT 24
Finished Aug 10 05:25:13 PM PDT 24
Peak memory 200340 kb
Host smart-b24499d9-80f8-4509-a9ff-3c371a6e84a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3093658588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.rstmgr_sw_rst_reset_race.3093658588
Directory /workspace/41.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/42.rstmgr_alert_test.52040234
Short name T538
Test name
Test status
Simulation time 62027766 ps
CPU time 0.74 seconds
Started Aug 10 05:25:24 PM PDT 24
Finished Aug 10 05:25:25 PM PDT 24
Peak memory 200000 kb
Host smart-aded0c87-78dc-4ed5-bd06-9a201dd55753
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52040234 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_alert_test.52040234
Directory /workspace/42.rstmgr_alert_test/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_cnsty.1780991429
Short name T452
Test name
Test status
Simulation time 1889888881 ps
CPU time 7.25 seconds
Started Aug 10 05:25:09 PM PDT 24
Finished Aug 10 05:25:16 PM PDT 24
Peak memory 217712 kb
Host smart-af759766-f192-4301-808a-ec630fec4ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1780991429 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_cnsty.1780991429
Directory /workspace/42.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/42.rstmgr_leaf_rst_shadow_attack.1783083535
Short name T391
Test name
Test status
Simulation time 244201732 ps
CPU time 1.1 seconds
Started Aug 10 05:25:02 PM PDT 24
Finished Aug 10 05:25:04 PM PDT 24
Peak memory 217556 kb
Host smart-a468aa4a-3c0b-446a-9340-28316624f63a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783083535 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_leaf_rst_shadow_attack.1783083535
Directory /workspace/42.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/42.rstmgr_por_stretcher.3283329683
Short name T442
Test name
Test status
Simulation time 215620535 ps
CPU time 0.98 seconds
Started Aug 10 05:25:27 PM PDT 24
Finished Aug 10 05:25:29 PM PDT 24
Peak memory 200136 kb
Host smart-01294a70-ea16-4f24-99fd-4b032052a2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3283329683 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_por_stretcher.3283329683
Directory /workspace/42.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/42.rstmgr_reset.2910248694
Short name T467
Test name
Test status
Simulation time 1101089372 ps
CPU time 5.76 seconds
Started Aug 10 05:25:16 PM PDT 24
Finished Aug 10 05:25:22 PM PDT 24
Peak memory 200548 kb
Host smart-efdba0b2-afcb-42fc-af8b-5504a197ecbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910248694 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_reset.2910248694
Directory /workspace/42.rstmgr_reset/latest

Test location /workspace/coverage/default/42.rstmgr_sec_cm_scan_intersig_mubi.3901999543
Short name T12
Test name
Test status
Simulation time 111206555 ps
CPU time 1.04 seconds
Started Aug 10 05:25:07 PM PDT 24
Finished Aug 10 05:25:08 PM PDT 24
Peak memory 200380 kb
Host smart-260750ec-3aaa-49bb-9cda-d147ed57d9d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3901999543 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sec_cm_scan_intersig_mubi.3901999543
Directory /workspace/42.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/42.rstmgr_smoke.660861339
Short name T410
Test name
Test status
Simulation time 229278965 ps
CPU time 1.47 seconds
Started Aug 10 05:24:57 PM PDT 24
Finished Aug 10 05:24:58 PM PDT 24
Peak memory 200384 kb
Host smart-690c9ba2-8654-402a-b56c-b84036ef98af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660861339 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_smoke.660861339
Directory /workspace/42.rstmgr_smoke/latest

Test location /workspace/coverage/default/42.rstmgr_stress_all.2512518519
Short name T115
Test name
Test status
Simulation time 10090445939 ps
CPU time 37.24 seconds
Started Aug 10 05:25:19 PM PDT 24
Finished Aug 10 05:25:56 PM PDT 24
Peak memory 200688 kb
Host smart-390cf6a8-9fbe-4c8b-991b-6af959591baf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512518519 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_stress_all.2512518519
Directory /workspace/42.rstmgr_stress_all/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst.1543937950
Short name T381
Test name
Test status
Simulation time 126239696 ps
CPU time 1.58 seconds
Started Aug 10 05:25:03 PM PDT 24
Finished Aug 10 05:25:05 PM PDT 24
Peak memory 200344 kb
Host smart-9b5589d6-ab01-4ae7-9193-27f926f05f93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1543937950 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst.1543937950
Directory /workspace/42.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/42.rstmgr_sw_rst_reset_race.3313623118
Short name T128
Test name
Test status
Simulation time 163370482 ps
CPU time 1.11 seconds
Started Aug 10 05:25:18 PM PDT 24
Finished Aug 10 05:25:19 PM PDT 24
Peak memory 200364 kb
Host smart-2b892c47-9dfb-432d-a514-fe4c3c9caf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3313623118 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.rstmgr_sw_rst_reset_race.3313623118
Directory /workspace/42.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/43.rstmgr_alert_test.1515804484
Short name T448
Test name
Test status
Simulation time 70286973 ps
CPU time 0.8 seconds
Started Aug 10 05:25:19 PM PDT 24
Finished Aug 10 05:25:20 PM PDT 24
Peak memory 200084 kb
Host smart-ded63fde-c680-4edb-a943-1e6f883b4e59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1515804484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_alert_test.1515804484
Directory /workspace/43.rstmgr_alert_test/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_cnsty.2675459485
Short name T496
Test name
Test status
Simulation time 2359249859 ps
CPU time 9 seconds
Started Aug 10 05:25:26 PM PDT 24
Finished Aug 10 05:25:35 PM PDT 24
Peak memory 221820 kb
Host smart-a51f759c-a3e1-4979-bf8e-77c29070ab00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675459485 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_cnsty.2675459485
Directory /workspace/43.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/43.rstmgr_leaf_rst_shadow_attack.2529574749
Short name T192
Test name
Test status
Simulation time 243243003 ps
CPU time 1.17 seconds
Started Aug 10 05:25:08 PM PDT 24
Finished Aug 10 05:25:09 PM PDT 24
Peak memory 217540 kb
Host smart-87cb6e10-c3a3-4606-bffd-af1884bb9a79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529574749 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_leaf_rst_shadow_attack.2529574749
Directory /workspace/43.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/43.rstmgr_por_stretcher.342841861
Short name T170
Test name
Test status
Simulation time 119195284 ps
CPU time 0.82 seconds
Started Aug 10 05:25:16 PM PDT 24
Finished Aug 10 05:25:17 PM PDT 24
Peak memory 200156 kb
Host smart-297e8b68-0da1-4b47-b329-c17fc325d558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=342841861 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_por_stretcher.342841861
Directory /workspace/43.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/43.rstmgr_reset.1720122588
Short name T294
Test name
Test status
Simulation time 829160625 ps
CPU time 4.2 seconds
Started Aug 10 05:25:05 PM PDT 24
Finished Aug 10 05:25:09 PM PDT 24
Peak memory 200572 kb
Host smart-39146b16-0dc2-4672-bfca-eb48977c70b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1720122588 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_reset.1720122588
Directory /workspace/43.rstmgr_reset/latest

Test location /workspace/coverage/default/43.rstmgr_sec_cm_scan_intersig_mubi.639364484
Short name T145
Test name
Test status
Simulation time 151731453 ps
CPU time 1.08 seconds
Started Aug 10 05:25:07 PM PDT 24
Finished Aug 10 05:25:08 PM PDT 24
Peak memory 200436 kb
Host smart-a102519f-548b-4fbd-b7fb-06ba0fd8261d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639364484 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sec_cm_scan_intersig_mubi.639364484
Directory /workspace/43.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/43.rstmgr_smoke.2047640142
Short name T307
Test name
Test status
Simulation time 122326002 ps
CPU time 1.15 seconds
Started Aug 10 05:25:07 PM PDT 24
Finished Aug 10 05:25:09 PM PDT 24
Peak memory 200372 kb
Host smart-05248a30-8f53-4c83-bb3e-89edda717eea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2047640142 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_smoke.2047640142
Directory /workspace/43.rstmgr_smoke/latest

Test location /workspace/coverage/default/43.rstmgr_stress_all.1889017185
Short name T493
Test name
Test status
Simulation time 1011922090 ps
CPU time 4.73 seconds
Started Aug 10 05:25:19 PM PDT 24
Finished Aug 10 05:25:24 PM PDT 24
Peak memory 200576 kb
Host smart-d6bee2a4-e868-460d-b5c2-65ebc060005a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889017185 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_stress_all.1889017185
Directory /workspace/43.rstmgr_stress_all/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst.2524598665
Short name T41
Test name
Test status
Simulation time 438488756 ps
CPU time 2.35 seconds
Started Aug 10 05:25:14 PM PDT 24
Finished Aug 10 05:25:17 PM PDT 24
Peak memory 208444 kb
Host smart-d8b118bf-3828-44ed-b640-faca2fe39aa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2524598665 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst.2524598665
Directory /workspace/43.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/43.rstmgr_sw_rst_reset_race.3393778756
Short name T202
Test name
Test status
Simulation time 109574668 ps
CPU time 1 seconds
Started Aug 10 05:24:54 PM PDT 24
Finished Aug 10 05:24:55 PM PDT 24
Peak memory 200252 kb
Host smart-c026a2b9-8e55-49fa-af48-590b0fb64e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393778756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.rstmgr_sw_rst_reset_race.3393778756
Directory /workspace/43.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/44.rstmgr_alert_test.2055299306
Short name T501
Test name
Test status
Simulation time 66532527 ps
CPU time 0.79 seconds
Started Aug 10 05:25:03 PM PDT 24
Finished Aug 10 05:25:09 PM PDT 24
Peak memory 200176 kb
Host smart-9ce448c2-3573-4ec1-a481-05691857255f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055299306 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_alert_test.2055299306
Directory /workspace/44.rstmgr_alert_test/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_cnsty.1985762900
Short name T24
Test name
Test status
Simulation time 1878508947 ps
CPU time 7.12 seconds
Started Aug 10 05:25:04 PM PDT 24
Finished Aug 10 05:25:12 PM PDT 24
Peak memory 217712 kb
Host smart-2d6e23b2-c499-4c02-97d7-7fa49ffe353e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985762900 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_cnsty.1985762900
Directory /workspace/44.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/44.rstmgr_leaf_rst_shadow_attack.4098645212
Short name T189
Test name
Test status
Simulation time 244734978 ps
CPU time 1.19 seconds
Started Aug 10 05:25:08 PM PDT 24
Finished Aug 10 05:25:09 PM PDT 24
Peak memory 217508 kb
Host smart-155df842-1a0a-4b40-9283-5a35485a8c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4098645212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_leaf_rst_shadow_attack.4098645212
Directory /workspace/44.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/44.rstmgr_por_stretcher.2375731196
Short name T515
Test name
Test status
Simulation time 94703525 ps
CPU time 0.76 seconds
Started Aug 10 05:25:07 PM PDT 24
Finished Aug 10 05:25:08 PM PDT 24
Peak memory 200116 kb
Host smart-82a6868e-e725-4e4b-b7b0-951b669f17f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375731196 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_por_stretcher.2375731196
Directory /workspace/44.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/44.rstmgr_sec_cm_scan_intersig_mubi.793326517
Short name T226
Test name
Test status
Simulation time 142783067 ps
CPU time 1.15 seconds
Started Aug 10 05:25:07 PM PDT 24
Finished Aug 10 05:25:08 PM PDT 24
Peak memory 200388 kb
Host smart-ed810d82-00ba-4a7f-a3c4-134799d5267c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793326517 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sec_cm_scan_intersig_mubi.793326517
Directory /workspace/44.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/44.rstmgr_smoke.2462466096
Short name T321
Test name
Test status
Simulation time 227029207 ps
CPU time 1.44 seconds
Started Aug 10 05:25:08 PM PDT 24
Finished Aug 10 05:25:09 PM PDT 24
Peak memory 200508 kb
Host smart-f867b984-9ba4-46bb-89ea-c772e9156769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462466096 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_smoke.2462466096
Directory /workspace/44.rstmgr_smoke/latest

Test location /workspace/coverage/default/44.rstmgr_stress_all.3908723099
Short name T213
Test name
Test status
Simulation time 1765845590 ps
CPU time 6.13 seconds
Started Aug 10 05:25:02 PM PDT 24
Finished Aug 10 05:25:08 PM PDT 24
Peak memory 208800 kb
Host smart-465077af-11dd-4368-8998-ff2385b073b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3908723099 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_stress_all.3908723099
Directory /workspace/44.rstmgr_stress_all/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst.1923930579
Short name T68
Test name
Test status
Simulation time 360904448 ps
CPU time 2.46 seconds
Started Aug 10 05:25:20 PM PDT 24
Finished Aug 10 05:25:23 PM PDT 24
Peak memory 200308 kb
Host smart-04882b66-f532-401d-86c7-14f513d19c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923930579 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst.1923930579
Directory /workspace/44.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/44.rstmgr_sw_rst_reset_race.922918454
Short name T253
Test name
Test status
Simulation time 125116318 ps
CPU time 0.93 seconds
Started Aug 10 05:25:09 PM PDT 24
Finished Aug 10 05:25:10 PM PDT 24
Peak memory 200336 kb
Host smart-97c99bde-8a96-4277-9bb6-21cfeb890e18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=922918454 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.rstmgr_sw_rst_reset_race.922918454
Directory /workspace/44.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/45.rstmgr_alert_test.846903029
Short name T403
Test name
Test status
Simulation time 67912049 ps
CPU time 0.79 seconds
Started Aug 10 05:25:07 PM PDT 24
Finished Aug 10 05:25:08 PM PDT 24
Peak memory 200160 kb
Host smart-5c4353c8-2e4e-4b4e-8692-765a9d268989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846903029 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_alert_test.846903029
Directory /workspace/45.rstmgr_alert_test/latest

Test location /workspace/coverage/default/45.rstmgr_leaf_rst_shadow_attack.189383934
Short name T368
Test name
Test status
Simulation time 244199105 ps
CPU time 1.09 seconds
Started Aug 10 05:25:38 PM PDT 24
Finished Aug 10 05:25:40 PM PDT 24
Peak memory 217492 kb
Host smart-d5a4bac9-a917-4eb4-beff-451825f37579
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=189383934 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_leaf_rst_shadow_attack.189383934
Directory /workspace/45.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/45.rstmgr_por_stretcher.2815735258
Short name T426
Test name
Test status
Simulation time 159075516 ps
CPU time 0.84 seconds
Started Aug 10 05:25:18 PM PDT 24
Finished Aug 10 05:25:19 PM PDT 24
Peak memory 200148 kb
Host smart-3b23733e-f032-4b34-9547-78768c35fabe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815735258 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_por_stretcher.2815735258
Directory /workspace/45.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/45.rstmgr_reset.1172833326
Short name T221
Test name
Test status
Simulation time 1615784521 ps
CPU time 6.24 seconds
Started Aug 10 05:25:22 PM PDT 24
Finished Aug 10 05:25:28 PM PDT 24
Peak memory 200552 kb
Host smart-9b3b1c1c-0297-4c4e-98ee-3666ed50ed20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172833326 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_reset.1172833326
Directory /workspace/45.rstmgr_reset/latest

Test location /workspace/coverage/default/45.rstmgr_sec_cm_scan_intersig_mubi.939055943
Short name T144
Test name
Test status
Simulation time 187106360 ps
CPU time 1.23 seconds
Started Aug 10 05:25:17 PM PDT 24
Finished Aug 10 05:25:18 PM PDT 24
Peak memory 200336 kb
Host smart-8837cd08-c68c-4077-874a-3e0ff07c0c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939055943 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sec_cm_scan_intersig_mubi.939055943
Directory /workspace/45.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/45.rstmgr_smoke.1280721369
Short name T499
Test name
Test status
Simulation time 236115696 ps
CPU time 1.57 seconds
Started Aug 10 05:25:07 PM PDT 24
Finished Aug 10 05:25:09 PM PDT 24
Peak memory 200376 kb
Host smart-0c136798-e180-43ea-be76-6d5f8a8d2c3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280721369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_smoke.1280721369
Directory /workspace/45.rstmgr_smoke/latest

Test location /workspace/coverage/default/45.rstmgr_stress_all.3121169991
Short name T401
Test name
Test status
Simulation time 937702546 ps
CPU time 4.45 seconds
Started Aug 10 05:25:23 PM PDT 24
Finished Aug 10 05:25:27 PM PDT 24
Peak memory 200556 kb
Host smart-ac092606-5655-4035-8cef-4d8277b0597e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3121169991 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_stress_all.3121169991
Directory /workspace/45.rstmgr_stress_all/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst.1846232124
Short name T129
Test name
Test status
Simulation time 300655288 ps
CPU time 2.07 seconds
Started Aug 10 05:25:16 PM PDT 24
Finished Aug 10 05:25:18 PM PDT 24
Peak memory 208468 kb
Host smart-31c9dae9-78f8-4593-bb51-b79ad321af09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846232124 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst.1846232124
Directory /workspace/45.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/45.rstmgr_sw_rst_reset_race.2832921682
Short name T175
Test name
Test status
Simulation time 132944991 ps
CPU time 1.01 seconds
Started Aug 10 05:25:17 PM PDT 24
Finished Aug 10 05:25:18 PM PDT 24
Peak memory 200340 kb
Host smart-8621214a-0ae6-415a-9b2a-9446b6133637
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2832921682 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.rstmgr_sw_rst_reset_race.2832921682
Directory /workspace/45.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/46.rstmgr_alert_test.1889597113
Short name T237
Test name
Test status
Simulation time 86403639 ps
CPU time 0.9 seconds
Started Aug 10 05:25:24 PM PDT 24
Finished Aug 10 05:25:25 PM PDT 24
Peak memory 200172 kb
Host smart-301a3e0d-5edc-4807-9ec8-0dea037467af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889597113 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_alert_test.1889597113
Directory /workspace/46.rstmgr_alert_test/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_cnsty.1886847654
Short name T239
Test name
Test status
Simulation time 1226245510 ps
CPU time 5.77 seconds
Started Aug 10 05:25:20 PM PDT 24
Finished Aug 10 05:25:26 PM PDT 24
Peak memory 221728 kb
Host smart-4a597e07-5879-48cb-95f3-2e962d8c0e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886847654 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_cnsty.1886847654
Directory /workspace/46.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/46.rstmgr_leaf_rst_shadow_attack.2174848463
Short name T271
Test name
Test status
Simulation time 246205273 ps
CPU time 1.05 seconds
Started Aug 10 05:25:25 PM PDT 24
Finished Aug 10 05:25:26 PM PDT 24
Peak memory 217516 kb
Host smart-04a8f699-48da-42cb-81b1-4162ae355b84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174848463 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_leaf_rst_shadow_attack.2174848463
Directory /workspace/46.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/46.rstmgr_por_stretcher.4222131549
Short name T412
Test name
Test status
Simulation time 106406934 ps
CPU time 0.8 seconds
Started Aug 10 05:25:23 PM PDT 24
Finished Aug 10 05:25:24 PM PDT 24
Peak memory 200180 kb
Host smart-c67e4156-4a4f-4b49-ba02-01373a5aa007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222131549 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_por_stretcher.4222131549
Directory /workspace/46.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/46.rstmgr_reset.46619365
Short name T303
Test name
Test status
Simulation time 819863200 ps
CPU time 4.33 seconds
Started Aug 10 05:25:30 PM PDT 24
Finished Aug 10 05:25:35 PM PDT 24
Peak memory 200532 kb
Host smart-1fe95d3c-3f6f-42a1-be7f-07e87ac4e438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46619365 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_reset.46619365
Directory /workspace/46.rstmgr_reset/latest

Test location /workspace/coverage/default/46.rstmgr_sec_cm_scan_intersig_mubi.404246695
Short name T211
Test name
Test status
Simulation time 150496879 ps
CPU time 1.11 seconds
Started Aug 10 05:25:17 PM PDT 24
Finished Aug 10 05:25:18 PM PDT 24
Peak memory 200364 kb
Host smart-88881bf9-afcd-4c3a-b280-cd524e37439b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404246695 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sec_cm_scan_intersig_mubi.404246695
Directory /workspace/46.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/46.rstmgr_smoke.2982832325
Short name T435
Test name
Test status
Simulation time 186581045 ps
CPU time 1.33 seconds
Started Aug 10 05:25:25 PM PDT 24
Finished Aug 10 05:25:27 PM PDT 24
Peak memory 200300 kb
Host smart-24d5a643-39e6-4ec9-864e-fac68064f10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982832325 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_smoke.2982832325
Directory /workspace/46.rstmgr_smoke/latest

Test location /workspace/coverage/default/46.rstmgr_stress_all.4262013807
Short name T396
Test name
Test status
Simulation time 8029212465 ps
CPU time 27.44 seconds
Started Aug 10 05:25:26 PM PDT 24
Finished Aug 10 05:25:54 PM PDT 24
Peak memory 200628 kb
Host smart-e5f8b7e8-6449-4973-b726-a304a738d033
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4262013807 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_stress_all.4262013807
Directory /workspace/46.rstmgr_stress_all/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst.2605042817
Short name T177
Test name
Test status
Simulation time 388277428 ps
CPU time 2.53 seconds
Started Aug 10 05:25:23 PM PDT 24
Finished Aug 10 05:25:26 PM PDT 24
Peak memory 200316 kb
Host smart-4da3d7c3-665a-4495-9a9a-1d3a90c290e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605042817 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst.2605042817
Directory /workspace/46.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/46.rstmgr_sw_rst_reset_race.854199039
Short name T494
Test name
Test status
Simulation time 57234593 ps
CPU time 0.75 seconds
Started Aug 10 05:25:22 PM PDT 24
Finished Aug 10 05:25:23 PM PDT 24
Peak memory 200356 kb
Host smart-346fd214-582b-4886-93d8-76967ec79f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=854199039 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.rstmgr_sw_rst_reset_race.854199039
Directory /workspace/46.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/47.rstmgr_alert_test.4006007
Short name T361
Test name
Test status
Simulation time 60493186 ps
CPU time 0.74 seconds
Started Aug 10 05:25:25 PM PDT 24
Finished Aug 10 05:25:26 PM PDT 24
Peak memory 199972 kb
Host smart-1a712cc2-0f80-4592-b2b6-e1218d295264
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4006007 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_alert_test.4006007
Directory /workspace/47.rstmgr_alert_test/latest

Test location /workspace/coverage/default/47.rstmgr_leaf_rst_shadow_attack.3558979264
Short name T276
Test name
Test status
Simulation time 244619084 ps
CPU time 1.07 seconds
Started Aug 10 05:25:28 PM PDT 24
Finished Aug 10 05:25:29 PM PDT 24
Peak memory 217540 kb
Host smart-0e88e699-b875-4b4a-bd69-68e68af795a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558979264 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_leaf_rst_shadow_attack.3558979264
Directory /workspace/47.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/47.rstmgr_por_stretcher.2363312827
Short name T453
Test name
Test status
Simulation time 104999436 ps
CPU time 0.76 seconds
Started Aug 10 05:25:22 PM PDT 24
Finished Aug 10 05:25:23 PM PDT 24
Peak memory 200124 kb
Host smart-d6733537-473d-4924-a12e-848d8bc562c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363312827 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_por_stretcher.2363312827
Directory /workspace/47.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/47.rstmgr_reset.1316209639
Short name T345
Test name
Test status
Simulation time 918707713 ps
CPU time 4.43 seconds
Started Aug 10 05:25:22 PM PDT 24
Finished Aug 10 05:25:27 PM PDT 24
Peak memory 200364 kb
Host smart-03fa8740-923e-4c14-b451-a1070b7f5068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316209639 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_reset.1316209639
Directory /workspace/47.rstmgr_reset/latest

Test location /workspace/coverage/default/47.rstmgr_sec_cm_scan_intersig_mubi.1676276408
Short name T305
Test name
Test status
Simulation time 180564947 ps
CPU time 1.18 seconds
Started Aug 10 05:25:16 PM PDT 24
Finished Aug 10 05:25:17 PM PDT 24
Peak memory 200352 kb
Host smart-9cd8317e-fd36-46c7-981b-3a34d26183ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676276408 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sec_cm_scan_intersig_mubi.1676276408
Directory /workspace/47.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/47.rstmgr_smoke.113641017
Short name T243
Test name
Test status
Simulation time 195739160 ps
CPU time 1.34 seconds
Started Aug 10 05:25:05 PM PDT 24
Finished Aug 10 05:25:07 PM PDT 24
Peak memory 200672 kb
Host smart-3e8c0b12-8d00-41d1-9ed0-6a6798f4cb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113641017 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_smoke.113641017
Directory /workspace/47.rstmgr_smoke/latest

Test location /workspace/coverage/default/47.rstmgr_stress_all.1138055854
Short name T296
Test name
Test status
Simulation time 2865304163 ps
CPU time 10.92 seconds
Started Aug 10 05:25:28 PM PDT 24
Finished Aug 10 05:25:39 PM PDT 24
Peak memory 200628 kb
Host smart-88109cef-cde0-45ad-9839-684fb6a22681
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138055854 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_stress_all.1138055854
Directory /workspace/47.rstmgr_stress_all/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst.470813928
Short name T160
Test name
Test status
Simulation time 148452332 ps
CPU time 1.94 seconds
Started Aug 10 05:25:24 PM PDT 24
Finished Aug 10 05:25:26 PM PDT 24
Peak memory 200316 kb
Host smart-3d2f3525-b4c2-43e1-952c-84ef556c7adc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=470813928 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst.470813928
Directory /workspace/47.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/47.rstmgr_sw_rst_reset_race.3830188284
Short name T153
Test name
Test status
Simulation time 126151721 ps
CPU time 1.02 seconds
Started Aug 10 05:25:31 PM PDT 24
Finished Aug 10 05:25:32 PM PDT 24
Peak memory 200336 kb
Host smart-f2a2a824-85c2-483d-a1d2-09c89628d582
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830188284 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.rstmgr_sw_rst_reset_race.3830188284
Directory /workspace/47.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/48.rstmgr_alert_test.2070545224
Short name T460
Test name
Test status
Simulation time 71319195 ps
CPU time 0.79 seconds
Started Aug 10 05:25:12 PM PDT 24
Finished Aug 10 05:25:13 PM PDT 24
Peak memory 200036 kb
Host smart-5d6d4e29-d0e4-42d2-bb72-d904de243dfa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070545224 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_alert_test.2070545224
Directory /workspace/48.rstmgr_alert_test/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_cnsty.2631210323
Short name T28
Test name
Test status
Simulation time 1224663020 ps
CPU time 5.88 seconds
Started Aug 10 05:25:23 PM PDT 24
Finished Aug 10 05:25:29 PM PDT 24
Peak memory 217760 kb
Host smart-c698c67b-6f5b-4e7b-9673-27b175b9b23a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631210323 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_cnsty.2631210323
Directory /workspace/48.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/48.rstmgr_leaf_rst_shadow_attack.1616661242
Short name T492
Test name
Test status
Simulation time 243440630 ps
CPU time 1.09 seconds
Started Aug 10 05:25:24 PM PDT 24
Finished Aug 10 05:25:25 PM PDT 24
Peak memory 217440 kb
Host smart-5de69f65-55d3-493b-aeac-87f293c17334
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616661242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_leaf_rst_shadow_attack.1616661242
Directory /workspace/48.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/48.rstmgr_por_stretcher.1710963009
Short name T340
Test name
Test status
Simulation time 105148359 ps
CPU time 0.79 seconds
Started Aug 10 05:25:11 PM PDT 24
Finished Aug 10 05:25:12 PM PDT 24
Peak memory 200196 kb
Host smart-5fdc61ce-b2ce-4411-aff5-e1896b494d8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710963009 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_por_stretcher.1710963009
Directory /workspace/48.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/48.rstmgr_reset.1297850170
Short name T436
Test name
Test status
Simulation time 1606546109 ps
CPU time 5.97 seconds
Started Aug 10 05:25:19 PM PDT 24
Finished Aug 10 05:25:25 PM PDT 24
Peak memory 200740 kb
Host smart-29d8a152-e75e-4769-93d0-ce5ad0f106e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297850170 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_reset.1297850170
Directory /workspace/48.rstmgr_reset/latest

Test location /workspace/coverage/default/48.rstmgr_sec_cm_scan_intersig_mubi.2771840800
Short name T228
Test name
Test status
Simulation time 170456721 ps
CPU time 1.2 seconds
Started Aug 10 05:25:25 PM PDT 24
Finished Aug 10 05:25:26 PM PDT 24
Peak memory 200380 kb
Host smart-da97ef36-7f55-4940-a929-1bf70cd7dddd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771840800 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sec_cm_scan_intersig_mubi.2771840800
Directory /workspace/48.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/48.rstmgr_smoke.2152687156
Short name T351
Test name
Test status
Simulation time 191776452 ps
CPU time 1.35 seconds
Started Aug 10 05:25:22 PM PDT 24
Finished Aug 10 05:25:24 PM PDT 24
Peak memory 200484 kb
Host smart-e400bc09-b88c-4f6b-af4f-8dd01744f412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152687156 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_smoke.2152687156
Directory /workspace/48.rstmgr_smoke/latest

Test location /workspace/coverage/default/48.rstmgr_stress_all.550738567
Short name T310
Test name
Test status
Simulation time 5958866462 ps
CPU time 21.79 seconds
Started Aug 10 05:25:25 PM PDT 24
Finished Aug 10 05:25:47 PM PDT 24
Peak memory 200640 kb
Host smart-6307f4b3-2045-4da7-a6e8-0c500015ab03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550738567 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_stress_all.550738567
Directory /workspace/48.rstmgr_stress_all/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst.1112587993
Short name T265
Test name
Test status
Simulation time 123866965 ps
CPU time 1.5 seconds
Started Aug 10 05:25:10 PM PDT 24
Finished Aug 10 05:25:11 PM PDT 24
Peak memory 200276 kb
Host smart-9478ba78-5f36-4459-8202-cab9e7912e0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112587993 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst.1112587993
Directory /workspace/48.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/48.rstmgr_sw_rst_reset_race.2574384097
Short name T316
Test name
Test status
Simulation time 243409711 ps
CPU time 1.42 seconds
Started Aug 10 05:25:24 PM PDT 24
Finished Aug 10 05:25:25 PM PDT 24
Peak memory 200364 kb
Host smart-994c9253-2550-4419-95dc-6b265e1dbf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574384097 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.rstmgr_sw_rst_reset_race.2574384097
Directory /workspace/48.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/49.rstmgr_alert_test.3774768338
Short name T252
Test name
Test status
Simulation time 60570759 ps
CPU time 0.71 seconds
Started Aug 10 05:25:29 PM PDT 24
Finished Aug 10 05:25:30 PM PDT 24
Peak memory 200164 kb
Host smart-740d8667-b965-4d34-bc43-f7a615812428
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774768338 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_alert_test.3774768338
Directory /workspace/49.rstmgr_alert_test/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_cnsty.2264892985
Short name T497
Test name
Test status
Simulation time 1235835343 ps
CPU time 6.19 seconds
Started Aug 10 05:25:32 PM PDT 24
Finished Aug 10 05:25:38 PM PDT 24
Peak memory 217756 kb
Host smart-4613c1a2-4bbe-443c-8750-4a72affb00a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2264892985 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_cnsty.2264892985
Directory /workspace/49.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/49.rstmgr_leaf_rst_shadow_attack.3160147896
Short name T539
Test name
Test status
Simulation time 243701065 ps
CPU time 1.12 seconds
Started Aug 10 05:25:28 PM PDT 24
Finished Aug 10 05:25:29 PM PDT 24
Peak memory 217476 kb
Host smart-27499d6c-eef6-4548-97e5-e94c48824b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160147896 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_leaf_rst_shadow_attack.3160147896
Directory /workspace/49.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/49.rstmgr_por_stretcher.2300682164
Short name T431
Test name
Test status
Simulation time 152574833 ps
CPU time 0.9 seconds
Started Aug 10 05:25:23 PM PDT 24
Finished Aug 10 05:25:24 PM PDT 24
Peak memory 200160 kb
Host smart-65a24730-4ffb-41b4-981f-e4055d1101b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300682164 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_por_stretcher.2300682164
Directory /workspace/49.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/49.rstmgr_reset.1447315347
Short name T397
Test name
Test status
Simulation time 698070271 ps
CPU time 3.7 seconds
Started Aug 10 05:25:26 PM PDT 24
Finished Aug 10 05:25:29 PM PDT 24
Peak memory 200568 kb
Host smart-53ae8283-3df2-4d65-84ac-302d08b65296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447315347 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_reset.1447315347
Directory /workspace/49.rstmgr_reset/latest

Test location /workspace/coverage/default/49.rstmgr_sec_cm_scan_intersig_mubi.210157927
Short name T118
Test name
Test status
Simulation time 172193331 ps
CPU time 1.25 seconds
Started Aug 10 05:25:26 PM PDT 24
Finished Aug 10 05:25:28 PM PDT 24
Peak memory 200156 kb
Host smart-028daded-616f-40f5-94e2-ffa763fcad98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=210157927 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sec_cm_scan_intersig_mubi.210157927
Directory /workspace/49.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/49.rstmgr_smoke.1140701051
Short name T266
Test name
Test status
Simulation time 194070597 ps
CPU time 1.29 seconds
Started Aug 10 05:25:23 PM PDT 24
Finished Aug 10 05:25:25 PM PDT 24
Peak memory 200492 kb
Host smart-3534873e-2059-4699-9153-cc41b9dbf0eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1140701051 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_smoke.1140701051
Directory /workspace/49.rstmgr_smoke/latest

Test location /workspace/coverage/default/49.rstmgr_stress_all.3276494922
Short name T479
Test name
Test status
Simulation time 3431723696 ps
CPU time 15.31 seconds
Started Aug 10 05:25:38 PM PDT 24
Finished Aug 10 05:25:54 PM PDT 24
Peak memory 208860 kb
Host smart-7dafcf08-663c-4e75-8e41-e964b6cdfd46
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276494922 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_stress_all.3276494922
Directory /workspace/49.rstmgr_stress_all/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst.4231758024
Short name T429
Test name
Test status
Simulation time 143695244 ps
CPU time 1.63 seconds
Started Aug 10 05:25:23 PM PDT 24
Finished Aug 10 05:25:25 PM PDT 24
Peak memory 200172 kb
Host smart-af6bc539-382d-4aef-b666-578d2f4f35ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4231758024 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst.4231758024
Directory /workspace/49.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/49.rstmgr_sw_rst_reset_race.2281930849
Short name T172
Test name
Test status
Simulation time 266442184 ps
CPU time 1.57 seconds
Started Aug 10 05:25:24 PM PDT 24
Finished Aug 10 05:25:26 PM PDT 24
Peak memory 200332 kb
Host smart-f1aa44ef-388d-4b65-b307-575bfed92747
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281930849 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.rstmgr_sw_rst_reset_race.2281930849
Directory /workspace/49.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/5.rstmgr_alert_test.4113672908
Short name T376
Test name
Test status
Simulation time 98411957 ps
CPU time 0.8 seconds
Started Aug 10 05:24:31 PM PDT 24
Finished Aug 10 05:24:32 PM PDT 24
Peak memory 200116 kb
Host smart-f55c5a20-123b-4f71-a5c5-86042bbc5da1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113672908 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_alert_test.4113672908
Directory /workspace/5.rstmgr_alert_test/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_cnsty.3441572872
Short name T408
Test name
Test status
Simulation time 2206580461 ps
CPU time 7.25 seconds
Started Aug 10 05:24:35 PM PDT 24
Finished Aug 10 05:24:43 PM PDT 24
Peak memory 216852 kb
Host smart-6e365e6d-8a4a-47f2-a15d-9d802a696f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441572872 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_cnsty.3441572872
Directory /workspace/5.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/5.rstmgr_leaf_rst_shadow_attack.483785427
Short name T491
Test name
Test status
Simulation time 244249143 ps
CPU time 1.13 seconds
Started Aug 10 05:24:08 PM PDT 24
Finished Aug 10 05:24:09 PM PDT 24
Peak memory 217528 kb
Host smart-4ff269d0-6914-4028-b8a4-f7b0855eff97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483785427 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_leaf_rst_shadow_attack.483785427
Directory /workspace/5.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/5.rstmgr_por_stretcher.1715147369
Short name T162
Test name
Test status
Simulation time 168315585 ps
CPU time 0.92 seconds
Started Aug 10 05:24:35 PM PDT 24
Finished Aug 10 05:24:36 PM PDT 24
Peak memory 200144 kb
Host smart-82645328-1b12-4cce-a7c4-22985772cf86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715147369 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_por_stretcher.1715147369
Directory /workspace/5.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/5.rstmgr_reset.1477909080
Short name T60
Test name
Test status
Simulation time 713367264 ps
CPU time 3.97 seconds
Started Aug 10 05:24:30 PM PDT 24
Finished Aug 10 05:24:34 PM PDT 24
Peak memory 200512 kb
Host smart-da494745-151e-4006-922b-0f065481056e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477909080 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_reset.1477909080
Directory /workspace/5.rstmgr_reset/latest

Test location /workspace/coverage/default/5.rstmgr_sec_cm_scan_intersig_mubi.295405969
Short name T525
Test name
Test status
Simulation time 112782366 ps
CPU time 1.1 seconds
Started Aug 10 05:24:17 PM PDT 24
Finished Aug 10 05:24:18 PM PDT 24
Peak memory 200336 kb
Host smart-9562417b-1e28-4583-b661-6427edf236ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295405969 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sec_cm_scan_intersig_mubi.295405969
Directory /workspace/5.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/5.rstmgr_smoke.330875322
Short name T148
Test name
Test status
Simulation time 115455961 ps
CPU time 1.21 seconds
Started Aug 10 05:24:20 PM PDT 24
Finished Aug 10 05:24:21 PM PDT 24
Peak memory 200500 kb
Host smart-01d89c8e-34e8-494a-b208-5e56b689b87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330875322 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_smoke.330875322
Directory /workspace/5.rstmgr_smoke/latest

Test location /workspace/coverage/default/5.rstmgr_stress_all.4148563168
Short name T466
Test name
Test status
Simulation time 4353107719 ps
CPU time 20.71 seconds
Started Aug 10 05:24:26 PM PDT 24
Finished Aug 10 05:24:46 PM PDT 24
Peak memory 208812 kb
Host smart-0ea74a3f-9a27-438b-8eea-f5c62d73c887
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148563168 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_stress_all.4148563168
Directory /workspace/5.rstmgr_stress_all/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst.3180825513
Short name T152
Test name
Test status
Simulation time 357788102 ps
CPU time 2.15 seconds
Started Aug 10 05:24:23 PM PDT 24
Finished Aug 10 05:24:25 PM PDT 24
Peak memory 200304 kb
Host smart-4ac07262-beca-4f8d-902f-020179ed8439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180825513 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst.3180825513
Directory /workspace/5.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/5.rstmgr_sw_rst_reset_race.4052566548
Short name T370
Test name
Test status
Simulation time 229651734 ps
CPU time 1.4 seconds
Started Aug 10 05:24:05 PM PDT 24
Finished Aug 10 05:24:07 PM PDT 24
Peak memory 200360 kb
Host smart-d1c26849-089a-4b49-844b-287d57a076b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052566548 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.rstmgr_sw_rst_reset_race.4052566548
Directory /workspace/5.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/6.rstmgr_alert_test.819417839
Short name T267
Test name
Test status
Simulation time 62286492 ps
CPU time 0.74 seconds
Started Aug 10 05:24:23 PM PDT 24
Finished Aug 10 05:24:24 PM PDT 24
Peak memory 200180 kb
Host smart-651a4e23-4701-4a81-af3f-1acc2f966f38
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819417839 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_alert_test.819417839
Directory /workspace/6.rstmgr_alert_test/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_cnsty.2929674712
Short name T40
Test name
Test status
Simulation time 1890082314 ps
CPU time 7.3 seconds
Started Aug 10 05:24:26 PM PDT 24
Finished Aug 10 05:24:33 PM PDT 24
Peak memory 217352 kb
Host smart-a759ef93-0fdd-40e3-8bf7-a6eb95dda9b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929674712 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_cnsty.2929674712
Directory /workspace/6.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/6.rstmgr_leaf_rst_shadow_attack.3850453592
Short name T259
Test name
Test status
Simulation time 244112047 ps
CPU time 1.07 seconds
Started Aug 10 05:24:24 PM PDT 24
Finished Aug 10 05:24:26 PM PDT 24
Peak memory 217328 kb
Host smart-cb7ffc40-2dab-4492-bd8c-fd9e029f305e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850453592 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_leaf_rst_shadow_attack.3850453592
Directory /workspace/6.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/6.rstmgr_por_stretcher.3314659815
Short name T529
Test name
Test status
Simulation time 97118504 ps
CPU time 0.83 seconds
Started Aug 10 05:24:30 PM PDT 24
Finished Aug 10 05:24:36 PM PDT 24
Peak memory 200052 kb
Host smart-32a750e5-f362-4808-94a6-747bb78238d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314659815 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_por_stretcher.3314659815
Directory /workspace/6.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/6.rstmgr_reset.1071895640
Short name T502
Test name
Test status
Simulation time 1947592378 ps
CPU time 7.15 seconds
Started Aug 10 05:24:13 PM PDT 24
Finished Aug 10 05:24:20 PM PDT 24
Peak memory 200616 kb
Host smart-fcaf318c-bb9e-4a38-bc45-e2a10864d610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071895640 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_reset.1071895640
Directory /workspace/6.rstmgr_reset/latest

Test location /workspace/coverage/default/6.rstmgr_sec_cm_scan_intersig_mubi.985115348
Short name T350
Test name
Test status
Simulation time 154620737 ps
CPU time 1.15 seconds
Started Aug 10 05:24:29 PM PDT 24
Finished Aug 10 05:24:30 PM PDT 24
Peak memory 200384 kb
Host smart-88383c9b-6261-4cbe-a3ab-0c85c57c8edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985115348 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sec_cm_scan_intersig_mubi.985115348
Directory /workspace/6.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/6.rstmgr_smoke.3553802756
Short name T196
Test name
Test status
Simulation time 192442111 ps
CPU time 1.47 seconds
Started Aug 10 05:24:16 PM PDT 24
Finished Aug 10 05:24:17 PM PDT 24
Peak memory 200428 kb
Host smart-d5ba3337-8116-4524-a675-cfa7a330d6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553802756 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_smoke.3553802756
Directory /workspace/6.rstmgr_smoke/latest

Test location /workspace/coverage/default/6.rstmgr_stress_all.2315198622
Short name T204
Test name
Test status
Simulation time 4209270701 ps
CPU time 18.82 seconds
Started Aug 10 05:24:13 PM PDT 24
Finished Aug 10 05:24:32 PM PDT 24
Peak memory 208724 kb
Host smart-cdf4519d-9a84-4859-871f-89de0eb5928a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315198622 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_stress_all.2315198622
Directory /workspace/6.rstmgr_stress_all/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst.4019556866
Short name T390
Test name
Test status
Simulation time 441373897 ps
CPU time 2.46 seconds
Started Aug 10 05:24:22 PM PDT 24
Finished Aug 10 05:24:24 PM PDT 24
Peak memory 200284 kb
Host smart-f071ac87-cbff-445a-8f47-5da5d4a65837
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019556866 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst.4019556866
Directory /workspace/6.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/6.rstmgr_sw_rst_reset_race.4066150242
Short name T517
Test name
Test status
Simulation time 154161345 ps
CPU time 1.26 seconds
Started Aug 10 05:24:24 PM PDT 24
Finished Aug 10 05:24:25 PM PDT 24
Peak memory 200292 kb
Host smart-44d2ee04-7db8-45f5-ab0e-59a5e4cfac63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066150242 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.rstmgr_sw_rst_reset_race.4066150242
Directory /workspace/6.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/7.rstmgr_alert_test.947960212
Short name T418
Test name
Test status
Simulation time 70328865 ps
CPU time 0.8 seconds
Started Aug 10 05:24:27 PM PDT 24
Finished Aug 10 05:24:28 PM PDT 24
Peak memory 200048 kb
Host smart-82175339-a03d-4f7f-9859-1edf17bfd3e4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947960212 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_alert_test.947960212
Directory /workspace/7.rstmgr_alert_test/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_cnsty.352822498
Short name T341
Test name
Test status
Simulation time 1886506220 ps
CPU time 7.21 seconds
Started Aug 10 05:24:31 PM PDT 24
Finished Aug 10 05:24:39 PM PDT 24
Peak memory 217616 kb
Host smart-0a717ab6-975b-4510-b73a-99f294d28032
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352822498 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_cnsty.352822498
Directory /workspace/7.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/7.rstmgr_leaf_rst_shadow_attack.517622609
Short name T270
Test name
Test status
Simulation time 244860310 ps
CPU time 1.08 seconds
Started Aug 10 05:24:25 PM PDT 24
Finished Aug 10 05:24:26 PM PDT 24
Peak memory 217500 kb
Host smart-63afd98c-d794-452b-aace-412298f72e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517622609 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_leaf_rst_shadow_attack.517622609
Directory /workspace/7.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/7.rstmgr_por_stretcher.3884583305
Short name T17
Test name
Test status
Simulation time 114899383 ps
CPU time 0.8 seconds
Started Aug 10 05:24:08 PM PDT 24
Finished Aug 10 05:24:09 PM PDT 24
Peak memory 200164 kb
Host smart-07c9509c-8fb4-44d4-b284-480a18b65d41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884583305 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_por_stretcher.3884583305
Directory /workspace/7.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/7.rstmgr_reset.304900137
Short name T88
Test name
Test status
Simulation time 1630418065 ps
CPU time 6.88 seconds
Started Aug 10 05:24:20 PM PDT 24
Finished Aug 10 05:24:27 PM PDT 24
Peak memory 200560 kb
Host smart-c9db899c-52e6-4e91-beb0-02f65cdad781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304900137 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_reset.304900137
Directory /workspace/7.rstmgr_reset/latest

Test location /workspace/coverage/default/7.rstmgr_sec_cm_scan_intersig_mubi.240086431
Short name T139
Test name
Test status
Simulation time 151829587 ps
CPU time 1.18 seconds
Started Aug 10 05:24:22 PM PDT 24
Finished Aug 10 05:24:24 PM PDT 24
Peak memory 200384 kb
Host smart-99b900ef-9faa-4f92-98fb-386094a709e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240086431 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sec_cm_scan_intersig_mubi.240086431
Directory /workspace/7.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/7.rstmgr_smoke.3836984772
Short name T320
Test name
Test status
Simulation time 230612999 ps
CPU time 1.48 seconds
Started Aug 10 05:24:27 PM PDT 24
Finished Aug 10 05:24:29 PM PDT 24
Peak memory 200332 kb
Host smart-5840e68c-7cc9-4d71-8155-925a7ea6f183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3836984772 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_smoke.3836984772
Directory /workspace/7.rstmgr_smoke/latest

Test location /workspace/coverage/default/7.rstmgr_stress_all.3247510497
Short name T373
Test name
Test status
Simulation time 2045716256 ps
CPU time 10.02 seconds
Started Aug 10 05:24:24 PM PDT 24
Finished Aug 10 05:24:34 PM PDT 24
Peak memory 208820 kb
Host smart-01f8ba81-4b6c-42a2-b6b6-20ca9bbb7022
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247510497 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_stress_all.3247510497
Directory /workspace/7.rstmgr_stress_all/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst.891726603
Short name T7
Test name
Test status
Simulation time 364208903 ps
CPU time 2.04 seconds
Started Aug 10 05:24:23 PM PDT 24
Finished Aug 10 05:24:25 PM PDT 24
Peak memory 200104 kb
Host smart-0f462ac7-f80a-4f43-b9d8-249dbc4e8f6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891726603 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst.891726603
Directory /workspace/7.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/7.rstmgr_sw_rst_reset_race.2113706841
Short name T210
Test name
Test status
Simulation time 110982268 ps
CPU time 0.9 seconds
Started Aug 10 05:24:24 PM PDT 24
Finished Aug 10 05:24:25 PM PDT 24
Peak memory 200388 kb
Host smart-17302ad0-3e64-4636-a47c-80dba5ab9a81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113706841 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.rstmgr_sw_rst_reset_race.2113706841
Directory /workspace/7.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/8.rstmgr_alert_test.307976274
Short name T193
Test name
Test status
Simulation time 69485051 ps
CPU time 0.77 seconds
Started Aug 10 05:24:19 PM PDT 24
Finished Aug 10 05:24:20 PM PDT 24
Peak memory 200060 kb
Host smart-88b036ed-21a9-4815-a4e8-34711541a675
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307976274 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_alert_test.307976274
Directory /workspace/8.rstmgr_alert_test/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_cnsty.1628106858
Short name T331
Test name
Test status
Simulation time 2371669217 ps
CPU time 8.76 seconds
Started Aug 10 05:24:27 PM PDT 24
Finished Aug 10 05:24:35 PM PDT 24
Peak memory 217772 kb
Host smart-e74e648f-39c2-44b2-a046-c5cbd61e911a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628106858 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_cnsty.1628106858
Directory /workspace/8.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/8.rstmgr_leaf_rst_shadow_attack.1481421474
Short name T241
Test name
Test status
Simulation time 244374281 ps
CPU time 1.12 seconds
Started Aug 10 05:24:32 PM PDT 24
Finished Aug 10 05:24:33 PM PDT 24
Peak memory 217508 kb
Host smart-cde72d81-2b99-4dd0-a045-ff7d1b9d1f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481421474 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_leaf_rst_shadow_attack.1481421474
Directory /workspace/8.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/8.rstmgr_por_stretcher.1838763135
Short name T165
Test name
Test status
Simulation time 88907068 ps
CPU time 0.77 seconds
Started Aug 10 05:24:18 PM PDT 24
Finished Aug 10 05:24:19 PM PDT 24
Peak memory 199976 kb
Host smart-913cfa7c-c64f-47d5-b1e2-e0797b22c81a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838763135 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_por_stretcher.1838763135
Directory /workspace/8.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/8.rstmgr_reset.4051092193
Short name T528
Test name
Test status
Simulation time 1255659144 ps
CPU time 4.94 seconds
Started Aug 10 05:24:33 PM PDT 24
Finished Aug 10 05:24:38 PM PDT 24
Peak memory 200588 kb
Host smart-a104e240-3d70-44a7-af0a-8ac2fb120dd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051092193 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_reset.4051092193
Directory /workspace/8.rstmgr_reset/latest

Test location /workspace/coverage/default/8.rstmgr_sec_cm_scan_intersig_mubi.4164932502
Short name T181
Test name
Test status
Simulation time 93110203 ps
CPU time 0.99 seconds
Started Aug 10 05:24:29 PM PDT 24
Finished Aug 10 05:24:30 PM PDT 24
Peak memory 200264 kb
Host smart-64bdb7b2-8258-4c50-a25a-85ad96e27c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164932502 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sec_cm_scan_intersig_mubi.4164932502
Directory /workspace/8.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/8.rstmgr_smoke.2614603132
Short name T186
Test name
Test status
Simulation time 190364736 ps
CPU time 1.38 seconds
Started Aug 10 05:24:25 PM PDT 24
Finished Aug 10 05:24:27 PM PDT 24
Peak memory 200364 kb
Host smart-a8081d7d-cb77-471b-bcfc-beb178977f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614603132 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_smoke.2614603132
Directory /workspace/8.rstmgr_smoke/latest

Test location /workspace/coverage/default/8.rstmgr_stress_all.3730752863
Short name T445
Test name
Test status
Simulation time 5356780990 ps
CPU time 18.37 seconds
Started Aug 10 05:24:29 PM PDT 24
Finished Aug 10 05:24:47 PM PDT 24
Peak memory 209620 kb
Host smart-1de5ee24-e17c-4b3a-b2b2-c00e4a4b952f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730752863 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_stress_all.3730752863
Directory /workspace/8.rstmgr_stress_all/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst.1922418261
Short name T506
Test name
Test status
Simulation time 153148161 ps
CPU time 1.82 seconds
Started Aug 10 05:24:30 PM PDT 24
Finished Aug 10 05:24:32 PM PDT 24
Peak memory 200116 kb
Host smart-ec2c5eff-870b-4d28-b397-599533a87252
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922418261 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst.1922418261
Directory /workspace/8.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/8.rstmgr_sw_rst_reset_race.698702805
Short name T468
Test name
Test status
Simulation time 232456530 ps
CPU time 1.38 seconds
Started Aug 10 05:24:34 PM PDT 24
Finished Aug 10 05:24:35 PM PDT 24
Peak memory 200360 kb
Host smart-0442bfaa-8918-4c29-b7ae-11c30857ab70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=698702805 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.rstmgr_sw_rst_reset_race.698702805
Directory /workspace/8.rstmgr_sw_rst_reset_race/latest

Test location /workspace/coverage/default/9.rstmgr_alert_test.3433403581
Short name T58
Test name
Test status
Simulation time 91109519 ps
CPU time 0.89 seconds
Started Aug 10 05:24:27 PM PDT 24
Finished Aug 10 05:24:28 PM PDT 24
Peak memory 200172 kb
Host smart-f40d03f2-75a8-4173-b8f2-45bcdd7ceba6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433403581 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_alert_test.3433403581
Directory /workspace/9.rstmgr_alert_test/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_cnsty.2629633876
Short name T379
Test name
Test status
Simulation time 1907958397 ps
CPU time 7.93 seconds
Started Aug 10 05:24:36 PM PDT 24
Finished Aug 10 05:24:44 PM PDT 24
Peak memory 216796 kb
Host smart-9ea20357-67f0-427d-9add-8444dc9f7f82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629633876 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_cnsty_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_cnsty.2629633876
Directory /workspace/9.rstmgr_leaf_rst_cnsty/latest

Test location /workspace/coverage/default/9.rstmgr_leaf_rst_shadow_attack.3050526512
Short name T168
Test name
Test status
Simulation time 243459384 ps
CPU time 1.04 seconds
Started Aug 10 05:24:29 PM PDT 24
Finished Aug 10 05:24:30 PM PDT 24
Peak memory 217576 kb
Host smart-6d8f8a10-ecfe-41fb-8417-2d48d78fcfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3050526512 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_leaf_rst_shadow_attack_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_leaf_rst_shadow_attack.3050526512
Directory /workspace/9.rstmgr_leaf_rst_shadow_attack/latest

Test location /workspace/coverage/default/9.rstmgr_por_stretcher.2499965953
Short name T146
Test name
Test status
Simulation time 185205597 ps
CPU time 0.87 seconds
Started Aug 10 05:24:27 PM PDT 24
Finished Aug 10 05:24:28 PM PDT 24
Peak memory 200148 kb
Host smart-954f809b-1f48-45b3-890c-7873454d4a42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499965953 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_por_stretcher_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_por_stretcher.2499965953
Directory /workspace/9.rstmgr_por_stretcher/latest

Test location /workspace/coverage/default/9.rstmgr_reset.1507192778
Short name T289
Test name
Test status
Simulation time 1975543046 ps
CPU time 7.14 seconds
Started Aug 10 05:24:29 PM PDT 24
Finished Aug 10 05:24:37 PM PDT 24
Peak memory 200404 kb
Host smart-0d23d668-c350-4b1e-aaea-f77ae39b160c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1507192778 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_reset_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_reset.1507192778
Directory /workspace/9.rstmgr_reset/latest

Test location /workspace/coverage/default/9.rstmgr_sec_cm_scan_intersig_mubi.2498896260
Short name T293
Test name
Test status
Simulation time 112700580 ps
CPU time 1.01 seconds
Started Aug 10 05:24:27 PM PDT 24
Finished Aug 10 05:24:28 PM PDT 24
Peak memory 200260 kb
Host smart-034796e0-4acd-45c8-9b09-bc69a1e6d21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498896260 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sec_cm_scan_intersig_mubi_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sec_cm_scan_intersig_mubi.2498896260
Directory /workspace/9.rstmgr_sec_cm_scan_intersig_mubi/latest

Test location /workspace/coverage/default/9.rstmgr_smoke.534063882
Short name T380
Test name
Test status
Simulation time 245650860 ps
CPU time 1.64 seconds
Started Aug 10 05:24:29 PM PDT 24
Finished Aug 10 05:24:31 PM PDT 24
Peak memory 200428 kb
Host smart-36637728-5630-4278-a733-aaa4e73ecb5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534063882 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_smoke.534063882
Directory /workspace/9.rstmgr_smoke/latest

Test location /workspace/coverage/default/9.rstmgr_stress_all.2184085174
Short name T288
Test name
Test status
Simulation time 2292718094 ps
CPU time 10.4 seconds
Started Aug 10 05:24:29 PM PDT 24
Finished Aug 10 05:24:40 PM PDT 24
Peak memory 200588 kb
Host smart-5add0ab6-1365-4aa6-a2cf-26df2d40cd9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184085174 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_stress_all.2184085174
Directory /workspace/9.rstmgr_stress_all/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst.2431696179
Short name T355
Test name
Test status
Simulation time 355450925 ps
CPU time 2.36 seconds
Started Aug 10 05:24:25 PM PDT 24
Finished Aug 10 05:24:28 PM PDT 24
Peak memory 200312 kb
Host smart-4e8fe59d-4040-4122-bb02-3f189ab333f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431696179 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst.2431696179
Directory /workspace/9.rstmgr_sw_rst/latest

Test location /workspace/coverage/default/9.rstmgr_sw_rst_reset_race.3624787737
Short name T256
Test name
Test status
Simulation time 64828288 ps
CPU time 0.78 seconds
Started Aug 10 05:24:29 PM PDT 24
Finished Aug 10 05:24:30 PM PDT 24
Peak memory 200352 kb
Host smart-b571a7a0-a115-43c0-8e8d-e14d63208a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624787737 -assert nopostproc +UVM_TESTNAME=rstmgr_base_test +UVM_TEST_SEQ=rstmgr_sw_rst_reset_race_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.rstmgr_sw_rst_reset_race.3624787737
Directory /workspace/9.rstmgr_sw_rst_reset_race/latest
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