Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	651889	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

389735

1

T1

77

T2

385

T3

5536

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	557902	1			T1	99		T2	539		T3	8386
values[0x0]	242188	1			T1	44		T2	258		T3	3225
values[0x1]	241534	1			T1	69		T2	235		T3	3262

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	546955	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

494669

1

T1

101

T2

487

T3

7055

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4479	1			T2	3		T3	66		T8	185
valid_sources[0x01]	3894	1			T2	3		T3	53		T8	143
valid_sources[0x02]	4252	1			T2	2		T3	55		T8	196
valid_sources[0x03]	3466	1			T2	4		T3	52		T8	28
valid_sources[0x04]	3765	1			T2	2		T3	58		T8	38
valid_sources[0x05]	3178	1			T2	3		T3	72		T8	31
valid_sources[0x06]	4037	1			T2	1		T3	59		T8	217
valid_sources[0x07]	4514	1			T2	6		T3	63		T8	152
valid_sources[0x08]	3455	1			T2	7		T3	67		T8	73
valid_sources[0x09]	4125	1			T2	4		T3	39		T8	56
valid_sources[0x0a]	4792	1			T2	6		T3	59		T8	101
valid_sources[0x0b]	3226	1			T2	3		T3	62		T8	87
valid_sources[0x0c]	4657	1			T2	5		T3	65		T8	85
valid_sources[0x0d]	3813	1			T2	4		T3	51		T8	103
valid_sources[0x0e]	4358	1			T2	2		T3	49		T8	92
valid_sources[0x0f]	4339	1			T2	4		T3	39		T8	68
valid_sources[0x10]	3926	1			T2	6		T3	42		T8	93
valid_sources[0x11]	2956	1			T2	7		T3	56		T8	54
valid_sources[0x12]	3653	1			T2	1		T3	56		T8	107
valid_sources[0x13]	4929	1			T2	4		T3	48		T8	77
valid_sources[0x14]	3617	1			T2	2		T3	67		T8	44
valid_sources[0x15]	4231	1			T2	6		T3	61		T8	176
valid_sources[0x16]	3261	1			T2	5		T3	43		T8	75
valid_sources[0x17]	3882	1			T3	65		T8	114		T9	20
valid_sources[0x18]	5485	1			T1	8		T2	1		T3	65
valid_sources[0x19]	3579	1			T2	4		T3	74		T8	57
valid_sources[0x1a]	3990	1			T2	5		T3	58		T8	74
valid_sources[0x1b]	3187	1			T2	3		T3	55		T8	71
valid_sources[0x1c]	3429	1			T2	6		T3	51		T8	36
valid_sources[0x1d]	3901	1			T2	3		T3	61		T8	85
valid_sources[0x1e]	3577	1			T2	6		T3	56		T8	169
valid_sources[0x1f]	3787	1			T2	7		T3	70		T8	79
valid_sources[0x20]	3638	1			T1	3		T2	6		T3	53
valid_sources[0x21]	3155	1			T2	5		T3	63		T8	42
valid_sources[0x22]	4094	1			T2	2		T3	65		T8	104
valid_sources[0x23]	4487	1			T1	2		T2	5		T3	49
valid_sources[0x24]	4425	1			T2	3		T3	64		T8	42
valid_sources[0x25]	3417	1			T2	2		T3	48		T8	55
valid_sources[0x26]	3457	1			T2	2		T3	70		T8	30
valid_sources[0x27]	4562	1			T2	7		T3	62		T8	95
valid_sources[0x28]	5070	1			T2	3		T3	67		T8	59
valid_sources[0x29]	3464	1			T2	3		T3	51		T8	85
valid_sources[0x2a]	4118	1			T2	6		T3	57		T8	78
valid_sources[0x2b]	4833	1			T1	6		T2	4		T3	60
valid_sources[0x2c]	4050	1			T2	3		T3	56		T8	69
valid_sources[0x2d]	3486	1			T2	2		T3	54		T8	148
valid_sources[0x2e]	3913	1			T2	2		T3	49		T8	14
valid_sources[0x2f]	3827	1			T2	3		T3	63		T8	86
valid_sources[0x30]	4264	1			T2	4		T3	56		T8	20
valid_sources[0x31]	7826	1			T2	6		T3	44		T8	102
valid_sources[0x32]	7315	1			T1	5		T2	4		T3	60
valid_sources[0x33]	4512	1			T2	4		T3	89		T8	119
valid_sources[0x34]	3302	1			T2	3		T3	59		T8	96
valid_sources[0x35]	3791	1			T2	3		T3	62		T8	24
valid_sources[0x36]	5536	1			T2	1		T3	48		T8	184
valid_sources[0x37]	3658	1			T2	5		T3	62		T8	64
valid_sources[0x38]	3379	1			T2	2		T3	58		T8	27
valid_sources[0x39]	4032	1			T2	1		T3	50		T8	67
valid_sources[0x3a]	4115	1			T2	3		T3	62		T8	264
valid_sources[0x3b]	4714	1			T2	2		T3	62		T8	173
valid_sources[0x3c]	3910	1			T2	8		T3	51		T8	108
valid_sources[0x3d]	3881	1			T2	6		T3	72		T8	18
valid_sources[0x3e]	3556	1			T2	2		T3	81		T8	50
valid_sources[0x3f]	4341	1			T2	6		T3	72		T8	66
valid_sources[0x40]	4428	1			T2	6		T3	69		T8	69
valid_sources[0x41]	3514	1			T2	8		T3	76		T8	17
valid_sources[0x42]	3904	1			T1	11		T2	5		T3	70
valid_sources[0x43]	3126	1			T2	7		T3	48		T8	77
valid_sources[0x44]	3627	1			T2	5		T3	43		T8	102
valid_sources[0x45]	3399	1			T2	1		T3	77		T8	16
valid_sources[0x46]	4417	1			T2	3		T3	61		T8	31
valid_sources[0x47]	4445	1			T1	5		T2	1		T3	48
valid_sources[0x48]	3672	1			T2	4		T3	65		T8	152
valid_sources[0x49]	3550	1			T2	4		T3	53		T8	80
valid_sources[0x4a]	3529	1			T2	2		T3	58		T8	89
valid_sources[0x4b]	4336	1			T2	8		T3	57		T8	87
valid_sources[0x4c]	3434	1			T2	7		T3	61		T8	178
valid_sources[0x4d]	4002	1			T1	9		T2	6		T3	71
valid_sources[0x4e]	3304	1			T2	1		T3	56		T8	98
valid_sources[0x4f]	4403	1			T1	11		T2	4		T3	55
valid_sources[0x50]	3657	1			T2	3		T3	55		T8	86
valid_sources[0x51]	4120	1			T2	4		T3	66		T8	41
valid_sources[0x52]	4549	1			T2	5		T3	54		T8	17
valid_sources[0x53]	3917	1			T1	11		T2	7		T3	54
valid_sources[0x54]	6720	1			T1	2		T2	4		T3	42
valid_sources[0x55]	5416	1			T2	1		T3	46		T8	151
valid_sources[0x56]	3031	1			T1	8		T2	4		T3	54
valid_sources[0x57]	3932	1			T2	4		T3	57		T8	32
valid_sources[0x58]	6398	1			T1	2		T2	4		T3	60
valid_sources[0x59]	6402	1			T2	4		T3	58		T8	42
valid_sources[0x5a]	4373	1			T2	2		T3	41		T8	23
valid_sources[0x5b]	6091	1			T2	4		T3	60		T8	209
valid_sources[0x5c]	4992	1			T2	4		T3	65		T8	150
valid_sources[0x5d]	4176	1			T2	4		T3	58		T8	54
valid_sources[0x5e]	4379	1			T2	6		T3	61		T8	158
valid_sources[0x5f]	3331	1			T1	1		T2	3		T3	70
valid_sources[0x60]	4127	1			T2	7		T3	49		T8	73
valid_sources[0x61]	2823	1			T2	6		T3	68		T8	44
valid_sources[0x62]	3019	1			T2	7		T3	64		T8	24
valid_sources[0x63]	3501	1			T2	4		T3	62		T8	275
valid_sources[0x64]	3347	1			T2	4		T3	52		T8	80
valid_sources[0x65]	3523	1			T2	3		T3	52		T8	110
valid_sources[0x66]	4310	1			T2	12		T3	71		T8	163
valid_sources[0x67]	4148	1			T2	3		T3	59		T8	6
valid_sources[0x68]	3365	1			T2	7		T3	64		T8	250
valid_sources[0x69]	4280	1			T2	2		T3	75		T8	188
valid_sources[0x6a]	3034	1			T2	4		T3	67		T8	160
valid_sources[0x6b]	3246	1			T2	7		T3	64		T8	63
valid_sources[0x6c]	3606	1			T2	5		T3	71		T8	71
valid_sources[0x6d]	3844	1			T2	2		T3	63		T8	68
valid_sources[0x6e]	4369	1			T2	4		T3	38		T8	100
valid_sources[0x6f]	3316	1			T2	8		T3	58		T8	89
valid_sources[0x70]	3565	1			T1	4		T2	3		T3	53
valid_sources[0x71]	6656	1			T2	3		T3	46		T8	93
valid_sources[0x72]	4236	1			T2	1		T3	77		T8	133
valid_sources[0x73]	3324	1			T2	4		T3	64		T8	148
valid_sources[0x74]	4326	1			T1	3		T2	6		T3	53
valid_sources[0x75]	3283	1			T2	5		T3	53		T8	81
valid_sources[0x76]	4109	1			T1	10		T2	5		T3	62
valid_sources[0x77]	3360	1			T2	4		T3	50		T8	177
valid_sources[0x78]	3820	1			T2	4		T3	53		T8	74
valid_sources[0x79]	3030	1			T2	2		T3	62		T8	106
valid_sources[0x7a]	3284	1			T2	2		T3	76		T8	22
valid_sources[0x7b]	3973	1			T2	6		T3	64		T8	55
valid_sources[0x7c]	6986	1			T2	2		T3	62		T8	77
valid_sources[0x7d]	5891	1			T2	3		T3	55		T8	38
valid_sources[0x7e]	3905	1			T2	7		T3	45		T8	53
valid_sources[0x7f]	3553	1			T2	5		T3	63		T8	142
valid_sources[0x80]	3720	1			T2	11		T3	57		T8	114

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

260819

1

T1

48

T2

258

T3

3902

values[0x0]

all_enables

biggest_size

84528

1

T1

14

T2

95

T3

1088

values[0x1]

all_enables

biggest_size

44388

1

T1

15

T2

32

T3

546