| SCORE | INSTANCES | WEIGHT | GOAL | AT LEAST | PER INSTANCE | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 58.33 | 1 | 100 | 1 | 1 | 64 | 64 | 
| NAME | SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| mubi4_cov_of_mubi4_cov_of_rstmgr_reg_block.reset_req.val | 16.67 | 1 | 100 | 1 | 64 | 64 | 
| mubi4_cov_of_mubi4_cov_of_tb.dut.u_scanmode_mubi_cov_if | 100.00 | 1 | 100 | 1 | 64 | 64 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 16.67 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 6 | 5 | 1 | 16.67 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 6 | 5 | 1 | 16.67 | 100 | 1 | 1 | 0 | 
| SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING | 
| 100.00 | 1 | 100 | 1 | 64 | 64 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| Variables | 6 | 0 | 6 | 100.00 | 
| VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT | 
| cp_value | 6 | 0 | 6 | 100.00 | 100 | 1 | 1 | 0 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 6 | 5 | 1 | 16.67 | 
| NAME | COUNT | AT LEAST | NUMBER | STATUS | 
| others[0] | 0 | 1 | 1 | |
| others[1] | 0 | 1 | 1 | |
| others[2] | 0 | 1 | 1 | |
| others[3] | 0 | 1 | 1 | |
| false | 0 | 1 | 1 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| true | 5692 | 1 | T1 | 1 | T3 | 97 | T5 | 1 | 
| CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT | 
| User Defined Bins | 6 | 0 | 6 | 100.00 | 
| NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
| others[0] | 673 | 1 | T1 | 14 | T5 | 7 | T82 | 5 | ||||
| others[1] | 696 | 1 | T1 | 14 | T5 | 4 | T82 | 6 | ||||
| others[2] | 698 | 1 | T1 | 18 | T5 | 7 | T82 | 7 | ||||
| others[3] | 1155 | 1 | T1 | 27 | T5 | 13 | T82 | 8 | ||||
| false | 24025 | 1 | T1 | 21 | T2 | 1 | T3 | 295 | ||||
| true | 2472 | 1 | T1 | 1 | T3 | 52 | T5 | 1 | 
| 0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |