Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T3,T5

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	12114692	13996	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	12114692	129197	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	12114692	7293799	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	12114692	206515	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	12114692	13996	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	12114692	129197	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	12114692	7293799	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	12114692	206515	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12114692	13996	0	0
T1	3312	4	0	0
T2	3349	0	0	0
T3	89752	190	0	0
T4	1458	0	0	0
T5	2283	4	0	0
T6	3089	0	0	0
T7	5093	0	0	0
T8	143917	305	0	0
T9	46117	36	0	0
T10	116075	120	0	0
T12	0	4	0	0
T13	0	122	0	0
T23	0	4	0	0
T24	0	4	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12114692	129197	0	0
T1	3312	37	0	0
T2	3349	0	0	0
T3	89752	1737	0	0
T4	1458	0	0	0
T5	2283	37	0	0
T6	3089	0	0	0
T7	5093	0	0	0
T8	143917	2819	0	0
T9	46117	326	0	0
T10	116075	1084	0	0
T12	0	37	0	0
T13	0	1106	0	0
T23	0	38	0	0
T24	0	38	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12114692	7293799	0	0
T1	3312	2384	0	0
T2	3349	2773	0	0
T3	89752	41887	0	0
T4	1458	832	0	0
T5	2283	1287	0	0
T6	3089	615	0	0
T7	5093	577	0	0
T8	143917	71147	0	0
T9	46117	35174	0	0
T10	116075	85238	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12114692	206515	0	0
T1	3312	53	0	0
T2	3349	0	0	0
T3	89752	2785	0	0
T4	1458	0	0	0
T5	2283	47	0	0
T6	3089	0	0	0
T7	5093	0	0	0
T8	143917	4520	0	0
T9	46117	521	0	0
T10	116075	1757	0	0
T12	0	46	0	0
T13	0	1756	0	0
T23	0	58	0	0
T24	0	46	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12114692	13996	0	0
T1	3312	4	0	0
T2	3349	0	0	0
T3	89752	190	0	0
T4	1458	0	0	0
T5	2283	4	0	0
T6	3089	0	0	0
T7	5093	0	0	0
T8	143917	305	0	0
T9	46117	36	0	0
T10	116075	120	0	0
T12	0	4	0	0
T13	0	122	0	0
T23	0	4	0	0
T24	0	4	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12114692	129197	0	0
T1	3312	37	0	0
T2	3349	0	0	0
T3	89752	1737	0	0
T4	1458	0	0	0
T5	2283	37	0	0
T6	3089	0	0	0
T7	5093	0	0	0
T8	143917	2819	0	0
T9	46117	326	0	0
T10	116075	1084	0	0
T12	0	37	0	0
T13	0	1106	0	0
T23	0	38	0	0
T24	0	38	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12114692	7293799	0	0
T1	3312	2384	0	0
T2	3349	2773	0	0
T3	89752	41887	0	0
T4	1458	832	0	0
T5	2283	1287	0	0
T6	3089	615	0	0
T7	5093	577	0	0
T8	143917	71147	0	0
T9	46117	35174	0	0
T10	116075	85238	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12114692	206515	0	0
T1	3312	53	0	0
T2	3349	0	0	0
T3	89752	2785	0	0
T4	1458	0	0	0
T5	2283	47	0	0
T6	3089	0	0	0
T7	5093	0	0	0
T8	143917	4520	0	0
T9	46117	521	0	0
T10	116075	1757	0	0
T12	0	46	0	0
T13	0	1756	0	0
T23	0	58	0	0
T24	0	46	0	0