Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T5
0	1	Covered	T3,T5,T8
1	0	Covered	T3,T8,T9

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T7
1	0	Covered	T1,T3,T5
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	57200454	9051	0	0
CascadeEffAonToRstPorAboveRise_A	57200454	9051	0	0
CascadeEffAonToRstPorIoAboveFall_A	54910853	9051	0	0
CascadeEffAonToRstPorIoAboveRise_A	54910853	9051	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27456414	9051	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27456414	9051	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13727933	9051	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13727933	9051	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27456419	9051	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27456419	9051	0	0
CascadeLcToLcAboveFall_A	57200454	23047	0	0
CascadeLcToLcAboveRise_A	57200454	23047	0	0
CascadeLcToLcAonAboveFall_A	1733748	23047	0	0
CascadeLcToLcAonAboveRise_A	1733748	23047	0	0
CascadeLcToLcShadowedAboveFall_A	57200454	23047	0	0
CascadeLcToLcShadowedAboveRise_A	57200454	23047	0	0
CascadePorToAonAboveFall_A	1733748	7028	0	0
CascadeSysToSysAboveFall_A	57200454	23047	0	0
CascadeSysToSysAboveRise_A	57200454	23047	0	0
ScanRstToAonRise_A	1733748	206	0	0
StablePorToAonRise_A	1733748	9051	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12114692	23047	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12114692	23047	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12114692	23047	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12114692	23047	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13727933	23047	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13727933	23047	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12114692	23047	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12114692	23047	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12114692	23047	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12114692	23047	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57200454	9051	0	0
T1	14999	2	0	0
T2	14334	1	0	0
T3	486587	105	0	0
T4	6256	1	0	0
T5	10329	2	0	0
T6	13352	2	0	0
T7	24290	8	0	0
T8	770080	161	0	0
T9	215775	26	0	0
T10	543282	66	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57200454	9051	0	0
T1	14999	2	0	0
T2	14334	1	0	0
T3	486587	105	0	0
T4	6256	1	0	0
T5	10329	2	0	0
T6	13352	2	0	0
T7	24290	8	0	0
T8	770080	161	0	0
T9	215775	26	0	0
T10	543282	66	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54910853	9051	0	0
T1	14401	2	0	0
T2	13761	1	0	0
T3	467112	105	0	0
T4	6005	1	0	0
T5	9918	2	0	0
T6	12818	2	0	0
T7	23335	8	0	0
T8	739321	161	0	0
T9	207173	26	0	0
T10	521515	66	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54910853	9051	0	0
T1	14401	2	0	0
T2	13761	1	0	0
T3	467112	105	0	0
T4	6005	1	0	0
T5	9918	2	0	0
T6	12818	2	0	0
T7	23335	8	0	0
T8	739321	161	0	0
T9	207173	26	0	0
T10	521515	66	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27456414	9051	0	0
T1	7200	2	0	0
T2	6880	1	0	0
T3	233575	105	0	0
T4	3002	1	0	0
T5	4955	2	0	0
T6	6408	2	0	0
T7	11665	8	0	0
T8	369664	161	0	0
T9	103582	26	0	0
T10	260775	66	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27456414	9051	0	0
T1	7200	2	0	0
T2	6880	1	0	0
T3	233575	105	0	0
T4	3002	1	0	0
T5	4955	2	0	0
T6	6408	2	0	0
T7	11665	8	0	0
T8	369664	161	0	0
T9	103582	26	0	0
T10	260775	66	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13727933	9051	0	0
T1	3601	2	0	0
T2	3438	1	0	0
T3	116789	105	0	0
T4	1500	1	0	0
T5	2477	2	0	0
T6	3203	2	0	0
T7	5829	8	0	0
T8	184853	161	0	0
T9	51796	26	0	0
T10	130388	66	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13727933	9051	0	0
T1	3601	2	0	0
T2	3438	1	0	0
T3	116789	105	0	0
T4	1500	1	0	0
T5	2477	2	0	0
T6	3203	2	0	0
T7	5829	8	0	0
T8	184853	161	0	0
T9	51796	26	0	0
T10	130388	66	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27456419	9051	0	0
T1	7201	2	0	0
T2	6880	1	0	0
T3	233561	105	0	0
T4	3001	1	0	0
T5	4957	2	0	0
T6	6408	2	0	0
T7	11665	8	0	0
T8	369664	161	0	0
T9	103583	26	0	0
T10	260761	66	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27456419	9051	0	0
T1	7201	2	0	0
T2	6880	1	0	0
T3	233561	105	0	0
T4	3001	1	0	0
T5	4957	2	0	0
T6	6408	2	0	0
T7	11665	8	0	0
T8	369664	161	0	0
T9	103583	26	0	0
T10	260761	66	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57200454	23047	0	0
T1	14999	6	0	0
T2	14334	1	0	0
T3	486587	295	0	0
T4	6256	1	0	0
T5	10329	6	0	0
T6	13352	2	0	0
T7	24290	8	0	0
T8	770080	466	0	0
T9	215775	62	0	0
T10	543282	186	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57200454	23047	0	0
T1	14999	6	0	0
T2	14334	1	0	0
T3	486587	295	0	0
T4	6256	1	0	0
T5	10329	6	0	0
T6	13352	2	0	0
T7	24290	8	0	0
T8	770080	466	0	0
T9	215775	62	0	0
T10	543282	186	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1733748	23047	0	0
T1	449	6	0	0
T2	428	1	0	0
T3	14974	295	0	0
T4	186	1	0	0
T5	309	6	0	0
T6	398	2	0	0
T7	732	8	0	0
T8	23673	466	0	0
T9	6527	62	0	0
T10	16558	186	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1733748	23047	0	0
T1	449	6	0	0
T2	428	1	0	0
T3	14974	295	0	0
T4	186	1	0	0
T5	309	6	0	0
T6	398	2	0	0
T7	732	8	0	0
T8	23673	466	0	0
T9	6527	62	0	0
T10	16558	186	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57200454	23047	0	0
T1	14999	6	0	0
T2	14334	1	0	0
T3	486587	295	0	0
T4	6256	1	0	0
T5	10329	6	0	0
T6	13352	2	0	0
T7	24290	8	0	0
T8	770080	466	0	0
T9	215775	62	0	0
T10	543282	186	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57200454	23047	0	0
T1	14999	6	0	0
T2	14334	1	0	0
T3	486587	295	0	0
T4	6256	1	0	0
T5	10329	6	0	0
T6	13352	2	0	0
T7	24290	8	0	0
T8	770080	466	0	0
T9	215775	62	0	0
T10	543282	186	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1733748	7028	0	0
T1	449	1	0	0
T2	428	1	0	0
T3	14974	53	0	0
T4	186	1	0	0
T5	309	1	0	0
T6	398	11	0	0
T7	732	8	0	0
T8	23673	80	0	0
T9	6527	10	0	0
T10	16558	36	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57200454	23047	0	0
T1	14999	6	0	0
T2	14334	1	0	0
T3	486587	295	0	0
T4	6256	1	0	0
T5	10329	6	0	0
T6	13352	2	0	0
T7	24290	8	0	0
T8	770080	466	0	0
T9	215775	62	0	0
T10	543282	186	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	57200454	23047	0	0
T1	14999	6	0	0
T2	14334	1	0	0
T3	486587	295	0	0
T4	6256	1	0	0
T5	10329	6	0	0
T6	13352	2	0	0
T7	24290	8	0	0
T8	770080	466	0	0
T9	215775	62	0	0
T10	543282	186	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1733748	206	0	0
T3	14974	3	0	0
T4	186	0	0	0
T5	309	0	0	0
T6	398	0	0	0
T7	732	0	0	0
T8	23673	5	0	0
T9	6527	1	0	0
T10	16558	3	0	0
T11	460	0	0	0
T13	0	4	0	0
T22	161	0	0	0
T60	0	1	0	0
T70	0	1	0	0
T84	0	2	0	0
T99	0	3	0	0
T105	0	5	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1733748	9051	0	0
T1	449	2	0	0
T2	428	1	0	0
T3	14974	105	0	0
T4	186	1	0	0
T5	309	2	0	0
T6	398	2	0	0
T7	732	8	0	0
T8	23673	161	0	0
T9	6527	26	0	0
T10	16558	66	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12114692	23047	0	0
T1	3312	6	0	0
T2	3349	1	0	0
T3	89752	295	0	0
T4	1458	1	0	0
T5	2283	6	0	0
T6	3089	2	0	0
T7	5093	8	0	0
T8	143917	466	0	0
T9	46117	62	0	0
T10	116075	186	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12114692	23047	0	0
T1	3312	6	0	0
T2	3349	1	0	0
T3	89752	295	0	0
T4	1458	1	0	0
T5	2283	6	0	0
T6	3089	2	0	0
T7	5093	8	0	0
T8	143917	466	0	0
T9	46117	62	0	0
T10	116075	186	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12114692	23047	0	0
T1	3312	6	0	0
T2	3349	1	0	0
T3	89752	295	0	0
T4	1458	1	0	0
T5	2283	6	0	0
T6	3089	2	0	0
T7	5093	8	0	0
T8	143917	466	0	0
T9	46117	62	0	0
T10	116075	186	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12114692	23047	0	0
T1	3312	6	0	0
T2	3349	1	0	0
T3	89752	295	0	0
T4	1458	1	0	0
T5	2283	6	0	0
T6	3089	2	0	0
T7	5093	8	0	0
T8	143917	466	0	0
T9	46117	62	0	0
T10	116075	186	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13727933	23047	0	0
T1	3601	6	0	0
T2	3438	1	0	0
T3	116789	295	0	0
T4	1500	1	0	0
T5	2477	6	0	0
T6	3203	2	0	0
T7	5829	8	0	0
T8	184853	466	0	0
T9	51796	62	0	0
T10	130388	186	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13727933	23047	0	0
T1	3601	6	0	0
T2	3438	1	0	0
T3	116789	295	0	0
T4	1500	1	0	0
T5	2477	6	0	0
T6	3203	2	0	0
T7	5829	8	0	0
T8	184853	466	0	0
T9	51796	62	0	0
T10	130388	186	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12114692	23047	0	0
T1	3312	6	0	0
T2	3349	1	0	0
T3	89752	295	0	0
T4	1458	1	0	0
T5	2283	6	0	0
T6	3089	2	0	0
T7	5093	8	0	0
T8	143917	466	0	0
T9	46117	62	0	0
T10	116075	186	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12114692	23047	0	0
T1	3312	6	0	0
T2	3349	1	0	0
T3	89752	295	0	0
T4	1458	1	0	0
T5	2283	6	0	0
T6	3089	2	0	0
T7	5093	8	0	0
T8	143917	466	0	0
T9	46117	62	0	0
T10	116075	186	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12114692	23047	0	0
T1	3312	6	0	0
T2	3349	1	0	0
T3	89752	295	0	0
T4	1458	1	0	0
T5	2283	6	0	0
T6	3089	2	0	0
T7	5093	8	0	0
T8	143917	466	0	0
T9	46117	62	0	0
T10	116075	186	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12114692	23047	0	0
T1	3312	6	0	0
T2	3349	1	0	0
T3	89752	295	0	0
T4	1458	1	0	0
T5	2283	6	0	0
T6	3089	2	0	0
T7	5093	8	0	0
T8	143917	466	0	0
T9	46117	62	0	0
T10	116075	186	0	0