Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T10
1	0	Covered	T1,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T10
1	0	Covered	T1,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T10
1	0	Covered	T1,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T10
1	0	Covered	T1,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T8,T10
1	0	Covered	T1,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T3,T5

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T8
1	0	Covered	T1,T3,T5

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13727933	14808	0	0
gen_assertions[0].RstEnOn_A	13727933	1040	0	0
gen_assertions[0].RstNOff_A	13727933	14808	0	0
gen_assertions[0].RstNOn_A	13727933	1040	0	0
gen_assertions[1].RstEnOff_A	54910853	13423	0	0
gen_assertions[1].RstEnOn_A	54910853	970	0	0
gen_assertions[1].RstNOff_A	54910853	13423	0	0
gen_assertions[1].RstNOn_A	54910853	970	0	0
gen_assertions[2].RstEnOff_A	27456414	13481	0	0
gen_assertions[2].RstEnOn_A	27456414	968	0	0
gen_assertions[2].RstNOff_A	27456414	13481	0	0
gen_assertions[2].RstNOn_A	27456414	968	0	0
gen_assertions[3].RstEnOff_A	27456419	13507	0	0
gen_assertions[3].RstEnOn_A	27456419	987	0	0
gen_assertions[3].RstNOff_A	27456419	13507	0	0
gen_assertions[3].RstNOn_A	27456419	987	0	0
gen_assertions[4].RstEnOff_A	1733748	22821	0	0
gen_assertions[4].RstEnOn_A	1733748	1054	0	0
gen_assertions[4].RstNOff_A	1733748	22821	0	0
gen_assertions[4].RstNOn_A	1733748	1054	0	0
gen_assertions[5].RstEnOff_A	13727933	15056	0	0
gen_assertions[5].RstEnOn_A	13727933	1100	0	0
gen_assertions[5].RstNOff_A	13727933	15056	0	0
gen_assertions[5].RstNOn_A	13727933	1100	0	0
gen_assertions[6].RstEnOff_A	13727933	15093	0	0
gen_assertions[6].RstEnOn_A	13727933	1142	0	0
gen_assertions[6].RstNOff_A	13727933	15093	0	0
gen_assertions[6].RstNOn_A	13727933	1142	0	0
gen_assertions[7].RstEnOff_A	13727933	15168	0	0
gen_assertions[7].RstEnOn_A	13727933	1218	0	0
gen_assertions[7].RstNOff_A	13727933	15168	0	0
gen_assertions[7].RstNOn_A	13727933	1218	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13727933	14808	0	0
T1	3601	4	0	0
T2	3438	6	0	0
T3	116789	190	0	0
T4	1500	0	0	0
T5	2477	4	0	0
T6	3203	0	0	0
T7	5829	0	0	0
T8	184853	315	0	0
T9	51796	36	0	0
T10	130388	143	0	0
T12	0	4	0	0
T13	0	142	0	0
T23	0	5	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13727933	1040	0	0
T2	3438	6	0	0
T3	116789	0	0	0
T4	1500	0	0	0
T5	2477	0	0	0
T6	3203	0	0	0
T7	5829	0	0	0
T8	184853	13	0	0
T9	51796	0	0	0
T10	130388	23	0	0
T11	3693	0	0	0
T13	0	23	0	0
T23	0	1	0	0
T24	0	1	0	0
T62	0	5	0	0
T63	0	3	0	0
T69	0	1	0	0
T86	0	5	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13727933	14808	0	0
T1	3601	4	0	0
T2	3438	6	0	0
T3	116789	190	0	0
T4	1500	0	0	0
T5	2477	4	0	0
T6	3203	0	0	0
T7	5829	0	0	0
T8	184853	315	0	0
T9	51796	36	0	0
T10	130388	143	0	0
T12	0	4	0	0
T13	0	142	0	0
T23	0	5	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13727933	1040	0	0
T2	3438	6	0	0
T3	116789	0	0	0
T4	1500	0	0	0
T5	2477	0	0	0
T6	3203	0	0	0
T7	5829	0	0	0
T8	184853	13	0	0
T9	51796	0	0	0
T10	130388	23	0	0
T11	3693	0	0	0
T13	0	23	0	0
T23	0	1	0	0
T24	0	1	0	0
T62	0	5	0	0
T63	0	3	0	0
T69	0	1	0	0
T86	0	5	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54910853	13423	0	0
T1	14401	4	0	0
T2	13761	7	0	0
T3	467112	170	0	0
T4	6005	0	0	0
T5	9918	3	0	0
T6	12818	0	0	0
T7	23335	0	0	0
T8	739321	284	0	0
T9	207173	33	0	0
T10	521515	134	0	0
T12	0	1	0	0
T13	0	126	0	0
T23	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54910853	970	0	0
T2	13761	7	0	0
T3	467112	0	0	0
T4	6005	0	0	0
T5	9918	0	0	0
T6	12818	0	0	0
T7	23335	0	0	0
T8	739321	13	0	0
T9	207173	0	0	0
T10	521515	30	0	0
T11	14773	0	0	0
T13	0	22	0	0
T24	0	1	0	0
T55	0	4	0	0
T62	0	7	0	0
T63	0	4	0	0
T86	0	5	0	0
T87	0	8	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54910853	13423	0	0
T1	14401	4	0	0
T2	13761	7	0	0
T3	467112	170	0	0
T4	6005	0	0	0
T5	9918	3	0	0
T6	12818	0	0	0
T7	23335	0	0	0
T8	739321	284	0	0
T9	207173	33	0	0
T10	521515	134	0	0
T12	0	1	0	0
T13	0	126	0	0
T23	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54910853	970	0	0
T2	13761	7	0	0
T3	467112	0	0	0
T4	6005	0	0	0
T5	9918	0	0	0
T6	12818	0	0	0
T7	23335	0	0	0
T8	739321	13	0	0
T9	207173	0	0	0
T10	521515	30	0	0
T11	14773	0	0	0
T13	0	22	0	0
T24	0	1	0	0
T55	0	4	0	0
T62	0	7	0	0
T63	0	4	0	0
T86	0	5	0	0
T87	0	8	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27456414	13481	0	0
T1	7200	4	0	0
T2	6880	7	0	0
T3	233575	170	0	0
T4	3002	0	0	0
T5	4955	3	0	0
T6	6408	0	0	0
T7	11665	0	0	0
T8	369664	286	0	0
T9	103582	33	0	0
T10	260775	128	0	0
T12	0	2	0	0
T13	0	125	0	0
T23	0	5	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27456414	968	0	0
T2	6880	7	0	0
T3	233575	1	0	0
T4	3002	0	0	0
T5	4955	0	0	0
T6	6408	0	0	0
T7	11665	0	0	0
T8	369664	12	0	0
T9	103582	0	0	0
T10	260775	22	0	0
T11	7386	0	0	0
T12	0	1	0	0
T13	0	21	0	0
T23	0	1	0	0
T62	0	7	0	0
T63	0	5	0	0
T88	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27456414	13481	0	0
T1	7200	4	0	0
T2	6880	7	0	0
T3	233575	170	0	0
T4	3002	0	0	0
T5	4955	3	0	0
T6	6408	0	0	0
T7	11665	0	0	0
T8	369664	286	0	0
T9	103582	33	0	0
T10	260775	128	0	0
T12	0	2	0	0
T13	0	125	0	0
T23	0	5	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27456414	968	0	0
T2	6880	7	0	0
T3	233575	1	0	0
T4	3002	0	0	0
T5	4955	0	0	0
T6	6408	0	0	0
T7	11665	0	0	0
T8	369664	12	0	0
T9	103582	0	0	0
T10	260775	22	0	0
T11	7386	0	0	0
T12	0	1	0	0
T13	0	21	0	0
T23	0	1	0	0
T62	0	7	0	0
T63	0	5	0	0
T88	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27456419	13507	0	0
T1	7201	4	0	0
T2	6880	11	0	0
T3	233561	170	0	0
T4	3001	0	0	0
T5	4957	3	0	0
T6	6408	0	0	0
T7	11665	0	0	0
T8	369664	286	0	0
T9	103583	33	0	0
T10	260761	127	0	0
T12	0	1	0	0
T13	0	123	0	0
T23	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27456419	987	0	0
T2	6880	11	0	0
T3	233561	0	0	0
T4	3001	0	0	0
T5	4957	0	0	0
T6	6408	0	0	0
T7	11665	0	0	0
T8	369664	13	0	0
T9	103583	0	0	0
T10	260761	21	0	0
T11	7385	0	0	0
T13	0	19	0	0
T62	0	8	0	0
T63	0	5	0	0
T69	0	1	0	0
T70	0	1	0	0
T86	0	8	0	0
T87	0	11	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27456419	13507	0	0
T1	7201	4	0	0
T2	6880	11	0	0
T3	233561	170	0	0
T4	3001	0	0	0
T5	4957	3	0	0
T6	6408	0	0	0
T7	11665	0	0	0
T8	369664	286	0	0
T9	103583	33	0	0
T10	260761	127	0	0
T12	0	1	0	0
T13	0	123	0	0
T23	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27456419	987	0	0
T2	6880	11	0	0
T3	233561	0	0	0
T4	3001	0	0	0
T5	4957	0	0	0
T6	6408	0	0	0
T7	11665	0	0	0
T8	369664	13	0	0
T9	103583	0	0	0
T10	260761	21	0	0
T11	7385	0	0	0
T13	0	19	0	0
T62	0	8	0	0
T63	0	5	0	0
T69	0	1	0	0
T70	0	1	0	0
T86	0	8	0	0
T87	0	11	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1733748	22821	0	0
T1	449	6	0	0
T2	428	11	0	0
T3	14974	287	0	0
T4	186	1	0	0
T5	309	5	0	0
T6	398	2	0	0
T7	732	3	0	0
T8	23673	467	0	0
T9	6527	61	0	0
T10	16558	202	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1733748	1054	0	0
T2	428	10	0	0
T3	14974	0	0	0
T4	186	0	0	0
T5	309	0	0	0
T6	398	0	0	0
T7	732	0	0	0
T8	23673	13	0	0
T9	6527	0	0	0
T10	16558	22	0	0
T11	460	0	0	0
T12	0	1	0	0
T13	0	23	0	0
T23	0	1	0	0
T62	0	8	0	0
T63	0	7	0	0
T86	0	7	0	0
T87	0	12	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1733748	22821	0	0
T1	449	6	0	0
T2	428	11	0	0
T3	14974	287	0	0
T4	186	1	0	0
T5	309	5	0	0
T6	398	2	0	0
T7	732	3	0	0
T8	23673	467	0	0
T9	6527	61	0	0
T10	16558	202	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1733748	1054	0	0
T2	428	10	0	0
T3	14974	0	0	0
T4	186	0	0	0
T5	309	0	0	0
T6	398	0	0	0
T7	732	0	0	0
T8	23673	13	0	0
T9	6527	0	0	0
T10	16558	22	0	0
T11	460	0	0	0
T12	0	1	0	0
T13	0	23	0	0
T23	0	1	0	0
T62	0	8	0	0
T63	0	7	0	0
T86	0	7	0	0
T87	0	12	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13727933	15056	0	0
T1	3601	4	0	0
T2	3438	10	0	0
T3	116789	190	0	0
T4	1500	0	0	0
T5	2477	4	0	0
T6	3203	0	0	0
T7	5829	0	0	0
T8	184853	315	0	0
T9	51796	36	0	0
T10	130388	145	0	0
T12	0	5	0	0
T13	0	143	0	0
T23	0	5	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13727933	1100	0	0
T2	3438	10	0	0
T3	116789	0	0	0
T4	1500	0	0	0
T5	2477	0	0	0
T6	3203	0	0	0
T7	5829	0	0	0
T8	184853	12	0	0
T9	51796	0	0	0
T10	130388	25	0	0
T11	3693	0	0	0
T12	0	1	0	0
T13	0	23	0	0
T23	0	1	0	0
T62	0	11	0	0
T63	0	8	0	0
T69	0	1	0	0
T70	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13727933	15056	0	0
T1	3601	4	0	0
T2	3438	10	0	0
T3	116789	190	0	0
T4	1500	0	0	0
T5	2477	4	0	0
T6	3203	0	0	0
T7	5829	0	0	0
T8	184853	315	0	0
T9	51796	36	0	0
T10	130388	145	0	0
T12	0	5	0	0
T13	0	143	0	0
T23	0	5	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13727933	1100	0	0
T2	3438	10	0	0
T3	116789	0	0	0
T4	1500	0	0	0
T5	2477	0	0	0
T6	3203	0	0	0
T7	5829	0	0	0
T8	184853	12	0	0
T9	51796	0	0	0
T10	130388	25	0	0
T11	3693	0	0	0
T12	0	1	0	0
T13	0	23	0	0
T23	0	1	0	0
T62	0	11	0	0
T63	0	8	0	0
T69	0	1	0	0
T70	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13727933	15093	0	0
T1	3601	4	0	0
T2	3438	12	0	0
T3	116789	190	0	0
T4	1500	0	0	0
T5	2477	4	0	0
T6	3203	0	0	0
T7	5829	0	0	0
T8	184853	315	0	0
T9	51796	36	0	0
T10	130388	142	0	0
T12	0	4	0	0
T13	0	141	0	0
T23	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13727933	1142	0	0
T2	3438	12	0	0
T3	116789	1	0	0
T4	1500	0	0	0
T5	2477	0	0	0
T6	3203	0	0	0
T7	5829	0	0	0
T8	184853	11	0	0
T9	51796	0	0	0
T10	130388	23	0	0
T11	3693	0	0	0
T13	0	23	0	0
T24	0	1	0	0
T62	0	11	0	0
T63	0	9	0	0
T86	0	9	0	0
T88	0	1	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13727933	15093	0	0
T1	3601	4	0	0
T2	3438	12	0	0
T3	116789	190	0	0
T4	1500	0	0	0
T5	2477	4	0	0
T6	3203	0	0	0
T7	5829	0	0	0
T8	184853	315	0	0
T9	51796	36	0	0
T10	130388	142	0	0
T12	0	4	0	0
T13	0	141	0	0
T23	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13727933	1142	0	0
T2	3438	12	0	0
T3	116789	1	0	0
T4	1500	0	0	0
T5	2477	0	0	0
T6	3203	0	0	0
T7	5829	0	0	0
T8	184853	11	0	0
T9	51796	0	0	0
T10	130388	23	0	0
T11	3693	0	0	0
T13	0	23	0	0
T24	0	1	0	0
T62	0	11	0	0
T63	0	9	0	0
T86	0	9	0	0
T88	0	1	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13727933	15168	0	0
T1	3601	4	0	0
T2	3438	12	0	0
T3	116789	190	0	0
T4	1500	0	0	0
T5	2477	4	0	0
T6	3203	0	0	0
T7	5829	0	0	0
T8	184853	316	0	0
T9	51796	36	0	0
T10	130388	140	0	0
T12	0	4	0	0
T13	0	141	0	0
T23	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13727933	1218	0	0
T2	3438	12	0	0
T3	116789	1	0	0
T4	1500	0	0	0
T5	2477	0	0	0
T6	3203	0	0	0
T7	5829	0	0	0
T8	184853	12	0	0
T9	51796	0	0	0
T10	130388	20	0	0
T11	3693	0	0	0
T13	0	23	0	0
T24	0	1	0	0
T62	0	10	0	0
T63	0	10	0	0
T69	0	1	0	0
T86	0	13	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13727933	15168	0	0
T1	3601	4	0	0
T2	3438	12	0	0
T3	116789	190	0	0
T4	1500	0	0	0
T5	2477	4	0	0
T6	3203	0	0	0
T7	5829	0	0	0
T8	184853	316	0	0
T9	51796	36	0	0
T10	130388	140	0	0
T12	0	4	0	0
T13	0	141	0	0
T23	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13727933	1218	0	0
T2	3438	12	0	0
T3	116789	1	0	0
T4	1500	0	0	0
T5	2477	0	0	0
T6	3203	0	0	0
T7	5829	0	0	0
T8	184853	12	0	0
T9	51796	0	0	0
T10	130388	20	0	0
T11	3693	0	0	0
T13	0	23	0	0
T24	0	1	0	0
T62	0	10	0	0
T63	0	10	0	0
T69	0	1	0	0
T86	0	13	0	0