Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12861151	7005	0	0
alert_regwen_rd_A	12861151	6223	0	0
cpu_regwen_rd_A	12861151	6322	0	0
sw_rst_ctrl_n_0_rd_A	12861151	10961	0	0
sw_rst_ctrl_n_1_rd_A	12861151	10990	0	0
sw_rst_ctrl_n_2_rd_A	12861151	10847	0	0
sw_rst_ctrl_n_3_rd_A	12861151	10789	0	0
sw_rst_ctrl_n_4_rd_A	12861151	10848	0	0
sw_rst_ctrl_n_5_rd_A	12861151	10758	0	0
sw_rst_ctrl_n_6_rd_A	12861151	10816	0	0
sw_rst_ctrl_n_7_rd_A	12861151	11071	0	0
sw_rst_regwen_0_rd_A	12861151	6344	0	0
sw_rst_regwen_1_rd_A	12861151	6446	0	0
sw_rst_regwen_2_rd_A	12861151	6530	0	0
sw_rst_regwen_3_rd_A	12861151	6575	0	0
sw_rst_regwen_4_rd_A	12861151	6598	0	0
sw_rst_regwen_5_rd_A	12861151	6523	0	0
sw_rst_regwen_6_rd_A	12861151	6485	0	0
sw_rst_regwen_7_rd_A	12861151	6609	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12861151	7005	0	0
T67	10679	2	0	0
T68	11285	1	0	0
T71	15401	641	0	0
T72	3709	263	0	0
T73	5088	69	0	0
T89	12138	527	0	0
T90	2920	306	0	0
T91	8269	337	0	0
T92	10762	1	0	0
T94	21857	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12861151	6223	0	0
T9	46117	107	0	0
T10	116075	0	0	0
T11	3554	0	0	0
T12	4459	0	0	0
T13	66577	0	0	0
T22	1287	0	0	0
T23	2475	0	0	0
T24	5722	0	0	0
T40	0	67	0	0
T60	0	92	0	0
T78	1788	0	0	0
T83	30577	0	0	0
T100	0	61	0	0
T102	0	198	0	0
T103	0	565	0	0
T104	0	53	0	0
T119	0	55	0	0
T120	0	123	0	0
T121	0	58	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12861151	6322	0	0
T9	46117	94	0	0
T10	116075	0	0	0
T11	3554	0	0	0
T12	4459	0	0	0
T13	66577	0	0	0
T22	1287	0	0	0
T23	2475	0	0	0
T24	5722	0	0	0
T40	0	65	0	0
T60	0	94	0	0
T78	1788	0	0	0
T83	30577	0	0	0
T100	0	61	0	0
T102	0	160	0	0
T103	0	573	0	0
T104	0	66	0	0
T119	0	54	0	0
T120	0	148	0	0
T121	0	66	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12861151	10961	0	0
T9	46117	82	0	0
T10	116075	0	0	0
T11	3554	0	0	0
T12	4459	0	0	0
T13	66577	0	0	0
T22	1287	0	0	0
T23	2475	0	0	0
T24	5722	17	0	0
T40	0	63	0	0
T41	0	69	0	0
T58	0	12	0	0
T60	0	64	0	0
T78	1788	0	0	0
T83	30577	0	0	0
T86	0	178	0	0
T87	0	213	0	0
T122	0	19	0	0
T123	0	14	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12861151	10990	0	0
T9	46117	96	0	0
T10	116075	0	0	0
T11	3554	0	0	0
T12	4459	0	0	0
T13	66577	0	0	0
T22	1287	0	0	0
T23	2475	0	0	0
T24	5722	16	0	0
T40	0	57	0	0
T41	0	51	0	0
T58	0	20	0	0
T60	0	47	0	0
T78	1788	0	0	0
T83	30577	0	0	0
T86	0	153	0	0
T87	0	250	0	0
T122	0	26	0	0
T123	0	14	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12861151	10847	0	0
T9	46117	142	0	0
T10	116075	0	0	0
T11	3554	0	0	0
T12	4459	0	0	0
T13	66577	0	0	0
T22	1287	0	0	0
T23	2475	0	0	0
T24	5722	9	0	0
T40	0	49	0	0
T41	0	50	0	0
T58	0	7	0	0
T60	0	79	0	0
T78	1788	0	0	0
T83	30577	0	0	0
T86	0	174	0	0
T87	0	210	0	0
T122	0	13	0	0
T123	0	3	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12861151	10789	0	0
T9	46117	85	0	0
T10	116075	0	0	0
T11	3554	0	0	0
T12	4459	0	0	0
T13	66577	0	0	0
T22	1287	0	0	0
T23	2475	0	0	0
T24	5722	5	0	0
T40	0	34	0	0
T41	0	65	0	0
T58	0	9	0	0
T60	0	82	0	0
T78	1788	0	0	0
T83	30577	0	0	0
T86	0	184	0	0
T87	0	233	0	0
T122	0	11	0	0
T123	0	16	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12861151	10848	0	0
T9	46117	97	0	0
T10	116075	0	0	0
T11	3554	0	0	0
T12	4459	0	0	0
T13	66577	0	0	0
T22	1287	0	0	0
T23	2475	0	0	0
T24	5722	7	0	0
T40	0	54	0	0
T41	0	48	0	0
T58	0	18	0	0
T60	0	60	0	0
T78	1788	0	0	0
T83	30577	0	0	0
T86	0	162	0	0
T87	0	215	0	0
T122	0	24	0	0
T123	0	10	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12861151	10758	0	0
T9	46117	93	0	0
T10	116075	0	0	0
T11	3554	0	0	0
T12	4459	0	0	0
T13	66577	0	0	0
T22	1287	0	0	0
T23	2475	0	0	0
T24	5722	5	0	0
T40	0	74	0	0
T41	0	57	0	0
T58	0	8	0	0
T60	0	87	0	0
T78	1788	0	0	0
T83	30577	0	0	0
T86	0	169	0	0
T87	0	220	0	0
T122	0	11	0	0
T123	0	7	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12861151	10816	0	0
T9	46117	92	0	0
T10	116075	0	0	0
T11	3554	0	0	0
T12	4459	0	0	0
T13	66577	0	0	0
T22	1287	0	0	0
T23	2475	0	0	0
T24	5722	13	0	0
T40	0	65	0	0
T41	0	67	0	0
T58	0	12	0	0
T60	0	86	0	0
T78	1788	0	0	0
T83	30577	0	0	0
T86	0	154	0	0
T87	0	198	0	0
T122	0	10	0	0
T123	0	18	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12861151	11071	0	0
T9	46117	99	0	0
T10	116075	0	0	0
T11	3554	0	0	0
T12	4459	0	0	0
T13	66577	0	0	0
T22	1287	0	0	0
T23	2475	0	0	0
T24	5722	7	0	0
T40	0	65	0	0
T41	0	68	0	0
T58	0	16	0	0
T60	0	71	0	0
T78	1788	0	0	0
T83	30577	0	0	0
T86	0	183	0	0
T87	0	204	0	0
T122	0	11	0	0
T123	0	10	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12861151	6344	0	0
T9	46117	78	0	0
T10	116075	0	0	0
T11	3554	0	0	0
T12	4459	0	0	0
T13	66577	0	0	0
T22	1287	0	0	0
T23	2475	0	0	0
T24	5722	2	0	0
T40	0	88	0	0
T58	0	2	0	0
T60	0	71	0	0
T78	1788	0	0	0
T83	30577	0	0	0
T86	0	25	0	0
T87	0	41	0	0
T104	0	59	0	0
T122	0	6	0	0
T123	0	2	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12861151	6446	0	0
T9	46117	92	0	0
T10	116075	0	0	0
T11	3554	0	0	0
T12	4459	0	0	0
T13	66577	0	0	0
T22	1287	0	0	0
T23	2475	0	0	0
T24	5722	5	0	0
T40	0	64	0	0
T58	0	10	0	0
T60	0	88	0	0
T78	1788	0	0	0
T83	30577	0	0	0
T86	0	25	0	0
T87	0	30	0	0
T104	0	42	0	0
T122	0	12	0	0
T123	0	3	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12861151	6530	0	0
T9	46117	93	0	0
T10	116075	0	0	0
T11	3554	0	0	0
T12	4459	0	0	0
T13	66577	0	0	0
T22	1287	0	0	0
T23	2475	0	0	0
T24	5722	2	0	0
T40	0	68	0	0
T58	0	11	0	0
T60	0	57	0	0
T78	1788	0	0	0
T83	30577	0	0	0
T86	0	25	0	0
T87	0	30	0	0
T104	0	31	0	0
T122	0	3	0	0
T123	0	2	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12861151	6575	0	0
T9	46117	95	0	0
T10	116075	0	0	0
T11	3554	0	0	0
T12	4459	0	0	0
T13	66577	0	0	0
T22	1287	0	0	0
T23	2475	0	0	0
T24	5722	6	0	0
T40	0	50	0	0
T58	0	8	0	0
T60	0	105	0	0
T78	1788	0	0	0
T83	30577	0	0	0
T86	0	33	0	0
T87	0	36	0	0
T104	0	46	0	0
T122	0	6	0	0
T123	0	3	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12861151	6598	0	0
T9	46117	96	0	0
T10	116075	0	0	0
T11	3554	0	0	0
T12	4459	0	0	0
T13	66577	0	0	0
T22	1287	0	0	0
T23	2475	0	0	0
T24	5722	12	0	0
T40	0	75	0	0
T58	0	6	0	0
T60	0	63	0	0
T78	1788	0	0	0
T83	30577	0	0	0
T86	0	32	0	0
T87	0	34	0	0
T104	0	46	0	0
T122	0	4	0	0
T123	0	5	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12861151	6523	0	0
T9	46117	97	0	0
T10	116075	0	0	0
T11	3554	0	0	0
T12	4459	0	0	0
T13	66577	0	0	0
T22	1287	0	0	0
T23	2475	0	0	0
T24	5722	4	0	0
T40	0	59	0	0
T58	0	8	0	0
T60	0	84	0	0
T78	1788	0	0	0
T83	30577	0	0	0
T86	0	22	0	0
T87	0	24	0	0
T104	0	48	0	0
T122	0	2	0	0
T123	0	1	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12861151	6485	0	0
T9	46117	101	0	0
T10	116075	0	0	0
T11	3554	0	0	0
T12	4459	0	0	0
T13	66577	0	0	0
T22	1287	0	0	0
T23	2475	0	0	0
T24	5722	16	0	0
T40	0	65	0	0
T58	0	5	0	0
T60	0	69	0	0
T78	1788	0	0	0
T83	30577	0	0	0
T86	0	40	0	0
T87	0	33	0	0
T104	0	47	0	0
T122	0	13	0	0
T123	0	6	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12861151	6609	0	0
T9	46117	64	0	0
T10	116075	0	0	0
T11	3554	0	0	0
T12	4459	0	0	0
T13	66577	0	0	0
T22	1287	0	0	0
T23	2475	0	0	0
T24	5722	1	0	0
T40	0	63	0	0
T58	0	6	0	0
T60	0	75	0	0
T78	1788	0	0	0
T83	30577	0	0	0
T86	0	30	0	0
T87	0	43	0	0
T104	0	60	0	0
T122	0	6	0	0
T123	0	7	0	0