Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	592399	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

356538

1

T1

1087

T2

6

T3

1084

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	505482	1			T1	1500		T3	1500		T4	99
values[0x0]	221209	1			T1	854		T2	10		T3	855
values[0x1]	222246	1			T1	846		T2	16		T3	845

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	497089	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

451848

1

T1

1441

T2

10

T3

1427

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	2812	1			T1	7		T7	3		T10	1
valid_sources[0x01]	3494	1			T1	13		T7	4		T9	1
valid_sources[0x02]	3102	1			T1	19		T9	1		T11	5
valid_sources[0x03]	3974	1			T1	8		T7	2		T11	8
valid_sources[0x04]	3471	1			T1	5		T7	3		T9	2
valid_sources[0x05]	2527	1			T1	8		T7	1		T11	10
valid_sources[0x06]	3911	1			T1	8		T7	1		T9	1
valid_sources[0x07]	4139	1			T1	5		T10	1		T11	26
valid_sources[0x08]	3216	1			T1	8		T7	2		T9	1
valid_sources[0x09]	3704	1			T1	14		T7	1		T9	1
valid_sources[0x0a]	3365	1			T1	10		T9	1		T10	1
valid_sources[0x0b]	2951	1			T1	14		T7	2		T10	2
valid_sources[0x0c]	2857	1			T1	5		T9	1		T10	2
valid_sources[0x0d]	3027	1			T1	4		T7	3		T9	6
valid_sources[0x0e]	2710	1			T1	7		T7	3		T10	3
valid_sources[0x0f]	3322	1			T1	18		T4	5		T5	1
valid_sources[0x10]	4966	1			T1	39		T7	2		T10	1
valid_sources[0x11]	6288	1			T1	13		T7	3		T9	1
valid_sources[0x12]	3307	1			T1	8		T10	1		T11	8
valid_sources[0x13]	3247	1			T1	6		T7	1		T9	1
valid_sources[0x14]	3643	1			T1	15		T11	11		T13	2
valid_sources[0x15]	3094	1			T1	6		T4	1		T7	3
valid_sources[0x16]	2955	1			T1	12		T7	3		T9	5
valid_sources[0x17]	3463	1			T1	14		T7	3		T9	1
valid_sources[0x18]	6669	1			T1	14		T10	2		T11	17
valid_sources[0x19]	3667	1			T1	14		T7	4		T9	1
valid_sources[0x1a]	3622	1			T1	31		T10	1		T11	9
valid_sources[0x1b]	3396	1			T1	10		T7	1		T11	11
valid_sources[0x1c]	3316	1			T1	15		T4	15		T7	3
valid_sources[0x1d]	2852	1			T1	6		T7	4		T10	3
valid_sources[0x1e]	3088	1			T1	24		T7	2		T9	2
valid_sources[0x1f]	3520	1			T1	7		T4	2		T7	3
valid_sources[0x20]	2739	1			T1	16		T7	1		T10	2
valid_sources[0x21]	3393	1			T1	12		T9	5		T10	3
valid_sources[0x22]	3382	1			T1	15		T7	1		T9	1
valid_sources[0x23]	3918	1			T1	15		T2	4		T7	1
valid_sources[0x24]	7372	1			T1	11		T5	1		T11	14
valid_sources[0x25]	7460	1			T1	10		T7	1		T9	3
valid_sources[0x26]	3761	1			T1	9		T9	2		T10	1
valid_sources[0x27]	3339	1			T1	14		T7	1		T9	3
valid_sources[0x28]	3751	1			T1	10		T7	1		T9	1
valid_sources[0x29]	2911	1			T1	15		T7	2		T9	1
valid_sources[0x2a]	6489	1			T1	7		T7	1		T9	2
valid_sources[0x2b]	3849	1			T1	12		T7	2		T10	3
valid_sources[0x2c]	3643	1			T1	16		T5	3		T9	2
valid_sources[0x2d]	3117	1			T1	12		T7	2		T9	2
valid_sources[0x2e]	2958	1			T1	18		T11	8		T43	4
valid_sources[0x2f]	3918	1			T1	9		T7	3		T10	1
valid_sources[0x30]	3013	1			T1	10		T10	2		T11	10
valid_sources[0x31]	3309	1			T1	10		T7	3		T9	1
valid_sources[0x32]	3681	1			T1	11		T9	5		T10	3
valid_sources[0x33]	3821	1			T1	7		T10	1		T11	16
valid_sources[0x34]	3892	1			T1	13		T9	8		T10	3
valid_sources[0x35]	3628	1			T1	14		T7	1		T10	4
valid_sources[0x36]	3219	1			T1	8		T7	1		T9	2
valid_sources[0x37]	3523	1			T1	10		T4	8		T7	1
valid_sources[0x38]	3043	1			T1	19		T7	1		T9	2
valid_sources[0x39]	6364	1			T1	9		T10	2		T11	14
valid_sources[0x3a]	3886	1			T1	5		T6	952		T7	1
valid_sources[0x3b]	3481	1			T1	19		T11	12		T43	3
valid_sources[0x3c]	8045	1			T1	8		T7	1		T8	1
valid_sources[0x3d]	3255	1			T1	11		T7	4		T9	2
valid_sources[0x3e]	3352	1			T1	16		T7	1		T9	1
valid_sources[0x3f]	2875	1			T1	7		T7	2		T10	5
valid_sources[0x40]	2889	1			T1	22		T11	22		T43	3
valid_sources[0x41]	3988	1			T1	14		T7	3		T9	1
valid_sources[0x42]	3815	1			T1	14		T7	2		T9	1
valid_sources[0x43]	3046	1			T1	8		T7	1		T10	1
valid_sources[0x44]	3434	1			T1	12		T7	1		T9	3
valid_sources[0x45]	3033	1			T1	25		T4	36		T7	1
valid_sources[0x46]	3269	1			T1	6		T9	1		T11	13
valid_sources[0x47]	3660	1			T1	11		T7	2		T9	2
valid_sources[0x48]	3347	1			T1	8		T7	5		T10	3
valid_sources[0x49]	3865	1			T1	17		T10	2		T11	15
valid_sources[0x4a]	3488	1			T1	14		T7	2		T9	1
valid_sources[0x4b]	6348	1			T1	14		T7	3		T11	13
valid_sources[0x4c]	3217	1			T1	14		T7	4		T10	5
valid_sources[0x4d]	3887	1			T1	10		T7	1		T9	2
valid_sources[0x4e]	2890	1			T1	6		T7	2		T9	3
valid_sources[0x4f]	3676	1			T1	11		T7	6		T10	2
valid_sources[0x50]	2889	1			T1	13		T7	4		T9	1
valid_sources[0x51]	2871	1			T1	22		T9	2		T10	1
valid_sources[0x52]	3933	1			T1	11		T4	55		T7	4
valid_sources[0x53]	3722	1			T1	11		T7	1		T10	4
valid_sources[0x54]	3842	1			T1	8		T9	3		T10	1
valid_sources[0x55]	3969	1			T1	13		T11	10		T43	4
valid_sources[0x56]	3621	1			T1	11		T9	3		T11	10
valid_sources[0x57]	2802	1			T1	23		T10	1		T11	10
valid_sources[0x58]	3850	1			T1	9		T4	9		T7	1
valid_sources[0x59]	3677	1			T1	11		T7	2		T11	18
valid_sources[0x5a]	4093	1			T1	12		T7	1		T9	2
valid_sources[0x5b]	3069	1			T1	15		T7	6		T10	1
valid_sources[0x5c]	3023	1			T1	5		T7	3		T9	2
valid_sources[0x5d]	6502	1			T1	16		T9	1		T10	3
valid_sources[0x5e]	3243	1			T1	3		T5	1		T9	5
valid_sources[0x5f]	4482	1			T1	10		T7	1		T9	1
valid_sources[0x60]	3476	1			T1	15		T7	1		T8	3
valid_sources[0x61]	3741	1			T1	16		T7	4		T11	14
valid_sources[0x62]	3725	1			T1	8		T7	3		T9	2
valid_sources[0x63]	2778	1			T1	11		T9	3		T11	6
valid_sources[0x64]	2802	1			T1	12		T7	3		T9	2
valid_sources[0x65]	3908	1			T1	8		T9	4		T10	2
valid_sources[0x66]	2916	1			T1	16		T9	1		T11	13
valid_sources[0x67]	2909	1			T1	14		T10	1		T11	13
valid_sources[0x68]	3067	1			T1	11		T2	8		T7	1
valid_sources[0x69]	3227	1			T1	21		T7	1		T9	1
valid_sources[0x6a]	3099	1			T1	15		T7	3		T9	3
valid_sources[0x6b]	3419	1			T1	7		T10	1		T11	12
valid_sources[0x6c]	4268	1			T1	13		T7	1		T10	3
valid_sources[0x6d]	6878	1			T1	28		T9	3		T11	14
valid_sources[0x6e]	3042	1			T1	17		T7	1		T11	20
valid_sources[0x6f]	2713	1			T1	8		T4	10		T7	1
valid_sources[0x70]	3098	1			T1	8		T7	4		T9	2
valid_sources[0x71]	3428	1			T1	11		T7	3		T9	1
valid_sources[0x72]	3433	1			T1	14		T5	1		T7	1
valid_sources[0x73]	4148	1			T1	11		T7	1		T10	2
valid_sources[0x74]	3496	1			T1	18		T7	1		T9	1
valid_sources[0x75]	3832	1			T1	16		T7	1		T9	2
valid_sources[0x76]	5294	1			T1	11		T5	2		T7	1
valid_sources[0x77]	5217	1			T1	14		T9	8		T10	2
valid_sources[0x78]	4584	1			T1	14		T2	4		T7	4
valid_sources[0x79]	3390	1			T1	22		T7	1		T9	6
valid_sources[0x7a]	3461	1			T1	16		T7	1		T9	1
valid_sources[0x7b]	5864	1			T1	15		T4	1		T8	1
valid_sources[0x7c]	3049	1			T1	6		T10	1		T11	17
valid_sources[0x7d]	3235	1			T1	9		T7	5		T9	1
valid_sources[0x7e]	2939	1			T1	18		T11	13		T43	6
valid_sources[0x7f]	2830	1			T1	14		T4	9		T7	2
valid_sources[0x80]	3093	1			T1	15		T7	2		T9	5

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

237355

1

T1

663

T3

673

T4

37

values[0x0]

all_enables

biggest_size

77752

1

T1

276

T2

5

T3

282

values[0x1]

all_enables

biggest_size

41431

1

T1

148

T2

1

T3

129