Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T7,T9
0	1	Covered	T4,T14,T55
1	0	Covered	T9,T10,T14

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T4,T7,T9
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	54221454	8966	0	0
CascadeEffAonToRstPorAboveRise_A	54221454	8966	0	0
CascadeEffAonToRstPorIoAboveFall_A	52050862	8966	0	0
CascadeEffAonToRstPorIoAboveRise_A	52050862	8966	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26026326	8966	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26026326	8966	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13012794	8966	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13012794	8966	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26026242	8966	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26026242	8966	0	0
CascadeLcToLcAboveFall_A	54221454	21635	0	0
CascadeLcToLcAboveRise_A	54221454	21635	0	0
CascadeLcToLcAonAboveFall_A	1642123	21635	0	0
CascadeLcToLcAonAboveRise_A	1642123	21635	0	0
CascadeLcToLcShadowedAboveFall_A	54221454	21635	0	0
CascadeLcToLcShadowedAboveRise_A	54221454	21635	0	0
CascadePorToAonAboveFall_A	1642123	7228	0	0
CascadeSysToSysAboveFall_A	54221454	21635	0	0
CascadeSysToSysAboveRise_A	54221454	21635	0	0
ScanRstToAonRise_A	1642123	206	0	0
StablePorToAonRise_A	1642123	8966	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11577982	21635	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11577982	21635	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11577982	21635	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11577982	21635	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13012794	21635	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13012794	21635	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11577982	21635	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11577982	21635	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11577982	21635	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11577982	21635	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54221454	8966	0	0
T1	189636	27	0	0
T2	8054	1	0	0
T3	187970	27	0	0
T4	17489	2	0	0
T5	165045	541	0	0
T6	13572	1	0	0
T7	25083	2	0	0
T8	7952	1	0	0
T9	25581	2	0	0
T10	25489	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54221454	8966	0	0
T1	189636	27	0	0
T2	8054	1	0	0
T3	187970	27	0	0
T4	17489	2	0	0
T5	165045	541	0	0
T6	13572	1	0	0
T7	25083	2	0	0
T8	7952	1	0	0
T9	25581	2	0	0
T10	25489	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52050862	8966	0	0
T1	182048	27	0	0
T2	7732	1	0	0
T3	180454	27	0	0
T4	16787	2	0	0
T5	158423	541	0	0
T6	13027	1	0	0
T7	24076	2	0	0
T8	7634	1	0	0
T9	24562	2	0	0
T10	24465	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52050862	8966	0	0
T1	182048	27	0	0
T2	7732	1	0	0
T3	180454	27	0	0
T4	16787	2	0	0
T5	158423	541	0	0
T6	13027	1	0	0
T7	24076	2	0	0
T8	7634	1	0	0
T9	24562	2	0	0
T10	24465	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26026326	8966	0	0
T1	91032	27	0	0
T2	3866	1	0	0
T3	90231	27	0	0
T4	8395	2	0	0
T5	792228	541	0	0
T6	6515	1	0	0
T7	12038	2	0	0
T8	3815	1	0	0
T9	12282	2	0	0
T10	12231	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26026326	8966	0	0
T1	91032	27	0	0
T2	3866	1	0	0
T3	90231	27	0	0
T4	8395	2	0	0
T5	792228	541	0	0
T6	6515	1	0	0
T7	12038	2	0	0
T8	3815	1	0	0
T9	12282	2	0	0
T10	12231	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012794	8966	0	0
T1	45511	27	0	0
T2	1933	1	0	0
T3	45119	27	0	0
T4	4196	2	0	0
T5	396150	541	0	0
T6	3257	1	0	0
T7	6019	2	0	0
T8	1907	1	0	0
T9	6140	2	0	0
T10	6115	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012794	8966	0	0
T1	45511	27	0	0
T2	1933	1	0	0
T3	45119	27	0	0
T4	4196	2	0	0
T5	396150	541	0	0
T6	3257	1	0	0
T7	6019	2	0	0
T8	1907	1	0	0
T9	6140	2	0	0
T10	6115	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26026242	8966	0	0
T1	91040	27	0	0
T2	3865	1	0	0
T3	90219	27	0	0
T4	8395	2	0	0
T5	792225	541	0	0
T6	6514	1	0	0
T7	12039	2	0	0
T8	3815	1	0	0
T9	12280	2	0	0
T10	12231	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26026242	8966	0	0
T1	91040	27	0	0
T2	3865	1	0	0
T3	90219	27	0	0
T4	8395	2	0	0
T5	792225	541	0	0
T6	6514	1	0	0
T7	12039	2	0	0
T8	3815	1	0	0
T9	12280	2	0	0
T10	12231	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54221454	21635	0	0
T1	189636	102	0	0
T2	8054	1	0	0
T3	187970	102	0	0
T4	17489	6	0	0
T5	165045	541	0	0
T6	13572	1	0	0
T7	25083	6	0	0
T8	7952	1	0	0
T9	25581	6	0	0
T10	25489	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54221454	21635	0	0
T1	189636	102	0	0
T2	8054	1	0	0
T3	187970	102	0	0
T4	17489	6	0	0
T5	165045	541	0	0
T6	13572	1	0	0
T7	25083	6	0	0
T8	7952	1	0	0
T9	25581	6	0	0
T10	25489	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1642123	21635	0	0
T1	5704	102	0	0
T2	241	1	0	0
T3	5653	102	0	0
T4	523	6	0	0
T5	49761	541	0	0
T6	407	1	0	0
T7	750	6	0	0
T8	236	1	0	0
T9	767	6	0	0
T10	763	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1642123	21635	0	0
T1	5704	102	0	0
T2	241	1	0	0
T3	5653	102	0	0
T4	523	6	0	0
T5	49761	541	0	0
T6	407	1	0	0
T7	750	6	0	0
T8	236	1	0	0
T9	767	6	0	0
T10	763	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54221454	21635	0	0
T1	189636	102	0	0
T2	8054	1	0	0
T3	187970	102	0	0
T4	17489	6	0	0
T5	165045	541	0	0
T6	13572	1	0	0
T7	25083	6	0	0
T8	7952	1	0	0
T9	25581	6	0	0
T10	25489	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54221454	21635	0	0
T1	189636	102	0	0
T2	8054	1	0	0
T3	187970	102	0	0
T4	17489	6	0	0
T5	165045	541	0	0
T6	13572	1	0	0
T7	25083	6	0	0
T8	7952	1	0	0
T9	25581	6	0	0
T10	25489	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1642123	7228	0	0
T1	5704	27	0	0
T2	241	1	0	0
T3	5653	27	0	0
T4	523	1	0	0
T5	49761	541	0	0
T6	407	1	0	0
T7	750	1	0	0
T8	236	1	0	0
T9	767	1	0	0
T10	763	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54221454	21635	0	0
T1	189636	102	0	0
T2	8054	1	0	0
T3	187970	102	0	0
T4	17489	6	0	0
T5	165045	541	0	0
T6	13572	1	0	0
T7	25083	6	0	0
T8	7952	1	0	0
T9	25581	6	0	0
T10	25489	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54221454	21635	0	0
T1	189636	102	0	0
T2	8054	1	0	0
T3	187970	102	0	0
T4	17489	6	0	0
T5	165045	541	0	0
T6	13572	1	0	0
T7	25083	6	0	0
T8	7952	1	0	0
T9	25581	6	0	0
T10	25489	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1642123	206	0	0
T16	312	0	0	0
T17	507	0	0	0
T18	577	0	0	0
T26	551	1	0	0
T27	238	0	0	0
T28	731	0	0	0
T29	17368	2	0	0
T30	7105	0	0	0
T31	730	0	0	0
T79	2243	1	0	0
T93	0	1	0	0
T94	0	2	0	0
T95	0	1	0	0
T97	0	11	0	0
T98	0	1	0	0
T99	0	3	0	0
T132	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1642123	8966	0	0
T1	5704	27	0	0
T2	241	1	0	0
T3	5653	27	0	0
T4	523	2	0	0
T5	49761	541	0	0
T6	407	1	0	0
T7	750	2	0	0
T8	236	1	0	0
T9	767	2	0	0
T10	763	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11577982	21635	0	0
T1	42332	102	0	0
T2	1914	1	0	0
T3	42073	102	0	0
T4	4003	6	0	0
T5	372126	541	0	0
T6	3214	1	0	0
T7	5777	6	0	0
T8	1817	1	0	0
T9	5849	6	0	0
T10	5776	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11577982	21635	0	0
T1	42332	102	0	0
T2	1914	1	0	0
T3	42073	102	0	0
T4	4003	6	0	0
T5	372126	541	0	0
T6	3214	1	0	0
T7	5777	6	0	0
T8	1817	1	0	0
T9	5849	6	0	0
T10	5776	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11577982	21635	0	0
T1	42332	102	0	0
T2	1914	1	0	0
T3	42073	102	0	0
T4	4003	6	0	0
T5	372126	541	0	0
T6	3214	1	0	0
T7	5777	6	0	0
T8	1817	1	0	0
T9	5849	6	0	0
T10	5776	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11577982	21635	0	0
T1	42332	102	0	0
T2	1914	1	0	0
T3	42073	102	0	0
T4	4003	6	0	0
T5	372126	541	0	0
T6	3214	1	0	0
T7	5777	6	0	0
T8	1817	1	0	0
T9	5849	6	0	0
T10	5776	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012794	21635	0	0
T1	45511	102	0	0
T2	1933	1	0	0
T3	45119	102	0	0
T4	4196	6	0	0
T5	396150	541	0	0
T6	3257	1	0	0
T7	6019	6	0	0
T8	1907	1	0	0
T9	6140	6	0	0
T10	6115	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012794	21635	0	0
T1	45511	102	0	0
T2	1933	1	0	0
T3	45119	102	0	0
T4	4196	6	0	0
T5	396150	541	0	0
T6	3257	1	0	0
T7	6019	6	0	0
T8	1907	1	0	0
T9	6140	6	0	0
T10	6115	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11577982	21635	0	0
T1	42332	102	0	0
T2	1914	1	0	0
T3	42073	102	0	0
T4	4003	6	0	0
T5	372126	541	0	0
T6	3214	1	0	0
T7	5777	6	0	0
T8	1817	1	0	0
T9	5849	6	0	0
T10	5776	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11577982	21635	0	0
T1	42332	102	0	0
T2	1914	1	0	0
T3	42073	102	0	0
T4	4003	6	0	0
T5	372126	541	0	0
T6	3214	1	0	0
T7	5777	6	0	0
T8	1817	1	0	0
T9	5849	6	0	0
T10	5776	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11577982	21635	0	0
T1	42332	102	0	0
T2	1914	1	0	0
T3	42073	102	0	0
T4	4003	6	0	0
T5	372126	541	0	0
T6	3214	1	0	0
T7	5777	6	0	0
T8	1817	1	0	0
T9	5849	6	0	0
T10	5776	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11577982	21635	0	0
T1	42332	102	0	0
T2	1914	1	0	0
T3	42073	102	0	0
T4	4003	6	0	0
T5	372126	541	0	0
T6	3214	1	0	0
T7	5777	6	0	0
T8	1817	1	0	0
T9	5849	6	0	0
T10	5776	6	0	0