Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T10
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T12
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T12,T43
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T43,T45
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T7,T10
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T43,T45
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T43,T45
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T6,T43,T45
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13012794	13509	0	0
gen_assertions[0].RstEnOn_A	13012794	1032	0	0
gen_assertions[0].RstNOff_A	13012794	13509	0	0
gen_assertions[0].RstNOn_A	13012794	1032	0	0
gen_assertions[1].RstEnOff_A	52050862	12307	0	0
gen_assertions[1].RstEnOn_A	52050862	1056	0	0
gen_assertions[1].RstNOff_A	52050862	12307	0	0
gen_assertions[1].RstNOn_A	52050862	1056	0	0
gen_assertions[2].RstEnOff_A	26026326	12340	0	0
gen_assertions[2].RstEnOn_A	26026326	1004	0	0
gen_assertions[2].RstNOff_A	26026326	12340	0	0
gen_assertions[2].RstNOn_A	26026326	1004	0	0
gen_assertions[3].RstEnOff_A	26026242	12361	0	0
gen_assertions[3].RstEnOn_A	26026242	1009	0	0
gen_assertions[3].RstNOff_A	26026242	12361	0	0
gen_assertions[3].RstNOn_A	26026242	1009	0	0
gen_assertions[4].RstEnOff_A	1642123	21523	0	0
gen_assertions[4].RstEnOn_A	1642123	1095	0	0
gen_assertions[4].RstNOff_A	1642123	21523	0	0
gen_assertions[4].RstNOn_A	1642123	1095	0	0
gen_assertions[5].RstEnOff_A	13012794	13754	0	0
gen_assertions[5].RstEnOn_A	13012794	1123	0	0
gen_assertions[5].RstNOff_A	13012794	13754	0	0
gen_assertions[5].RstNOn_A	13012794	1123	0	0
gen_assertions[6].RstEnOff_A	13012794	13789	0	0
gen_assertions[6].RstEnOn_A	13012794	1154	0	0
gen_assertions[6].RstNOff_A	13012794	13789	0	0
gen_assertions[6].RstNOn_A	13012794	1154	0	0
gen_assertions[7].RstEnOff_A	13012794	13878	0	0
gen_assertions[7].RstEnOn_A	13012794	1245	0	0
gen_assertions[7].RstNOff_A	13012794	13878	0	0
gen_assertions[7].RstNOn_A	13012794	1245	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012794	13509	0	0
T1	45511	75	0	0
T2	1933	0	0	0
T3	45119	75	0	0
T4	4196	4	0	0
T5	396150	0	0	0
T6	3257	4	0	0
T7	6019	5	0	0
T8	1907	0	0	0
T9	6140	4	0	0
T10	6115	5	0	0
T11	0	75	0	0
T12	0	20	0	0
T13	0	2	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012794	1032	0	0
T6	3257	4	0	0
T7	6019	1	0	0
T8	1907	0	0	0
T9	6140	0	0	0
T10	6115	1	0	0
T11	51620	0	0	0
T12	4104	12	0	0
T13	1712	0	0	0
T14	0	12	0	0
T42	1945	0	0	0
T43	3118	3	0	0
T45	0	2	0	0
T56	0	2	0	0
T59	0	6	0	0
T60	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012794	13509	0	0
T1	45511	75	0	0
T2	1933	0	0	0
T3	45119	75	0	0
T4	4196	4	0	0
T5	396150	0	0	0
T6	3257	4	0	0
T7	6019	5	0	0
T8	1907	0	0	0
T9	6140	4	0	0
T10	6115	5	0	0
T11	0	75	0	0
T12	0	20	0	0
T13	0	2	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012794	1032	0	0
T6	3257	4	0	0
T7	6019	1	0	0
T8	1907	0	0	0
T9	6140	0	0	0
T10	6115	1	0	0
T11	51620	0	0	0
T12	4104	12	0	0
T13	1712	0	0	0
T14	0	12	0	0
T42	1945	0	0	0
T43	3118	3	0	0
T45	0	2	0	0
T56	0	2	0	0
T59	0	6	0	0
T60	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52050862	12307	0	0
T1	182048	68	0	0
T2	7732	0	0	0
T3	180454	70	0	0
T4	16787	4	0	0
T5	158423	0	0	0
T6	13027	5	0	0
T7	24076	3	0	0
T8	7634	0	0	0
T9	24562	4	0	0
T10	24465	4	0	0
T11	0	66	0	0
T12	0	17	0	0
T13	0	1	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52050862	1056	0	0
T6	13027	5	0	0
T7	24076	1	0	0
T8	7634	0	0	0
T9	24562	0	0	0
T10	24465	0	0	0
T11	206421	0	0	0
T12	16417	7	0	0
T13	6850	0	0	0
T14	0	10	0	0
T29	0	5	0	0
T42	7785	0	0	0
T43	12477	5	0	0
T45	0	3	0	0
T54	0	2	0	0
T56	0	4	0	0
T59	0	7	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52050862	12307	0	0
T1	182048	68	0	0
T2	7732	0	0	0
T3	180454	70	0	0
T4	16787	4	0	0
T5	158423	0	0	0
T6	13027	5	0	0
T7	24076	3	0	0
T8	7634	0	0	0
T9	24562	4	0	0
T10	24465	4	0	0
T11	0	66	0	0
T12	0	17	0	0
T13	0	1	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52050862	1056	0	0
T6	13027	5	0	0
T7	24076	1	0	0
T8	7634	0	0	0
T9	24562	0	0	0
T10	24465	0	0	0
T11	206421	0	0	0
T12	16417	7	0	0
T13	6850	0	0	0
T14	0	10	0	0
T29	0	5	0	0
T42	7785	0	0	0
T43	12477	5	0	0
T45	0	3	0	0
T54	0	2	0	0
T56	0	4	0	0
T59	0	7	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26026326	12340	0	0
T1	91032	68	0	0
T2	3866	0	0	0
T3	90231	70	0	0
T4	8395	4	0	0
T5	792228	0	0	0
T6	6515	7	0	0
T7	12038	2	0	0
T8	3815	0	0	0
T9	12282	4	0	0
T10	12231	4	0	0
T11	0	66	0	0
T12	0	17	0	0
T13	0	1	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26026326	1004	0	0
T6	6515	7	0	0
T7	12038	0	0	0
T8	3815	0	0	0
T9	12282	0	0	0
T10	12231	0	0	0
T11	103219	0	0	0
T12	8209	2	0	0
T13	3423	0	0	0
T14	0	10	0	0
T29	0	5	0	0
T42	3891	0	0	0
T43	6238	5	0	0
T45	0	4	0	0
T54	0	3	0	0
T56	0	4	0	0
T59	0	8	0	0
T60	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26026326	12340	0	0
T1	91032	68	0	0
T2	3866	0	0	0
T3	90231	70	0	0
T4	8395	4	0	0
T5	792228	0	0	0
T6	6515	7	0	0
T7	12038	2	0	0
T8	3815	0	0	0
T9	12282	4	0	0
T10	12231	4	0	0
T11	0	66	0	0
T12	0	17	0	0
T13	0	1	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26026326	1004	0	0
T6	6515	7	0	0
T7	12038	0	0	0
T8	3815	0	0	0
T9	12282	0	0	0
T10	12231	0	0	0
T11	103219	0	0	0
T12	8209	2	0	0
T13	3423	0	0	0
T14	0	10	0	0
T29	0	5	0	0
T42	3891	0	0	0
T43	6238	5	0	0
T45	0	4	0	0
T54	0	3	0	0
T56	0	4	0	0
T59	0	8	0	0
T60	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26026242	12361	0	0
T1	91040	68	0	0
T2	3865	0	0	0
T3	90219	70	0	0
T4	8395	4	0	0
T5	792225	0	0	0
T6	6514	10	0	0
T7	12039	2	0	0
T8	3815	0	0	0
T9	12280	4	0	0
T10	12231	4	0	0
T11	0	66	0	0
T12	0	17	0	0
T13	0	1	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26026242	1009	0	0
T6	6514	10	0	0
T7	12039	0	0	0
T8	3815	0	0	0
T9	12280	0	0	0
T10	12231	0	0	0
T11	103216	0	0	0
T12	8209	0	0	0
T13	3423	0	0	0
T14	0	11	0	0
T29	0	6	0	0
T42	3891	0	0	0
T43	6238	5	0	0
T45	0	5	0	0
T54	0	3	0	0
T56	0	4	0	0
T59	0	11	0	0
T81	0	5	0	0
T82	0	7	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26026242	12361	0	0
T1	91040	68	0	0
T2	3865	0	0	0
T3	90219	70	0	0
T4	8395	4	0	0
T5	792225	0	0	0
T6	6514	10	0	0
T7	12039	2	0	0
T8	3815	0	0	0
T9	12280	4	0	0
T10	12231	4	0	0
T11	0	66	0	0
T12	0	17	0	0
T13	0	1	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26026242	1009	0	0
T6	6514	10	0	0
T7	12039	0	0	0
T8	3815	0	0	0
T9	12280	0	0	0
T10	12231	0	0	0
T11	103216	0	0	0
T12	8209	0	0	0
T13	3423	0	0	0
T14	0	11	0	0
T29	0	6	0	0
T42	3891	0	0	0
T43	6238	5	0	0
T45	0	5	0	0
T54	0	3	0	0
T56	0	4	0	0
T59	0	11	0	0
T81	0	5	0	0
T82	0	7	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1642123	21523	0	0
T1	5704	94	0	0
T2	241	1	0	0
T3	5653	86	0	0
T4	523	6	0	0
T5	49761	541	0	0
T6	407	12	0	0
T7	750	7	0	0
T8	236	1	0	0
T9	767	6	0	0
T10	763	7	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1642123	1095	0	0
T6	407	11	0	0
T7	750	1	0	0
T8	236	0	0	0
T9	767	0	0	0
T10	763	1	0	0
T11	6466	0	0	0
T12	512	0	0	0
T13	212	0	0	0
T14	0	9	0	0
T29	0	8	0	0
T42	243	0	0	0
T43	388	8	0	0
T45	0	5	0	0
T54	0	5	0	0
T56	0	6	0	0
T59	0	13	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1642123	21523	0	0
T1	5704	94	0	0
T2	241	1	0	0
T3	5653	86	0	0
T4	523	6	0	0
T5	49761	541	0	0
T6	407	12	0	0
T7	750	7	0	0
T8	236	1	0	0
T9	767	6	0	0
T10	763	7	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1642123	1095	0	0
T6	407	11	0	0
T7	750	1	0	0
T8	236	0	0	0
T9	767	0	0	0
T10	763	1	0	0
T11	6466	0	0	0
T12	512	0	0	0
T13	212	0	0	0
T14	0	9	0	0
T29	0	8	0	0
T42	243	0	0	0
T43	388	8	0	0
T45	0	5	0	0
T54	0	5	0	0
T56	0	6	0	0
T59	0	13	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012794	13754	0	0
T1	45511	75	0	0
T2	1933	0	0	0
T3	45119	75	0	0
T4	4196	4	0	0
T5	396150	0	0	0
T6	3257	10	0	0
T7	6019	4	0	0
T8	1907	0	0	0
T9	6140	4	0	0
T10	6115	4	0	0
T11	0	75	0	0
T12	0	20	0	0
T13	0	2	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012794	1123	0	0
T6	3257	10	0	0
T7	6019	0	0	0
T8	1907	0	0	0
T9	6140	0	0	0
T10	6115	0	0	0
T11	51620	0	0	0
T12	4104	0	0	0
T13	1712	0	0	0
T14	0	9	0	0
T29	0	4	0	0
T42	1945	0	0	0
T43	3118	8	0	0
T45	0	5	0	0
T54	0	5	0	0
T55	0	1	0	0
T56	0	6	0	0
T59	0	12	0	0
T60	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012794	13754	0	0
T1	45511	75	0	0
T2	1933	0	0	0
T3	45119	75	0	0
T4	4196	4	0	0
T5	396150	0	0	0
T6	3257	10	0	0
T7	6019	4	0	0
T8	1907	0	0	0
T9	6140	4	0	0
T10	6115	4	0	0
T11	0	75	0	0
T12	0	20	0	0
T13	0	2	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012794	1123	0	0
T6	3257	10	0	0
T7	6019	0	0	0
T8	1907	0	0	0
T9	6140	0	0	0
T10	6115	0	0	0
T11	51620	0	0	0
T12	4104	0	0	0
T13	1712	0	0	0
T14	0	9	0	0
T29	0	4	0	0
T42	1945	0	0	0
T43	3118	8	0	0
T45	0	5	0	0
T54	0	5	0	0
T55	0	1	0	0
T56	0	6	0	0
T59	0	12	0	0
T60	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012794	13789	0	0
T1	45511	75	0	0
T2	1933	0	0	0
T3	45119	75	0	0
T4	4196	4	0	0
T5	396150	0	0	0
T6	3257	12	0	0
T7	6019	4	0	0
T8	1907	0	0	0
T9	6140	4	0	0
T10	6115	4	0	0
T11	0	75	0	0
T12	0	20	0	0
T13	0	2	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012794	1154	0	0
T6	3257	12	0	0
T7	6019	0	0	0
T8	1907	0	0	0
T9	6140	0	0	0
T10	6115	0	0	0
T11	51620	0	0	0
T12	4104	0	0	0
T13	1712	0	0	0
T14	0	6	0	0
T29	0	6	0	0
T31	0	1	0	0
T42	1945	0	0	0
T43	3118	10	0	0
T45	0	8	0	0
T54	0	6	0	0
T56	0	6	0	0
T59	0	13	0	0
T81	0	10	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012794	13789	0	0
T1	45511	75	0	0
T2	1933	0	0	0
T3	45119	75	0	0
T4	4196	4	0	0
T5	396150	0	0	0
T6	3257	12	0	0
T7	6019	4	0	0
T8	1907	0	0	0
T9	6140	4	0	0
T10	6115	4	0	0
T11	0	75	0	0
T12	0	20	0	0
T13	0	2	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012794	1154	0	0
T6	3257	12	0	0
T7	6019	0	0	0
T8	1907	0	0	0
T9	6140	0	0	0
T10	6115	0	0	0
T11	51620	0	0	0
T12	4104	0	0	0
T13	1712	0	0	0
T14	0	6	0	0
T29	0	6	0	0
T31	0	1	0	0
T42	1945	0	0	0
T43	3118	10	0	0
T45	0	8	0	0
T54	0	6	0	0
T56	0	6	0	0
T59	0	13	0	0
T81	0	10	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012794	13878	0	0
T1	45511	75	0	0
T2	1933	0	0	0
T3	45119	75	0	0
T4	4196	4	0	0
T5	396150	0	0	0
T6	3257	12	0	0
T7	6019	4	0	0
T8	1907	0	0	0
T9	6140	4	0	0
T10	6115	4	0	0
T11	0	75	0	0
T12	0	20	0	0
T13	0	2	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012794	1245	0	0
T6	3257	12	0	0
T7	6019	0	0	0
T8	1907	0	0	0
T9	6140	0	0	0
T10	6115	0	0	0
T11	51620	0	0	0
T12	4104	0	0	0
T13	1712	0	0	0
T14	0	12	0	0
T42	1945	0	0	0
T43	3118	11	0	0
T45	0	9	0	0
T54	0	7	0	0
T55	0	1	0	0
T56	0	8	0	0
T59	0	11	0	0
T60	0	1	0	0
T80	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012794	13878	0	0
T1	45511	75	0	0
T2	1933	0	0	0
T3	45119	75	0	0
T4	4196	4	0	0
T5	396150	0	0	0
T6	3257	12	0	0
T7	6019	4	0	0
T8	1907	0	0	0
T9	6140	4	0	0
T10	6115	4	0	0
T11	0	75	0	0
T12	0	20	0	0
T13	0	2	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13012794	1245	0	0
T6	3257	12	0	0
T7	6019	0	0	0
T8	1907	0	0	0
T9	6140	0	0	0
T10	6115	0	0	0
T11	51620	0	0	0
T12	4104	0	0	0
T13	1712	0	0	0
T14	0	12	0	0
T42	1945	0	0	0
T43	3118	11	0	0
T45	0	9	0	0
T54	0	7	0	0
T55	0	1	0	0
T56	0	8	0	0
T59	0	11	0	0
T60	0	1	0	0
T80	0	1	0	0