Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12322522	7491	0	0
alert_regwen_rd_A	12322522	4782	0	0
cpu_regwen_rd_A	12322522	4750	0	0
sw_rst_ctrl_n_0_rd_A	12322522	7523	0	0
sw_rst_ctrl_n_1_rd_A	12322522	7414	0	0
sw_rst_ctrl_n_2_rd_A	12322522	7502	0	0
sw_rst_ctrl_n_3_rd_A	12322522	7219	0	0
sw_rst_ctrl_n_4_rd_A	12322522	7550	0	0
sw_rst_ctrl_n_5_rd_A	12322522	7546	0	0
sw_rst_ctrl_n_6_rd_A	12322522	7526	0	0
sw_rst_ctrl_n_7_rd_A	12322522	7345	0	0
sw_rst_regwen_0_rd_A	12322522	4988	0	0
sw_rst_regwen_1_rd_A	12322522	5158	0	0
sw_rst_regwen_2_rd_A	12322522	4982	0	0
sw_rst_regwen_3_rd_A	12322522	5035	0	0
sw_rst_regwen_4_rd_A	12322522	4957	0	0
sw_rst_regwen_5_rd_A	12322522	5137	0	0
sw_rst_regwen_6_rd_A	12322522	5090	0	0
sw_rst_regwen_7_rd_A	12322522	5144	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12322522	7491	0	0
T65	4349	14	0	0
T69	5298	203	0	0
T71	4378	18	0	0
T72	9197	1	0	0
T73	3081	416	0	0
T74	10473	4	0	0
T85	11018	2	0	0
T86	4957	21	0	0
T87	2925	10	0	0
T88	2399	6	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12322522	4782	0	0
T14	141459	177	0	0
T29	0	162	0	0
T33	26188	0	0	0
T52	5691	0	0	0
T53	3445	0	0	0
T54	2721	0	0	0
T55	5170	0	0	0
T56	6693	0	0	0
T57	1638	0	0	0
T58	1412	0	0	0
T59	8875	0	0	0
T93	0	50	0	0
T97	0	229	0	0
T100	0	46	0	0
T101	0	130	0	0
T104	0	54	0	0
T126	0	42	0	0
T127	0	152	0	0
T128	0	304	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12322522	4750	0	0
T14	141459	169	0	0
T29	0	191	0	0
T33	26188	0	0	0
T52	5691	0	0	0
T53	3445	0	0	0
T54	2721	0	0	0
T55	5170	0	0	0
T56	6693	0	0	0
T57	1638	0	0	0
T58	1412	0	0	0
T59	8875	0	0	0
T93	0	55	0	0
T97	0	279	0	0
T100	0	28	0	0
T101	0	173	0	0
T104	0	47	0	0
T126	0	35	0	0
T127	0	160	0	0
T128	0	297	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12322522	7523	0	0
T7	5777	12	0	0
T8	1817	0	0	0
T9	5849	13	0	0
T10	5776	5	0	0
T11	48598	0	0	0
T12	2634	0	0	0
T13	1588	0	0	0
T14	0	319	0	0
T29	0	250	0	0
T31	0	11	0	0
T42	1855	0	0	0
T43	3052	0	0	0
T44	2179	0	0	0
T55	0	16	0	0
T60	0	7	0	0
T129	0	7	0	0
T130	0	11	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12322522	7414	0	0
T7	5777	18	0	0
T8	1817	0	0	0
T9	5849	18	0	0
T10	5776	16	0	0
T11	48598	0	0	0
T12	2634	0	0	0
T13	1588	0	0	0
T14	0	354	0	0
T29	0	271	0	0
T31	0	14	0	0
T42	1855	0	0	0
T43	3052	0	0	0
T44	2179	0	0	0
T60	0	13	0	0
T93	0	48	0	0
T129	0	3	0	0
T130	0	4	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12322522	7502	0	0
T7	5777	12	0	0
T8	1817	0	0	0
T9	5849	26	0	0
T10	5776	12	0	0
T11	48598	0	0	0
T12	2634	0	0	0
T13	1588	0	0	0
T14	0	236	0	0
T29	0	278	0	0
T31	0	19	0	0
T42	1855	0	0	0
T43	3052	0	0	0
T44	2179	0	0	0
T55	0	12	0	0
T60	0	10	0	0
T129	0	10	0	0
T130	0	1	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12322522	7219	0	0
T7	5777	17	0	0
T8	1817	0	0	0
T9	5849	14	0	0
T10	5776	13	0	0
T11	48598	0	0	0
T12	2634	0	0	0
T13	1588	0	0	0
T14	0	317	0	0
T29	0	247	0	0
T31	0	18	0	0
T42	1855	0	0	0
T43	3052	0	0	0
T44	2179	0	0	0
T55	0	8	0	0
T60	0	12	0	0
T129	0	11	0	0
T130	0	2	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12322522	7550	0	0
T7	5777	8	0	0
T8	1817	0	0	0
T9	5849	20	0	0
T10	5776	17	0	0
T11	48598	0	0	0
T12	2634	0	0	0
T13	1588	0	0	0
T14	0	287	0	0
T29	0	248	0	0
T31	0	4	0	0
T42	1855	0	0	0
T43	3052	0	0	0
T44	2179	0	0	0
T55	0	17	0	0
T60	0	5	0	0
T93	0	48	0	0
T129	0	9	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12322522	7546	0	0
T7	5777	7	0	0
T8	1817	0	0	0
T9	5849	11	0	0
T10	5776	25	0	0
T11	48598	0	0	0
T12	2634	0	0	0
T13	1588	0	0	0
T14	0	301	0	0
T29	0	264	0	0
T31	0	20	0	0
T42	1855	0	0	0
T43	3052	0	0	0
T44	2179	0	0	0
T55	0	4	0	0
T60	0	4	0	0
T129	0	20	0	0
T130	0	8	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12322522	7526	0	0
T7	5777	7	0	0
T8	1817	0	0	0
T9	5849	14	0	0
T10	5776	16	0	0
T11	48598	0	0	0
T12	2634	0	0	0
T13	1588	0	0	0
T14	0	325	0	0
T29	0	255	0	0
T31	0	15	0	0
T42	1855	0	0	0
T43	3052	0	0	0
T44	2179	0	0	0
T55	0	8	0	0
T60	0	6	0	0
T129	0	8	0	0
T130	0	1	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12322522	7345	0	0
T7	5777	6	0	0
T8	1817	0	0	0
T9	5849	6	0	0
T10	5776	13	0	0
T11	48598	0	0	0
T12	2634	0	0	0
T13	1588	0	0	0
T14	0	310	0	0
T29	0	248	0	0
T31	0	12	0	0
T42	1855	0	0	0
T43	3052	0	0	0
T44	2179	0	0	0
T55	0	10	0	0
T60	0	3	0	0
T93	0	16	0	0
T129	0	16	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12322522	4988	0	0
T7	5777	11	0	0
T8	1817	0	0	0
T9	5849	5	0	0
T10	5776	7	0	0
T11	48598	0	0	0
T12	2634	0	0	0
T13	1588	0	0	0
T14	0	150	0	0
T29	0	198	0	0
T31	0	6	0	0
T42	1855	0	0	0
T43	3052	0	0	0
T44	2179	0	0	0
T55	0	6	0	0
T60	0	3	0	0
T93	0	38	0	0
T129	0	10	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12322522	5158	0	0
T7	5777	2	0	0
T8	1817	0	0	0
T9	5849	8	0	0
T10	5776	16	0	0
T11	48598	0	0	0
T12	2634	0	0	0
T13	1588	0	0	0
T14	0	221	0	0
T29	0	189	0	0
T31	0	8	0	0
T42	1855	0	0	0
T43	3052	0	0	0
T44	2179	0	0	0
T55	0	3	0	0
T60	0	9	0	0
T93	0	23	0	0
T129	0	12	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12322522	4982	0	0
T7	5777	1	0	0
T8	1817	0	0	0
T9	5849	3	0	0
T10	5776	17	0	0
T11	48598	0	0	0
T12	2634	0	0	0
T13	1588	0	0	0
T14	0	171	0	0
T29	0	148	0	0
T31	0	13	0	0
T42	1855	0	0	0
T43	3052	0	0	0
T44	2179	0	0	0
T55	0	5	0	0
T60	0	7	0	0
T93	0	33	0	0
T129	0	4	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12322522	5035	0	0
T7	5777	14	0	0
T8	1817	0	0	0
T9	5849	10	0	0
T10	5776	10	0	0
T11	48598	0	0	0
T12	2634	0	0	0
T13	1588	0	0	0
T14	0	195	0	0
T29	0	169	0	0
T31	0	11	0	0
T42	1855	0	0	0
T43	3052	0	0	0
T44	2179	0	0	0
T60	0	7	0	0
T93	0	43	0	0
T129	0	8	0	0
T131	0	4	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12322522	4957	0	0
T7	5777	3	0	0
T8	1817	0	0	0
T9	5849	7	0	0
T10	5776	1	0	0
T11	48598	0	0	0
T12	2634	0	0	0
T13	1588	0	0	0
T14	0	176	0	0
T29	0	189	0	0
T31	0	3	0	0
T42	1855	0	0	0
T43	3052	0	0	0
T44	2179	0	0	0
T55	0	14	0	0
T93	0	32	0	0
T129	0	12	0	0
T131	0	5	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12322522	5137	0	0
T7	5777	7	0	0
T8	1817	0	0	0
T9	5849	3	0	0
T10	5776	12	0	0
T11	48598	0	0	0
T12	2634	0	0	0
T13	1588	0	0	0
T14	0	144	0	0
T29	0	204	0	0
T31	0	2	0	0
T42	1855	0	0	0
T43	3052	0	0	0
T44	2179	0	0	0
T55	0	8	0	0
T60	0	15	0	0
T93	0	28	0	0
T129	0	6	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12322522	5090	0	0
T7	5777	3	0	0
T8	1817	0	0	0
T9	5849	11	0	0
T10	5776	8	0	0
T11	48598	0	0	0
T12	2634	0	0	0
T13	1588	0	0	0
T14	0	157	0	0
T29	0	145	0	0
T31	0	5	0	0
T42	1855	0	0	0
T43	3052	0	0	0
T44	2179	0	0	0
T93	0	60	0	0
T97	0	236	0	0
T129	0	11	0	0
T131	0	7	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12322522	5144	0	0
T7	5777	13	0	0
T8	1817	0	0	0
T9	5849	3	0	0
T10	5776	4	0	0
T11	48598	0	0	0
T12	2634	0	0	0
T13	1588	0	0	0
T14	0	209	0	0
T29	0	210	0	0
T42	1855	0	0	0
T43	3052	0	0	0
T44	2179	0	0	0
T55	0	9	0	0
T60	0	9	0	0
T93	0	34	0	0
T129	0	1	0	0
T131	0	6	0	0