Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	605454	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

360833

1

T1

141

T2

72

T3

4536

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	515384	1			T1	186		T2	99		T3	6766
values[0x0]	225201	1			T1	91		T2	57		T3	2623
values[0x1]	225702	1			T1	102		T2	56		T3	2533

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	508446	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

457841

1

T1

186

T2

92

T3

5720

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3411	1			T1	3		T3	50		T8	9
valid_sources[0x01]	3178	1			T1	1		T2	2		T3	54
valid_sources[0x02]	4104	1			T1	2		T3	52		T8	1
valid_sources[0x03]	3039	1			T1	3		T3	46		T8	5
valid_sources[0x04]	2897	1			T1	1		T3	44		T8	3
valid_sources[0x05]	2989	1			T1	1		T3	52		T12	58
valid_sources[0x06]	3859	1			T1	1		T2	3		T3	59
valid_sources[0x07]	3514	1			T1	3		T3	38		T8	2
valid_sources[0x08]	4866	1			T1	2		T2	1		T3	46
valid_sources[0x09]	3013	1			T1	1		T3	49		T8	1
valid_sources[0x0a]	3888	1			T3	50		T12	72		T13	1
valid_sources[0x0b]	3881	1			T2	4		T3	41		T12	76
valid_sources[0x0c]	4913	1			T1	2		T2	2		T3	53
valid_sources[0x0d]	3268	1			T3	65		T8	6		T12	85
valid_sources[0x0e]	5335	1			T1	2		T3	49		T12	70
valid_sources[0x0f]	4071	1			T1	1		T3	43		T8	2
valid_sources[0x10]	3248	1			T3	47		T8	2		T12	75
valid_sources[0x11]	3580	1			T2	1		T3	49		T8	3
valid_sources[0x12]	4407	1			T1	3		T3	43		T8	7
valid_sources[0x13]	3379	1			T3	58		T8	6		T12	77
valid_sources[0x14]	3683	1			T1	3		T3	38		T8	2
valid_sources[0x15]	4471	1			T3	45		T8	9		T12	79
valid_sources[0x16]	4209	1			T1	3		T3	52		T12	71
valid_sources[0x17]	3044	1			T1	1		T3	48		T8	4
valid_sources[0x18]	4028	1			T1	1		T3	43		T12	80
valid_sources[0x19]	4310	1			T1	2		T3	53		T8	2
valid_sources[0x1a]	4006	1			T1	2		T3	56		T12	65
valid_sources[0x1b]	3346	1			T1	1		T2	1		T3	57
valid_sources[0x1c]	3047	1			T1	1		T2	1		T3	53
valid_sources[0x1d]	3444	1			T1	2		T2	2		T3	47
valid_sources[0x1e]	3673	1			T3	43		T8	4		T12	70
valid_sources[0x1f]	2765	1			T1	3		T3	33		T5	1
valid_sources[0x20]	3333	1			T1	2		T3	42		T8	3
valid_sources[0x21]	3043	1			T3	52		T8	1		T12	60
valid_sources[0x22]	4098	1			T1	1		T2	2		T3	48
valid_sources[0x23]	6953	1			T1	3		T2	1		T3	62
valid_sources[0x24]	4070	1			T2	1		T3	47		T8	1
valid_sources[0x25]	3186	1			T1	4		T2	1		T3	54
valid_sources[0x26]	3045	1			T3	59		T8	7		T12	85
valid_sources[0x27]	2821	1			T2	1		T3	22		T8	1
valid_sources[0x28]	3278	1			T1	3		T2	1		T3	34
valid_sources[0x29]	4211	1			T1	1		T2	5		T3	38
valid_sources[0x2a]	3119	1			T3	49		T8	4		T12	63
valid_sources[0x2b]	2794	1			T1	2		T3	47		T8	4
valid_sources[0x2c]	3212	1			T1	1		T3	40		T8	7
valid_sources[0x2d]	2923	1			T1	2		T3	59		T5	1
valid_sources[0x2e]	3688	1			T3	60		T8	5		T12	64
valid_sources[0x2f]	3129	1			T3	35		T8	7		T12	67
valid_sources[0x30]	6421	1			T2	1		T3	55		T12	65
valid_sources[0x31]	7351	1			T1	6		T3	41		T8	3
valid_sources[0x32]	3559	1			T3	59		T8	4		T12	74
valid_sources[0x33]	4756	1			T1	1		T3	53		T8	4
valid_sources[0x34]	3522	1			T1	1		T3	34		T8	4
valid_sources[0x35]	3145	1			T1	1		T2	3		T3	43
valid_sources[0x36]	3715	1			T3	46		T8	1		T12	64
valid_sources[0x37]	4024	1			T1	1		T3	48		T12	74
valid_sources[0x38]	3510	1			T3	53		T8	2		T12	61
valid_sources[0x39]	3650	1			T3	54		T8	1		T12	80
valid_sources[0x3a]	2998	1			T1	1		T2	2		T3	66
valid_sources[0x3b]	4545	1			T1	2		T3	50		T8	5
valid_sources[0x3c]	3403	1			T2	2		T3	48		T8	5
valid_sources[0x3d]	3773	1			T3	42		T12	92		T61	7
valid_sources[0x3e]	4105	1			T1	2		T2	4		T3	44
valid_sources[0x3f]	3023	1			T3	56		T8	12		T12	80
valid_sources[0x40]	3696	1			T2	2		T3	50		T8	4
valid_sources[0x41]	3456	1			T1	2		T3	57		T8	2
valid_sources[0x42]	3651	1			T2	1		T3	44		T8	5
valid_sources[0x43]	3878	1			T1	2		T2	1		T3	34
valid_sources[0x44]	3994	1			T1	2		T3	45		T8	7
valid_sources[0x45]	3383	1			T1	2		T2	2		T3	59
valid_sources[0x46]	3973	1			T2	1		T3	44		T8	9
valid_sources[0x47]	3429	1			T3	46		T8	2		T12	60
valid_sources[0x48]	3508	1			T1	2		T3	73		T8	2
valid_sources[0x49]	2940	1			T1	2		T3	32		T12	92
valid_sources[0x4a]	3187	1			T3	52		T8	3		T12	57
valid_sources[0x4b]	3170	1			T1	1		T3	60		T12	70
valid_sources[0x4c]	4748	1			T1	4		T3	39		T8	2
valid_sources[0x4d]	5016	1			T3	69		T8	4		T12	61
valid_sources[0x4e]	3138	1			T1	2		T2	1		T3	37
valid_sources[0x4f]	3297	1			T1	1		T2	1		T3	67
valid_sources[0x50]	3606	1			T1	1		T3	42		T8	7
valid_sources[0x51]	4228	1			T1	2		T2	1		T3	70
valid_sources[0x52]	3865	1			T1	2		T3	47		T8	2
valid_sources[0x53]	3274	1			T1	1		T2	2		T3	48
valid_sources[0x54]	3434	1			T1	4		T2	1		T3	45
valid_sources[0x55]	3370	1			T3	36		T12	71		T13	6
valid_sources[0x56]	3578	1			T2	1		T3	48		T12	75
valid_sources[0x57]	4396	1			T1	2		T3	59		T8	3
valid_sources[0x58]	4019	1			T1	1		T2	1		T3	39
valid_sources[0x59]	3550	1			T1	6		T3	46		T8	1
valid_sources[0x5a]	3319	1			T1	3		T3	45		T8	5
valid_sources[0x5b]	4666	1			T1	5		T2	2		T3	51
valid_sources[0x5c]	3035	1			T1	1		T3	45		T8	1
valid_sources[0x5d]	3287	1			T1	1		T2	1		T3	51
valid_sources[0x5e]	3915	1			T1	1		T2	1		T3	34
valid_sources[0x5f]	3332	1			T3	37		T8	1		T12	81
valid_sources[0x60]	3286	1			T1	3		T3	42		T8	3
valid_sources[0x61]	3848	1			T2	1		T3	32		T5	3
valid_sources[0x62]	3406	1			T1	1		T3	38		T5	2
valid_sources[0x63]	3739	1			T1	2		T2	1		T3	50
valid_sources[0x64]	3173	1			T1	3		T2	4		T3	52
valid_sources[0x65]	3837	1			T1	1		T2	1		T3	60
valid_sources[0x66]	4119	1			T3	39		T12	68		T13	1
valid_sources[0x67]	3557	1			T1	1		T2	1		T3	50
valid_sources[0x68]	3215	1			T1	1		T2	1		T3	38
valid_sources[0x69]	4842	1			T1	1		T2	1		T3	49
valid_sources[0x6a]	4710	1			T2	1		T3	53		T8	4
valid_sources[0x6b]	3920	1			T2	3		T3	38		T8	4
valid_sources[0x6c]	3200	1			T2	1		T3	50		T12	70
valid_sources[0x6d]	2922	1			T1	3		T2	1		T3	43
valid_sources[0x6e]	4394	1			T1	1		T3	55		T8	9
valid_sources[0x6f]	3434	1			T2	1		T3	44		T8	3
valid_sources[0x70]	5644	1			T1	1		T3	38		T8	2
valid_sources[0x71]	6061	1			T1	1		T3	32		T8	2
valid_sources[0x72]	3246	1			T1	2		T3	35		T5	3
valid_sources[0x73]	3188	1			T1	1		T3	48		T12	69
valid_sources[0x74]	3425	1			T3	45		T12	69		T61	3
valid_sources[0x75]	3108	1			T1	5		T2	1		T3	51
valid_sources[0x76]	3131	1			T1	6		T2	3		T3	47
valid_sources[0x77]	4164	1			T3	41		T8	4		T12	73
valid_sources[0x78]	3004	1			T1	3		T3	40		T8	3
valid_sources[0x79]	3283	1			T1	1		T3	46		T8	2
valid_sources[0x7a]	3350	1			T1	6		T3	49		T8	2
valid_sources[0x7b]	3790	1			T1	5		T3	44		T5	2
valid_sources[0x7c]	4700	1			T1	3		T3	38		T8	9
valid_sources[0x7d]	3562	1			T1	2		T2	5		T3	47
valid_sources[0x7e]	2640	1			T2	1		T3	46		T8	2
valid_sources[0x7f]	3551	1			T1	3		T2	11		T3	37
valid_sources[0x80]	3083	1			T1	1		T3	52		T12	67

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

241329

1

T1

87

T2

43

T3

3224

values[0x0]

all_enables

biggest_size

77803

1

T1

35

T2

22

T3

864

values[0x1]

all_enables

biggest_size

41701

1

T1

19

T2

7

T3

448