Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11213383	12904	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11213383	118878	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11213383	6673182	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11213383	190331	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11213383	12904	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11213383	118878	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11213383	6673182	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11213383	190331	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11213383	12904	0	0
T1	5322	4	0	0
T2	3318	4	0	0
T3	76223	127	0	0
T4	1990	0	0	0
T5	1834	0	0	0
T6	5480	0	0	0
T7	4010	4	0	0
T8	9331	0	0	0
T9	1366	0	0	0
T10	5615	4	0	0
T12	0	236	0	0
T13	0	8	0	0
T14	0	4	0	0
T23	0	4	0	0
T24	0	4	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11213383	118878	0	0
T1	5322	38	0	0
T2	3318	37	0	0
T3	76223	1149	0	0
T4	1990	0	0	0
T5	1834	0	0	0
T6	5480	0	0	0
T7	4010	37	0	0
T8	9331	0	0	0
T9	1366	0	0	0
T10	5615	37	0	0
T12	0	2160	0	0
T13	0	74	0	0
T14	0	37	0	0
T23	0	37	0	0
T24	0	38	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11213383	6673182	0	0
T1	5322	4366	0	0
T2	3318	2354	0	0
T3	76223	36200	0	0
T4	1990	819	0	0
T5	1834	1267	0	0
T6	5480	579	0	0
T7	4010	3023	0	0
T8	9331	8764	0	0
T9	1366	752	0	0
T10	5615	4690	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11213383	190331	0	0
T1	5322	75	0	0
T2	3318	58	0	0
T3	76223	1825	0	0
T4	1990	0	0	0
T5	1834	0	0	0
T6	5480	0	0	0
T7	4010	58	0	0
T8	9331	0	0	0
T9	1366	0	0	0
T10	5615	57	0	0
T12	0	3500	0	0
T13	0	123	0	0
T14	0	58	0	0
T23	0	69	0	0
T24	0	54	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11213383	12904	0	0
T1	5322	4	0	0
T2	3318	4	0	0
T3	76223	127	0	0
T4	1990	0	0	0
T5	1834	0	0	0
T6	5480	0	0	0
T7	4010	4	0	0
T8	9331	0	0	0
T9	1366	0	0	0
T10	5615	4	0	0
T12	0	236	0	0
T13	0	8	0	0
T14	0	4	0	0
T23	0	4	0	0
T24	0	4	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11213383	118878	0	0
T1	5322	38	0	0
T2	3318	37	0	0
T3	76223	1149	0	0
T4	1990	0	0	0
T5	1834	0	0	0
T6	5480	0	0	0
T7	4010	37	0	0
T8	9331	0	0	0
T9	1366	0	0	0
T10	5615	37	0	0
T12	0	2160	0	0
T13	0	74	0	0
T14	0	37	0	0
T23	0	37	0	0
T24	0	38	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11213383	6673182	0	0
T1	5322	4366	0	0
T2	3318	2354	0	0
T3	76223	36200	0	0
T4	1990	819	0	0
T5	1834	1267	0	0
T6	5480	579	0	0
T7	4010	3023	0	0
T8	9331	8764	0	0
T9	1366	752	0	0
T10	5615	4690	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11213383	190331	0	0
T1	5322	75	0	0
T2	3318	58	0	0
T3	76223	1825	0	0
T4	1990	0	0	0
T5	1834	0	0	0
T6	5480	0	0	0
T7	4010	58	0	0
T8	9331	0	0	0
T9	1366	0	0	0
T10	5615	57	0	0
T12	0	3500	0	0
T13	0	123	0	0
T14	0	58	0	0
T23	0	69	0	0
T24	0	54	0	0