Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T7
1	0	Covered	T1,T3,T12

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	52926174	8444	0	0
CascadeEffAonToRstPorAboveRise_A	52926174	8444	0	0
CascadeEffAonToRstPorIoAboveFall_A	50807772	8444	0	0
CascadeEffAonToRstPorIoAboveRise_A	50807772	8444	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25404438	8444	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25404438	8444	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12701794	8444	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12701794	8444	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25404320	8444	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25404320	8444	0	0
CascadeLcToLcAboveFall_A	52926174	21348	0	0
CascadeLcToLcAboveRise_A	52926174	21348	0	0
CascadeLcToLcAonAboveFall_A	1603287	21348	0	0
CascadeLcToLcAonAboveRise_A	1603287	21348	0	0
CascadeLcToLcShadowedAboveFall_A	52926174	21348	0	0
CascadeLcToLcShadowedAboveRise_A	52926174	21348	0	0
CascadePorToAonAboveFall_A	1603287	6738	0	0
CascadeSysToSysAboveFall_A	52926174	21348	0	0
CascadeSysToSysAboveRise_A	52926174	21348	0	0
ScanRstToAonRise_A	1603287	199	0	0
StablePorToAonRise_A	1603287	8444	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11213383	21348	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11213383	21348	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11213383	21348	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11213383	21348	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12701794	21348	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12701794	21348	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11213383	21348	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11213383	21348	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11213383	21348	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11213383	21348	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52926174	8444	0	0
T1	23572	2	0	0
T2	15241	2	0	0
T3	395883	88	0	0
T4	8571	2	0	0
T5	8025	1	0	0
T6	24306	8	0	0
T7	17512	2	0	0
T8	39261	1	0	0
T9	5873	1	0	0
T10	24812	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52926174	8444	0	0
T1	23572	2	0	0
T2	15241	2	0	0
T3	395883	88	0	0
T4	8571	2	0	0
T5	8025	1	0	0
T6	24306	8	0	0
T7	17512	2	0	0
T8	39261	1	0	0
T9	5873	1	0	0
T10	24812	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50807772	8444	0	0
T1	22630	2	0	0
T2	14627	2	0	0
T3	380019	88	0	0
T4	8228	2	0	0
T5	7703	1	0	0
T6	23340	8	0	0
T7	16814	2	0	0
T8	37689	1	0	0
T9	5638	1	0	0
T10	23812	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50807772	8444	0	0
T1	22630	2	0	0
T2	14627	2	0	0
T3	380019	88	0	0
T4	8228	2	0	0
T5	7703	1	0	0
T6	23340	8	0	0
T7	16814	2	0	0
T8	37689	1	0	0
T9	5638	1	0	0
T10	23812	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25404438	8444	0	0
T1	11316	2	0	0
T2	7311	2	0	0
T3	190008	88	0	0
T4	4113	2	0	0
T5	3852	1	0	0
T6	11667	8	0	0
T7	8405	2	0	0
T8	18844	1	0	0
T9	2819	1	0	0
T10	11906	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25404438	8444	0	0
T1	11316	2	0	0
T2	7311	2	0	0
T3	190008	88	0	0
T4	4113	2	0	0
T5	3852	1	0	0
T6	11667	8	0	0
T7	8405	2	0	0
T8	18844	1	0	0
T9	2819	1	0	0
T10	11906	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12701794	8444	0	0
T1	5654	2	0	0
T2	3658	2	0	0
T3	95022	88	0	0
T4	2055	2	0	0
T5	1924	1	0	0
T6	5832	8	0	0
T7	4202	2	0	0
T8	9422	1	0	0
T9	1408	1	0	0
T10	5954	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12701794	8444	0	0
T1	5654	2	0	0
T2	3658	2	0	0
T3	95022	88	0	0
T4	2055	2	0	0
T5	1924	1	0	0
T6	5832	8	0	0
T7	4202	2	0	0
T8	9422	1	0	0
T9	1408	1	0	0
T10	5954	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25404320	8444	0	0
T1	11314	2	0	0
T2	7315	2	0	0
T3	190046	88	0	0
T4	4113	2	0	0
T5	3852	1	0	0
T6	11660	8	0	0
T7	8404	2	0	0
T8	18844	1	0	0
T9	2819	1	0	0
T10	11906	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25404320	8444	0	0
T1	11314	2	0	0
T2	7315	2	0	0
T3	190046	88	0	0
T4	4113	2	0	0
T5	3852	1	0	0
T6	11660	8	0	0
T7	8404	2	0	0
T8	18844	1	0	0
T9	2819	1	0	0
T10	11906	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52926174	21348	0	0
T1	23572	6	0	0
T2	15241	6	0	0
T3	395883	215	0	0
T4	8571	2	0	0
T5	8025	1	0	0
T6	24306	8	0	0
T7	17512	6	0	0
T8	39261	1	0	0
T9	5873	1	0	0
T10	24812	6	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52926174	21348	0	0
T1	23572	6	0	0
T2	15241	6	0	0
T3	395883	215	0	0
T4	8571	2	0	0
T5	8025	1	0	0
T6	24306	8	0	0
T7	17512	6	0	0
T8	39261	1	0	0
T9	5873	1	0	0
T10	24812	6	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1603287	21348	0	0
T1	705	6	0	0
T2	456	6	0	0
T3	12132	215	0	0
T4	255	2	0	0
T5	240	1	0	0
T6	732	8	0	0
T7	523	6	0	0
T8	1177	1	0	0
T9	176	1	0	0
T10	744	6	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1603287	21348	0	0
T1	705	6	0	0
T2	456	6	0	0
T3	12132	215	0	0
T4	255	2	0	0
T5	240	1	0	0
T6	732	8	0	0
T7	523	6	0	0
T8	1177	1	0	0
T9	176	1	0	0
T10	744	6	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52926174	21348	0	0
T1	23572	6	0	0
T2	15241	6	0	0
T3	395883	215	0	0
T4	8571	2	0	0
T5	8025	1	0	0
T6	24306	8	0	0
T7	17512	6	0	0
T8	39261	1	0	0
T9	5873	1	0	0
T10	24812	6	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52926174	21348	0	0
T1	23572	6	0	0
T2	15241	6	0	0
T3	395883	215	0	0
T4	8571	2	0	0
T5	8025	1	0	0
T6	24306	8	0	0
T7	17512	6	0	0
T8	39261	1	0	0
T9	5873	1	0	0
T10	24812	6	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1603287	6738	0	0
T1	705	1	0	0
T2	456	1	0	0
T3	12132	46	0	0
T4	255	3	0	0
T5	240	1	0	0
T6	732	8	0	0
T7	523	1	0	0
T8	1177	1	0	0
T9	176	1	0	0
T10	744	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52926174	21348	0	0
T1	23572	6	0	0
T2	15241	6	0	0
T3	395883	215	0	0
T4	8571	2	0	0
T5	8025	1	0	0
T6	24306	8	0	0
T7	17512	6	0	0
T8	39261	1	0	0
T9	5873	1	0	0
T10	24812	6	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	52926174	21348	0	0
T1	23572	6	0	0
T2	15241	6	0	0
T3	395883	215	0	0
T4	8571	2	0	0
T5	8025	1	0	0
T6	24306	8	0	0
T7	17512	6	0	0
T8	39261	1	0	0
T9	5873	1	0	0
T10	24812	6	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1603287	199	0	0
T3	12132	5	0	0
T4	255	0	0	0
T5	240	0	0	0
T6	732	0	0	0
T7	523	1	0	0
T8	1177	0	0	0
T9	176	0	0	0
T10	744	0	0	0
T11	343	0	0	0
T12	18289	6	0	0
T35	0	2	0	0
T37	0	1	0	0
T39	0	3	0	0
T54	0	1	0	0
T57	0	1	0	0
T87	0	1	0	0
T99	0	5	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1603287	8444	0	0
T1	705	2	0	0
T2	456	2	0	0
T3	12132	88	0	0
T4	255	2	0	0
T5	240	1	0	0
T6	732	8	0	0
T7	523	2	0	0
T8	1177	1	0	0
T9	176	1	0	0
T10	744	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11213383	21348	0	0
T1	5322	6	0	0
T2	3318	6	0	0
T3	76223	215	0	0
T4	1990	2	0	0
T5	1834	1	0	0
T6	5480	8	0	0
T7	4010	6	0	0
T8	9331	1	0	0
T9	1366	1	0	0
T10	5615	6	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11213383	21348	0	0
T1	5322	6	0	0
T2	3318	6	0	0
T3	76223	215	0	0
T4	1990	2	0	0
T5	1834	1	0	0
T6	5480	8	0	0
T7	4010	6	0	0
T8	9331	1	0	0
T9	1366	1	0	0
T10	5615	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11213383	21348	0	0
T1	5322	6	0	0
T2	3318	6	0	0
T3	76223	215	0	0
T4	1990	2	0	0
T5	1834	1	0	0
T6	5480	8	0	0
T7	4010	6	0	0
T8	9331	1	0	0
T9	1366	1	0	0
T10	5615	6	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11213383	21348	0	0
T1	5322	6	0	0
T2	3318	6	0	0
T3	76223	215	0	0
T4	1990	2	0	0
T5	1834	1	0	0
T6	5480	8	0	0
T7	4010	6	0	0
T8	9331	1	0	0
T9	1366	1	0	0
T10	5615	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12701794	21348	0	0
T1	5654	6	0	0
T2	3658	6	0	0
T3	95022	215	0	0
T4	2055	2	0	0
T5	1924	1	0	0
T6	5832	8	0	0
T7	4202	6	0	0
T8	9422	1	0	0
T9	1408	1	0	0
T10	5954	6	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12701794	21348	0	0
T1	5654	6	0	0
T2	3658	6	0	0
T3	95022	215	0	0
T4	2055	2	0	0
T5	1924	1	0	0
T6	5832	8	0	0
T7	4202	6	0	0
T8	9422	1	0	0
T9	1408	1	0	0
T10	5954	6	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11213383	21348	0	0
T1	5322	6	0	0
T2	3318	6	0	0
T3	76223	215	0	0
T4	1990	2	0	0
T5	1834	1	0	0
T6	5480	8	0	0
T7	4010	6	0	0
T8	9331	1	0	0
T9	1366	1	0	0
T10	5615	6	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11213383	21348	0	0
T1	5322	6	0	0
T2	3318	6	0	0
T3	76223	215	0	0
T4	1990	2	0	0
T5	1834	1	0	0
T6	5480	8	0	0
T7	4010	6	0	0
T8	9331	1	0	0
T9	1366	1	0	0
T10	5615	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11213383	21348	0	0
T1	5322	6	0	0
T2	3318	6	0	0
T3	76223	215	0	0
T4	1990	2	0	0
T5	1834	1	0	0
T6	5480	8	0	0
T7	4010	6	0	0
T8	9331	1	0	0
T9	1366	1	0	0
T10	5615	6	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11213383	21348	0	0
T1	5322	6	0	0
T2	3318	6	0	0
T3	76223	215	0	0
T4	1990	2	0	0
T5	1834	1	0	0
T6	5480	8	0	0
T7	4010	6	0	0
T8	9331	1	0	0
T9	1366	1	0	0
T10	5615	6	0	0