Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T8,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T3,T8
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12701794	13826	0	0
gen_assertions[0].RstEnOn_A	12701794	1092	0	0
gen_assertions[0].RstNOff_A	12701794	13826	0	0
gen_assertions[0].RstNOn_A	12701794	1092	0	0
gen_assertions[1].RstEnOff_A	50807772	12591	0	0
gen_assertions[1].RstEnOn_A	50807772	1042	0	0
gen_assertions[1].RstNOff_A	50807772	12591	0	0
gen_assertions[1].RstNOn_A	50807772	1042	0	0
gen_assertions[2].RstEnOff_A	25404438	12650	0	0
gen_assertions[2].RstEnOn_A	25404438	1047	0	0
gen_assertions[2].RstNOff_A	25404438	12650	0	0
gen_assertions[2].RstNOn_A	25404438	1047	0	0
gen_assertions[3].RstEnOff_A	25404320	12692	0	0
gen_assertions[3].RstEnOn_A	25404320	1082	0	0
gen_assertions[3].RstNOff_A	25404320	12692	0	0
gen_assertions[3].RstNOn_A	25404320	1082	0	0
gen_assertions[4].RstEnOff_A	1603287	21199	0	0
gen_assertions[4].RstEnOn_A	1603287	1127	0	0
gen_assertions[4].RstNOff_A	1603287	21199	0	0
gen_assertions[4].RstNOn_A	1603287	1127	0	0
gen_assertions[5].RstEnOff_A	12701794	14054	0	0
gen_assertions[5].RstEnOn_A	12701794	1181	0	0
gen_assertions[5].RstNOff_A	12701794	14054	0	0
gen_assertions[5].RstNOn_A	12701794	1181	0	0
gen_assertions[6].RstEnOff_A	12701794	14086	0	0
gen_assertions[6].RstEnOn_A	12701794	1217	0	0
gen_assertions[6].RstNOff_A	12701794	14086	0	0
gen_assertions[6].RstNOn_A	12701794	1217	0	0
gen_assertions[7].RstEnOff_A	12701794	14140	0	0
gen_assertions[7].RstEnOn_A	12701794	1270	0	0
gen_assertions[7].RstNOff_A	12701794	14140	0	0
gen_assertions[7].RstNOn_A	12701794	1270	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12701794	13826	0	0
T1	5654	4	0	0
T2	3658	4	0	0
T3	95022	142	0	0
T4	2055	0	0	0
T5	1924	0	0	0
T6	5832	0	0	0
T7	4202	4	0	0
T8	9422	2	0	0
T9	1408	0	0	0
T10	5954	5	0	0
T12	0	250	0	0
T13	0	12	0	0
T14	0	4	0	0
T61	0	2	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12701794	1092	0	0
T3	95022	16	0	0
T4	2055	0	0	0
T5	1924	0	0	0
T6	5832	0	0	0
T7	4202	0	0	0
T8	9422	2	0	0
T9	1408	0	0	0
T10	5954	1	0	0
T11	2744	0	0	0
T12	142673	14	0	0
T13	0	5	0	0
T49	0	6	0	0
T51	0	1	0	0
T53	0	1	0	0
T56	0	7	0	0
T61	0	2	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12701794	13826	0	0
T1	5654	4	0	0
T2	3658	4	0	0
T3	95022	142	0	0
T4	2055	0	0	0
T5	1924	0	0	0
T6	5832	0	0	0
T7	4202	4	0	0
T8	9422	2	0	0
T9	1408	0	0	0
T10	5954	5	0	0
T12	0	250	0	0
T13	0	12	0	0
T14	0	4	0	0
T61	0	2	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12701794	1092	0	0
T3	95022	16	0	0
T4	2055	0	0	0
T5	1924	0	0	0
T6	5832	0	0	0
T7	4202	0	0	0
T8	9422	2	0	0
T9	1408	0	0	0
T10	5954	1	0	0
T11	2744	0	0	0
T12	142673	14	0	0
T13	0	5	0	0
T49	0	6	0	0
T51	0	1	0	0
T53	0	1	0	0
T56	0	7	0	0
T61	0	2	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50807772	12591	0	0
T1	22630	4	0	0
T2	14627	3	0	0
T3	380019	129	0	0
T4	8228	0	0	0
T5	7703	0	0	0
T6	23340	0	0	0
T7	16814	4	0	0
T8	37689	3	0	0
T9	5638	0	0	0
T10	23812	4	0	0
T12	0	223	0	0
T13	0	10	0	0
T60	0	2	0	0
T61	0	3	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50807772	1042	0	0
T3	380019	19	0	0
T4	8228	0	0	0
T5	7703	0	0	0
T6	23340	0	0	0
T7	16814	0	0	0
T8	37689	3	0	0
T9	5638	0	0	0
T10	23812	0	0	0
T11	10978	0	0	0
T12	570659	14	0	0
T13	0	2	0	0
T49	0	7	0	0
T53	0	1	0	0
T56	0	6	0	0
T60	0	2	0	0
T61	0	3	0	0
T86	0	7	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50807772	12591	0	0
T1	22630	4	0	0
T2	14627	3	0	0
T3	380019	129	0	0
T4	8228	0	0	0
T5	7703	0	0	0
T6	23340	0	0	0
T7	16814	4	0	0
T8	37689	3	0	0
T9	5638	0	0	0
T10	23812	4	0	0
T12	0	223	0	0
T13	0	10	0	0
T60	0	2	0	0
T61	0	3	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50807772	1042	0	0
T3	380019	19	0	0
T4	8228	0	0	0
T5	7703	0	0	0
T6	23340	0	0	0
T7	16814	0	0	0
T8	37689	3	0	0
T9	5638	0	0	0
T10	23812	0	0	0
T11	10978	0	0	0
T12	570659	14	0	0
T13	0	2	0	0
T49	0	7	0	0
T53	0	1	0	0
T56	0	6	0	0
T60	0	2	0	0
T61	0	3	0	0
T86	0	7	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25404438	12650	0	0
T1	11316	4	0	0
T2	7311	3	0	0
T3	190008	128	0	0
T4	4113	0	0	0
T5	3852	0	0	0
T6	11667	0	0	0
T7	8405	4	0	0
T8	18844	4	0	0
T9	2819	0	0	0
T10	11906	4	0	0
T12	0	224	0	0
T13	0	11	0	0
T60	0	3	0	0
T61	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25404438	1047	0	0
T3	190008	17	0	0
T4	4113	0	0	0
T5	3852	0	0	0
T6	11667	0	0	0
T7	8405	0	0	0
T8	18844	4	0	0
T9	2819	0	0	0
T10	11906	0	0	0
T11	5488	0	0	0
T12	285364	13	0	0
T13	0	4	0	0
T49	0	8	0	0
T55	0	1	0	0
T56	0	2	0	0
T60	0	3	0	0
T61	0	4	0	0
T86	0	6	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25404438	12650	0	0
T1	11316	4	0	0
T2	7311	3	0	0
T3	190008	128	0	0
T4	4113	0	0	0
T5	3852	0	0	0
T6	11667	0	0	0
T7	8405	4	0	0
T8	18844	4	0	0
T9	2819	0	0	0
T10	11906	4	0	0
T12	0	224	0	0
T13	0	11	0	0
T60	0	3	0	0
T61	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25404438	1047	0	0
T3	190008	17	0	0
T4	4113	0	0	0
T5	3852	0	0	0
T6	11667	0	0	0
T7	8405	0	0	0
T8	18844	4	0	0
T9	2819	0	0	0
T10	11906	0	0	0
T11	5488	0	0	0
T12	285364	13	0	0
T13	0	4	0	0
T49	0	8	0	0
T55	0	1	0	0
T56	0	2	0	0
T60	0	3	0	0
T61	0	4	0	0
T86	0	6	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25404320	12692	0	0
T1	11314	4	0	0
T2	7315	3	0	0
T3	190046	130	0	0
T4	4113	0	0	0
T5	3852	0	0	0
T6	11660	0	0	0
T7	8404	4	0	0
T8	18844	4	0	0
T9	2819	0	0	0
T10	11906	4	0	0
T12	0	224	0	0
T13	0	10	0	0
T60	0	4	0	0
T61	0	5	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25404320	1082	0	0
T3	190046	19	0	0
T4	4113	0	0	0
T5	3852	0	0	0
T6	11660	0	0	0
T7	8404	0	0	0
T8	18844	4	0	0
T9	2819	0	0	0
T10	11906	0	0	0
T11	5489	0	0	0
T12	285334	14	0	0
T13	0	3	0	0
T49	0	8	0	0
T51	0	1	0	0
T55	0	1	0	0
T60	0	4	0	0
T61	0	5	0	0
T86	0	7	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25404320	12692	0	0
T1	11314	4	0	0
T2	7315	3	0	0
T3	190046	130	0	0
T4	4113	0	0	0
T5	3852	0	0	0
T6	11660	0	0	0
T7	8404	4	0	0
T8	18844	4	0	0
T9	2819	0	0	0
T10	11906	4	0	0
T12	0	224	0	0
T13	0	10	0	0
T60	0	4	0	0
T61	0	5	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25404320	1082	0	0
T3	190046	19	0	0
T4	4113	0	0	0
T5	3852	0	0	0
T6	11660	0	0	0
T7	8404	0	0	0
T8	18844	4	0	0
T9	2819	0	0	0
T10	11906	0	0	0
T11	5489	0	0	0
T12	285334	14	0	0
T13	0	3	0	0
T49	0	8	0	0
T51	0	1	0	0
T55	0	1	0	0
T60	0	4	0	0
T61	0	5	0	0
T86	0	7	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1603287	21199	0	0
T1	705	6	0	0
T2	456	6	0	0
T3	12132	225	0	0
T4	255	2	0	0
T5	240	1	0	0
T6	732	3	0	0
T7	523	6	0	0
T8	1177	8	0	0
T9	176	1	0	0
T10	744	6	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1603287	1127	0	0
T3	12132	19	0	0
T4	255	0	0	0
T5	240	0	0	0
T6	732	0	0	0
T7	523	0	0	0
T8	1177	7	0	0
T9	176	0	0	0
T10	744	0	0	0
T11	343	0	0	0
T12	18289	14	0	0
T13	0	3	0	0
T49	0	9	0	0
T53	0	1	0	0
T60	0	5	0	0
T61	0	5	0	0
T86	0	5	0	0
T87	0	23	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1603287	21199	0	0
T1	705	6	0	0
T2	456	6	0	0
T3	12132	225	0	0
T4	255	2	0	0
T5	240	1	0	0
T6	732	3	0	0
T7	523	6	0	0
T8	1177	8	0	0
T9	176	1	0	0
T10	744	6	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1603287	1127	0	0
T3	12132	19	0	0
T4	255	0	0	0
T5	240	0	0	0
T6	732	0	0	0
T7	523	0	0	0
T8	1177	7	0	0
T9	176	0	0	0
T10	744	0	0	0
T11	343	0	0	0
T12	18289	14	0	0
T13	0	3	0	0
T49	0	9	0	0
T53	0	1	0	0
T60	0	5	0	0
T61	0	5	0	0
T86	0	5	0	0
T87	0	23	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12701794	14054	0	0
T1	5654	4	0	0
T2	3658	4	0	0
T3	95022	143	0	0
T4	2055	0	0	0
T5	1924	0	0	0
T6	5832	0	0	0
T7	4202	4	0	0
T8	9422	7	0	0
T9	1408	0	0	0
T10	5954	5	0	0
T12	0	251	0	0
T13	0	12	0	0
T60	0	6	0	0
T61	0	7	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12701794	1181	0	0
T3	95022	17	0	0
T4	2055	0	0	0
T5	1924	0	0	0
T6	5832	0	0	0
T7	4202	0	0	0
T8	9422	7	0	0
T9	1408	0	0	0
T10	5954	1	0	0
T11	2744	0	0	0
T12	142673	15	0	0
T13	0	5	0	0
T49	0	9	0	0
T55	0	1	0	0
T60	0	6	0	0
T61	0	7	0	0
T86	0	7	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12701794	14054	0	0
T1	5654	4	0	0
T2	3658	4	0	0
T3	95022	143	0	0
T4	2055	0	0	0
T5	1924	0	0	0
T6	5832	0	0	0
T7	4202	4	0	0
T8	9422	7	0	0
T9	1408	0	0	0
T10	5954	5	0	0
T12	0	251	0	0
T13	0	12	0	0
T60	0	6	0	0
T61	0	7	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12701794	1181	0	0
T3	95022	17	0	0
T4	2055	0	0	0
T5	1924	0	0	0
T6	5832	0	0	0
T7	4202	0	0	0
T8	9422	7	0	0
T9	1408	0	0	0
T10	5954	1	0	0
T11	2744	0	0	0
T12	142673	15	0	0
T13	0	5	0	0
T49	0	9	0	0
T55	0	1	0	0
T60	0	6	0	0
T61	0	7	0	0
T86	0	7	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12701794	14086	0	0
T1	5654	4	0	0
T2	3658	4	0	0
T3	95022	144	0	0
T4	2055	0	0	0
T5	1924	0	0	0
T6	5832	0	0	0
T7	4202	4	0	0
T8	9422	8	0	0
T9	1408	0	0	0
T10	5954	4	0	0
T12	0	249	0	0
T13	0	12	0	0
T60	0	7	0	0
T61	0	8	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12701794	1217	0	0
T3	95022	19	0	0
T4	2055	0	0	0
T5	1924	0	0	0
T6	5832	0	0	0
T7	4202	0	0	0
T8	9422	8	0	0
T9	1408	0	0	0
T10	5954	0	0	0
T11	2744	0	0	0
T12	142673	13	0	0
T13	0	5	0	0
T36	0	12	0	0
T49	0	12	0	0
T60	0	7	0	0
T61	0	8	0	0
T86	0	5	0	0
T87	0	24	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12701794	14086	0	0
T1	5654	4	0	0
T2	3658	4	0	0
T3	95022	144	0	0
T4	2055	0	0	0
T5	1924	0	0	0
T6	5832	0	0	0
T7	4202	4	0	0
T8	9422	8	0	0
T9	1408	0	0	0
T10	5954	4	0	0
T12	0	249	0	0
T13	0	12	0	0
T60	0	7	0	0
T61	0	8	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12701794	1217	0	0
T3	95022	19	0	0
T4	2055	0	0	0
T5	1924	0	0	0
T6	5832	0	0	0
T7	4202	0	0	0
T8	9422	8	0	0
T9	1408	0	0	0
T10	5954	0	0	0
T11	2744	0	0	0
T12	142673	13	0	0
T13	0	5	0	0
T36	0	12	0	0
T49	0	12	0	0
T60	0	7	0	0
T61	0	8	0	0
T86	0	5	0	0
T87	0	24	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12701794	14140	0	0
T1	5654	5	0	0
T2	3658	4	0	0
T3	95022	144	0	0
T4	2055	0	0	0
T5	1924	0	0	0
T6	5832	0	0	0
T7	4202	4	0	0
T8	9422	9	0	0
T9	1408	0	0	0
T10	5954	4	0	0
T12	0	251	0	0
T13	0	11	0	0
T60	0	7	0	0
T61	0	9	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12701794	1270	0	0
T1	5654	1	0	0
T2	3658	0	0	0
T3	95022	18	0	0
T4	2055	0	0	0
T5	1924	0	0	0
T6	5832	0	0	0
T7	4202	0	0	0
T8	9422	9	0	0
T9	1408	0	0	0
T10	5954	0	0	0
T12	0	16	0	0
T13	0	3	0	0
T49	0	11	0	0
T53	0	1	0	0
T60	0	7	0	0
T61	0	9	0	0
T86	0	6	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12701794	14140	0	0
T1	5654	5	0	0
T2	3658	4	0	0
T3	95022	144	0	0
T4	2055	0	0	0
T5	1924	0	0	0
T6	5832	0	0	0
T7	4202	4	0	0
T8	9422	9	0	0
T9	1408	0	0	0
T10	5954	4	0	0
T12	0	251	0	0
T13	0	11	0	0
T60	0	7	0	0
T61	0	9	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12701794	1270	0	0
T1	5654	1	0	0
T2	3658	0	0	0
T3	95022	18	0	0
T4	2055	0	0	0
T5	1924	0	0	0
T6	5832	0	0	0
T7	4202	0	0	0
T8	9422	9	0	0
T9	1408	0	0	0
T10	5954	0	0	0
T12	0	16	0	0
T13	0	3	0	0
T49	0	11	0	0
T53	0	1	0	0
T60	0	7	0	0
T61	0	9	0	0
T86	0	6	0	0