Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12011775	8165	0	0
alert_regwen_rd_A	12011775	4670	0	0
cpu_regwen_rd_A	12011775	4622	0	0
sw_rst_ctrl_n_0_rd_A	12011775	9012	0	0
sw_rst_ctrl_n_1_rd_A	12011775	8769	0	0
sw_rst_ctrl_n_2_rd_A	12011775	8885	0	0
sw_rst_ctrl_n_3_rd_A	12011775	9109	0	0
sw_rst_ctrl_n_4_rd_A	12011775	8748	0	0
sw_rst_ctrl_n_5_rd_A	12011775	8885	0	0
sw_rst_ctrl_n_6_rd_A	12011775	8932	0	0
sw_rst_ctrl_n_7_rd_A	12011775	8925	0	0
sw_rst_regwen_0_rd_A	12011775	5193	0	0
sw_rst_regwen_1_rd_A	12011775	5175	0	0
sw_rst_regwen_2_rd_A	12011775	5332	0	0
sw_rst_regwen_3_rd_A	12011775	5181	0	0
sw_rst_regwen_4_rd_A	12011775	5269	0	0
sw_rst_regwen_5_rd_A	12011775	5318	0	0
sw_rst_regwen_6_rd_A	12011775	5351	0	0
sw_rst_regwen_7_rd_A	12011775	5271	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12011775	8165	0	0
T63	2377	5	0	0
T64	8757	1	0	0
T66	3460	438	0	0
T67	11037	612	0	0
T68	17687	2	0	0
T74	4103	11	0	0
T88	20058	3	0	0
T89	11411	522	0	0
T90	3494	212	0	0
T91	5871	117	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12011775	4670	0	0
T19	2578	0	0	0
T20	2897	0	0	0
T35	43259	70	0	0
T36	3367	0	0	0
T37	46475	93	0	0
T38	1592	0	0	0
T39	106963	0	0	0
T40	2921	0	0	0
T41	1478	0	0	0
T83	0	33	0	0
T96	0	49	0	0
T97	0	35	0	0
T98	0	116	0	0
T116	0	464	0	0
T117	0	74	0	0
T118	0	40	0	0
T119	0	53	0	0
T120	2250	0	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12011775	4622	0	0
T19	2578	0	0	0
T20	2897	0	0	0
T35	43259	63	0	0
T36	3367	0	0	0
T37	46475	71	0	0
T38	1592	0	0	0
T39	106963	0	0	0
T40	2921	0	0	0
T41	1478	0	0	0
T83	0	38	0	0
T96	0	58	0	0
T97	0	33	0	0
T98	0	191	0	0
T116	0	500	0	0
T117	0	35	0	0
T118	0	53	0	0
T119	0	57	0	0
T120	2250	0	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12011775	9012	0	0
T1	5322	6	0	0
T2	3318	0	0	0
T3	76223	0	0	0
T4	1990	0	0	0
T5	1834	0	0	0
T6	5480	0	0	0
T7	4010	0	0	0
T8	9331	147	0	0
T9	1366	0	0	0
T10	5615	6	0	0
T35	0	60	0	0
T37	0	100	0	0
T60	0	114	0	0
T61	0	131	0	0
T96	0	39	0	0
T121	0	96	0	0
T122	0	17	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12011775	8769	0	0
T1	5322	9	0	0
T2	3318	0	0	0
T3	76223	0	0	0
T4	1990	0	0	0
T5	1834	0	0	0
T6	5480	0	0	0
T7	4010	0	0	0
T8	9331	119	0	0
T9	1366	0	0	0
T10	5615	5	0	0
T35	0	61	0	0
T37	0	86	0	0
T60	0	141	0	0
T61	0	122	0	0
T96	0	30	0	0
T121	0	64	0	0
T122	0	9	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12011775	8885	0	0
T1	5322	5	0	0
T2	3318	0	0	0
T3	76223	0	0	0
T4	1990	0	0	0
T5	1834	0	0	0
T6	5480	0	0	0
T7	4010	0	0	0
T8	9331	127	0	0
T9	1366	0	0	0
T10	5615	11	0	0
T35	0	40	0	0
T37	0	87	0	0
T60	0	141	0	0
T61	0	133	0	0
T96	0	45	0	0
T121	0	59	0	0
T122	0	18	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12011775	9109	0	0
T1	5322	15	0	0
T2	3318	0	0	0
T3	76223	0	0	0
T4	1990	0	0	0
T5	1834	0	0	0
T6	5480	0	0	0
T7	4010	0	0	0
T8	9331	126	0	0
T9	1366	0	0	0
T10	5615	11	0	0
T35	0	77	0	0
T37	0	87	0	0
T60	0	130	0	0
T61	0	157	0	0
T96	0	42	0	0
T121	0	62	0	0
T122	0	12	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12011775	8748	0	0
T1	5322	6	0	0
T2	3318	0	0	0
T3	76223	0	0	0
T4	1990	0	0	0
T5	1834	0	0	0
T6	5480	0	0	0
T7	4010	0	0	0
T8	9331	153	0	0
T9	1366	0	0	0
T10	5615	20	0	0
T35	0	67	0	0
T37	0	104	0	0
T60	0	151	0	0
T61	0	151	0	0
T96	0	54	0	0
T121	0	55	0	0
T122	0	5	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12011775	8885	0	0
T1	5322	7	0	0
T2	3318	0	0	0
T3	76223	0	0	0
T4	1990	0	0	0
T5	1834	0	0	0
T6	5480	0	0	0
T7	4010	0	0	0
T8	9331	117	0	0
T9	1366	0	0	0
T10	5615	7	0	0
T35	0	60	0	0
T37	0	72	0	0
T60	0	110	0	0
T61	0	139	0	0
T96	0	42	0	0
T121	0	58	0	0
T122	0	26	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12011775	8932	0	0
T1	5322	8	0	0
T2	3318	0	0	0
T3	76223	0	0	0
T4	1990	0	0	0
T5	1834	0	0	0
T6	5480	0	0	0
T7	4010	0	0	0
T8	9331	139	0	0
T9	1366	0	0	0
T10	5615	18	0	0
T35	0	90	0	0
T37	0	81	0	0
T60	0	124	0	0
T61	0	135	0	0
T96	0	38	0	0
T121	0	42	0	0
T122	0	18	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12011775	8925	0	0
T1	5322	16	0	0
T2	3318	0	0	0
T3	76223	0	0	0
T4	1990	0	0	0
T5	1834	0	0	0
T6	5480	0	0	0
T7	4010	0	0	0
T8	9331	143	0	0
T9	1366	0	0	0
T10	5615	16	0	0
T35	0	64	0	0
T37	0	86	0	0
T60	0	121	0	0
T61	0	139	0	0
T96	0	37	0	0
T121	0	80	0	0
T122	0	13	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12011775	5193	0	0
T1	5322	4	0	0
T2	3318	0	0	0
T3	76223	0	0	0
T4	1990	0	0	0
T5	1834	0	0	0
T6	5480	0	0	0
T7	4010	0	0	0
T8	9331	35	0	0
T9	1366	0	0	0
T10	5615	6	0	0
T35	0	84	0	0
T37	0	90	0	0
T60	0	39	0	0
T61	0	31	0	0
T96	0	41	0	0
T123	0	4	0	0
T124	0	22	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12011775	5175	0	0
T1	5322	11	0	0
T2	3318	0	0	0
T3	76223	0	0	0
T4	1990	0	0	0
T5	1834	0	0	0
T6	5480	0	0	0
T7	4010	0	0	0
T8	9331	36	0	0
T9	1366	0	0	0
T10	5615	11	0	0
T35	0	74	0	0
T37	0	100	0	0
T60	0	44	0	0
T61	0	21	0	0
T96	0	55	0	0
T123	0	6	0	0
T124	0	30	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12011775	5332	0	0
T1	5322	2	0	0
T2	3318	0	0	0
T3	76223	0	0	0
T4	1990	0	0	0
T5	1834	0	0	0
T6	5480	0	0	0
T7	4010	0	0	0
T8	9331	38	0	0
T9	1366	0	0	0
T10	5615	17	0	0
T35	0	63	0	0
T37	0	103	0	0
T60	0	44	0	0
T61	0	33	0	0
T96	0	38	0	0
T123	0	10	0	0
T124	0	38	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12011775	5181	0	0
T8	9331	29	0	0
T9	1366	0	0	0
T10	5615	12	0	0
T11	2629	0	0	0
T12	113201	0	0	0
T13	5759	0	0	0
T14	2110	0	0	0
T35	0	62	0	0
T37	0	92	0	0
T60	8895	30	0	0
T61	9255	27	0	0
T72	1215	0	0	0
T96	0	30	0	0
T97	0	33	0	0
T123	0	7	0	0
T124	0	36	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12011775	5269	0	0
T1	5322	1	0	0
T2	3318	0	0	0
T3	76223	0	0	0
T4	1990	0	0	0
T5	1834	0	0	0
T6	5480	0	0	0
T7	4010	0	0	0
T8	9331	20	0	0
T9	1366	0	0	0
T10	5615	0	0	0
T35	0	78	0	0
T37	0	74	0	0
T60	0	19	0	0
T61	0	33	0	0
T96	0	56	0	0
T97	0	51	0	0
T123	0	14	0	0
T124	0	34	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12011775	5318	0	0
T1	5322	5	0	0
T2	3318	0	0	0
T3	76223	0	0	0
T4	1990	0	0	0
T5	1834	0	0	0
T6	5480	0	0	0
T7	4010	0	0	0
T8	9331	36	0	0
T9	1366	0	0	0
T10	5615	6	0	0
T35	0	66	0	0
T37	0	93	0	0
T60	0	30	0	0
T61	0	35	0	0
T96	0	58	0	0
T123	0	7	0	0
T124	0	44	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12011775	5351	0	0
T1	5322	7	0	0
T2	3318	0	0	0
T3	76223	0	0	0
T4	1990	0	0	0
T5	1834	0	0	0
T6	5480	0	0	0
T7	4010	0	0	0
T8	9331	22	0	0
T9	1366	0	0	0
T10	5615	8	0	0
T35	0	61	0	0
T37	0	108	0	0
T60	0	38	0	0
T61	0	21	0	0
T96	0	50	0	0
T123	0	3	0	0
T124	0	36	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12011775	5271	0	0
T1	5322	1	0	0
T2	3318	0	0	0
T3	76223	0	0	0
T4	1990	0	0	0
T5	1834	0	0	0
T6	5480	0	0	0
T7	4010	0	0	0
T8	9331	32	0	0
T9	1366	0	0	0
T10	5615	0	0	0
T35	0	92	0	0
T37	0	65	0	0
T60	0	24	0	0
T61	0	23	0	0
T96	0	29	0	0
T97	0	24	0	0
T123	0	11	0	0
T124	0	24	0	0