Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	603353	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

363278

1

T1

70

T2

123

T3

48

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	514027	1			T1	99		T2	186		T3	72
values[0x0]	226006	1			T1	54		T2	89		T3	42
values[0x1]	226598	1			T1	59		T2	104		T3	32

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	506395	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

460236

1

T1

89

T2

157

T3

62

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3231	1			T3	1		T5	13		T9	1
valid_sources[0x01]	3112	1			T5	57		T9	4		T10	75
valid_sources[0x02]	2964	1			T3	2		T5	14		T9	2
valid_sources[0x03]	5075	1			T5	7		T9	6		T10	61
valid_sources[0x04]	3107	1			T5	32		T9	3		T10	70
valid_sources[0x05]	3247	1			T5	60		T10	75		T11	76
valid_sources[0x06]	2815	1			T5	26		T9	4		T10	73
valid_sources[0x07]	3460	1			T5	45		T9	1		T10	62
valid_sources[0x08]	6444	1			T5	38		T10	80		T11	75
valid_sources[0x09]	3695	1			T5	98		T9	1		T10	65
valid_sources[0x0a]	3760	1			T5	53		T9	2		T10	72
valid_sources[0x0b]	3156	1			T3	1		T5	44		T9	1
valid_sources[0x0c]	11556	1			T5	129		T9	6		T10	82
valid_sources[0x0d]	4229	1			T5	56		T9	1		T10	89
valid_sources[0x0e]	3540	1			T5	16		T9	4		T10	67
valid_sources[0x0f]	2865	1			T5	80		T9	2		T10	79
valid_sources[0x10]	4259	1			T5	28		T9	2		T10	72
valid_sources[0x11]	6398	1			T3	3		T5	41		T9	6
valid_sources[0x12]	3197	1			T3	1		T5	20		T9	4
valid_sources[0x13]	3612	1			T3	1		T5	87		T9	3
valid_sources[0x14]	3772	1			T3	1		T5	91		T9	3
valid_sources[0x15]	3196	1			T5	84		T9	6		T10	36
valid_sources[0x16]	4836	1			T5	60		T9	1		T10	104
valid_sources[0x17]	2907	1			T5	37		T9	4		T10	84
valid_sources[0x18]	2691	1			T3	3		T5	58		T9	3
valid_sources[0x19]	4048	1			T3	1		T5	61		T9	1
valid_sources[0x1a]	6897	1			T5	12		T9	6		T10	84
valid_sources[0x1b]	5218	1			T3	1		T5	75		T9	2
valid_sources[0x1c]	3046	1			T5	40		T9	5		T10	73
valid_sources[0x1d]	3223	1			T5	23		T9	1		T10	76
valid_sources[0x1e]	3421	1			T5	14		T9	1		T10	63
valid_sources[0x1f]	3892	1			T3	1		T5	78		T9	4
valid_sources[0x20]	3344	1			T5	50		T9	4		T10	61
valid_sources[0x21]	3984	1			T5	25		T9	4		T10	69
valid_sources[0x22]	4301	1			T5	48		T9	7		T10	60
valid_sources[0x23]	3556	1			T5	43		T9	1		T10	76
valid_sources[0x24]	3769	1			T3	1		T5	24		T9	2
valid_sources[0x25]	3110	1			T3	1		T5	81		T9	1
valid_sources[0x26]	3238	1			T5	66		T9	2		T10	73
valid_sources[0x27]	3541	1			T5	31		T9	4		T10	84
valid_sources[0x28]	3165	1			T5	33		T9	4		T10	66
valid_sources[0x29]	2960	1			T5	56		T9	5		T10	70
valid_sources[0x2a]	2784	1			T5	37		T9	3		T10	75
valid_sources[0x2b]	2904	1			T3	2		T5	8		T9	4
valid_sources[0x2c]	3229	1			T3	1		T5	63		T9	4
valid_sources[0x2d]	3230	1			T3	1		T5	51		T9	3
valid_sources[0x2e]	2989	1			T3	1		T5	30		T9	4
valid_sources[0x2f]	3855	1			T5	65		T9	2		T10	93
valid_sources[0x30]	2779	1			T3	1		T5	45		T9	5
valid_sources[0x31]	3127	1			T3	3		T5	82		T9	1
valid_sources[0x32]	4035	1			T3	1		T5	79		T9	2
valid_sources[0x33]	7399	1			T5	26		T9	1		T10	69
valid_sources[0x34]	2744	1			T3	1		T5	42		T9	2
valid_sources[0x35]	2612	1			T3	3		T5	61		T9	3
valid_sources[0x36]	3474	1			T5	14		T9	1		T10	70
valid_sources[0x37]	4780	1			T5	42		T9	4		T10	91
valid_sources[0x38]	3278	1			T5	37		T9	2		T10	72
valid_sources[0x39]	3088	1			T5	119		T10	89		T11	63
valid_sources[0x3a]	5033	1			T5	56		T9	6		T10	65
valid_sources[0x3b]	3490	1			T3	1		T5	52		T9	2
valid_sources[0x3c]	3299	1			T3	3		T5	28		T9	1
valid_sources[0x3d]	6029	1			T5	33		T9	4		T10	68
valid_sources[0x3e]	3229	1			T5	63		T10	74		T11	73
valid_sources[0x3f]	3833	1			T5	30		T9	2		T10	70
valid_sources[0x40]	3227	1			T5	41		T9	1		T10	61
valid_sources[0x41]	5079	1			T5	42		T9	4		T10	90
valid_sources[0x42]	3157	1			T5	41		T6	129		T10	101
valid_sources[0x43]	4509	1			T5	121		T9	8		T10	62
valid_sources[0x44]	3098	1			T3	3		T5	44		T9	1
valid_sources[0x45]	3983	1			T3	1		T5	63		T9	3
valid_sources[0x46]	3113	1			T5	28		T9	8		T10	85
valid_sources[0x47]	4099	1			T3	1		T5	28		T9	4
valid_sources[0x48]	4456	1			T3	1		T5	66		T9	5
valid_sources[0x49]	3701	1			T3	2		T5	14		T9	8
valid_sources[0x4a]	3991	1			T3	3		T5	26		T9	3
valid_sources[0x4b]	6048	1			T3	1		T5	50		T9	2
valid_sources[0x4c]	2818	1			T3	1		T5	10		T9	1
valid_sources[0x4d]	2874	1			T5	114		T9	2		T10	90
valid_sources[0x4e]	3399	1			T3	6		T5	90		T9	6
valid_sources[0x4f]	3675	1			T3	2		T5	99		T9	3
valid_sources[0x50]	3905	1			T5	52		T9	3		T10	92
valid_sources[0x51]	3696	1			T2	379		T5	47		T9	1
valid_sources[0x52]	3226	1			T5	16		T9	6		T10	69
valid_sources[0x53]	3529	1			T3	1		T5	43		T9	2
valid_sources[0x54]	3254	1			T5	93		T9	1		T10	92
valid_sources[0x55]	4473	1			T5	26		T9	5		T10	58
valid_sources[0x56]	3635	1			T3	2		T5	17		T9	2
valid_sources[0x57]	3802	1			T3	2		T5	9		T9	4
valid_sources[0x58]	3296	1			T5	82		T9	3		T10	92
valid_sources[0x59]	4305	1			T3	1		T5	48		T9	5
valid_sources[0x5a]	3267	1			T3	1		T5	97		T9	4
valid_sources[0x5b]	4091	1			T3	2		T5	57		T9	4
valid_sources[0x5c]	4329	1			T5	32		T9	5		T10	76
valid_sources[0x5d]	3418	1			T5	60		T9	3		T10	88
valid_sources[0x5e]	3066	1			T5	42		T9	1		T10	89
valid_sources[0x5f]	3862	1			T5	86		T9	4		T10	79
valid_sources[0x60]	6995	1			T3	1		T5	83		T9	6
valid_sources[0x61]	6253	1			T3	1		T5	46		T9	4
valid_sources[0x62]	2960	1			T3	1		T5	53		T9	4
valid_sources[0x63]	3289	1			T5	25		T10	76		T11	59
valid_sources[0x64]	6375	1			T5	35		T9	2		T10	70
valid_sources[0x65]	3782	1			T5	8		T9	3		T10	77
valid_sources[0x66]	4266	1			T5	52		T9	5		T10	71
valid_sources[0x67]	5094	1			T3	1		T5	120		T9	2
valid_sources[0x68]	3122	1			T3	1		T5	61		T9	2
valid_sources[0x69]	3044	1			T3	1		T5	66		T9	7
valid_sources[0x6a]	3179	1			T5	15		T9	3		T10	71
valid_sources[0x6b]	2854	1			T3	2		T5	38		T10	84
valid_sources[0x6c]	3471	1			T5	57		T9	2		T10	86
valid_sources[0x6d]	3755	1			T4	23		T5	20		T9	5
valid_sources[0x6e]	3800	1			T5	75		T9	4		T10	77
valid_sources[0x6f]	3611	1			T3	2		T5	18		T9	1
valid_sources[0x70]	2730	1			T5	3		T9	4		T10	63
valid_sources[0x71]	7908	1			T3	1		T5	13		T9	2
valid_sources[0x72]	3730	1			T9	2		T10	77		T11	52
valid_sources[0x73]	2837	1			T5	33		T9	3		T10	59
valid_sources[0x74]	3985	1			T5	14		T9	2		T10	82
valid_sources[0x75]	3512	1			T3	2		T5	28		T9	1
valid_sources[0x76]	3827	1			T5	37		T9	1		T10	96
valid_sources[0x77]	3338	1			T3	2		T5	64		T9	7
valid_sources[0x78]	2714	1			T5	6		T9	5		T10	77
valid_sources[0x79]	3268	1			T5	61		T9	7		T10	66
valid_sources[0x7a]	3993	1			T3	1		T5	13		T9	7
valid_sources[0x7b]	2821	1			T3	1		T5	68		T9	3
valid_sources[0x7c]	2507	1			T3	1		T5	128		T9	3
valid_sources[0x7d]	3361	1			T5	64		T9	5		T10	100
valid_sources[0x7e]	3940	1			T5	27		T9	3		T10	73
valid_sources[0x7f]	3805	1			T3	1		T5	20		T9	5
valid_sources[0x80]	3205	1			T5	71		T9	3		T10	54

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

241113

1

T1

43

T2

86

T3

38

values[0x0]

all_enables

biggest_size

79637

1

T1

17

T2

25

T3

9

values[0x1]

all_enables

biggest_size

42528

1

T1

10

T2

12

T3

1