Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T5,T10,T11

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T5,T7,T8
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	53074442	8396	0	0
CascadeEffAonToRstPorAboveRise_A	53074442	8396	0	0
CascadeEffAonToRstPorIoAboveFall_A	50949654	8396	0	0
CascadeEffAonToRstPorIoAboveRise_A	50949654	8396	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	25475299	8396	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	25475299	8396	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12737431	8396	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12737431	8396	0	0
CascadeEffAonToRstPorUcbAboveFall_A	25475552	8396	0	0
CascadeEffAonToRstPorUcbAboveRise_A	25475552	8396	0	0
CascadeLcToLcAboveFall_A	53074442	21229	0	0
CascadeLcToLcAboveRise_A	53074442	21229	0	0
CascadeLcToLcAonAboveFall_A	1608232	21229	0	0
CascadeLcToLcAonAboveRise_A	1608232	21229	0	0
CascadeLcToLcShadowedAboveFall_A	53074442	21229	0	0
CascadeLcToLcShadowedAboveRise_A	53074442	21229	0	0
CascadePorToAonAboveFall_A	1608232	6770	0	0
CascadeSysToSysAboveFall_A	53074442	21229	0	0
CascadeSysToSysAboveRise_A	53074442	21229	0	0
ScanRstToAonRise_A	1608232	195	0	0
StablePorToAonRise_A	1608232	8396	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11286985	21229	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11286985	21229	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11286985	21229	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11286985	21229	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12737431	21229	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12737431	21229	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11286985	21229	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11286985	21229	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11286985	21229	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11286985	21229	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53074442	8396	0	0
T1	14518	2	0	0
T2	20553	2	0	0
T3	15747	1	0	0
T4	7451	1	0	0
T5	402430	84	0	0
T6	11926	1	0	0
T7	18252	2	0	0
T8	24282	8	0	0
T9	13157	1	0	0
T10	607358	128	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53074442	8396	0	0
T1	14518	2	0	0
T2	20553	2	0	0
T3	15747	1	0	0
T4	7451	1	0	0
T5	402430	84	0	0
T6	11926	1	0	0
T7	18252	2	0	0
T8	24282	8	0	0
T9	13157	1	0	0
T10	607358	128	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50949654	8396	0	0
T1	13940	2	0	0
T2	19731	2	0	0
T3	15115	1	0	0
T4	7153	1	0	0
T5	386353	84	0	0
T6	11449	1	0	0
T7	17522	2	0	0
T8	23308	8	0	0
T9	12630	1	0	0
T10	583047	128	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50949654	8396	0	0
T1	13940	2	0	0
T2	19731	2	0	0
T3	15115	1	0	0
T4	7153	1	0	0
T5	386353	84	0	0
T6	11449	1	0	0
T7	17522	2	0	0
T8	23308	8	0	0
T9	12630	1	0	0
T10	583047	128	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25475299	8396	0	0
T1	6969	2	0	0
T2	9864	2	0	0
T3	7558	1	0	0
T4	3575	1	0	0
T5	193142	84	0	0
T6	5725	1	0	0
T7	8760	2	0	0
T8	11661	8	0	0
T9	6315	1	0	0
T10	291549	128	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25475299	8396	0	0
T1	6969	2	0	0
T2	9864	2	0	0
T3	7558	1	0	0
T4	3575	1	0	0
T5	193142	84	0	0
T6	5725	1	0	0
T7	8760	2	0	0
T8	11661	8	0	0
T9	6315	1	0	0
T10	291549	128	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12737431	8396	0	0
T1	3484	2	0	0
T2	4930	2	0	0
T3	3778	1	0	0
T4	1786	1	0	0
T5	96577	84	0	0
T6	2862	1	0	0
T7	4379	2	0	0
T8	5827	8	0	0
T9	3157	1	0	0
T10	145783	128	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12737431	8396	0	0
T1	3484	2	0	0
T2	4930	2	0	0
T3	3778	1	0	0
T4	1786	1	0	0
T5	96577	84	0	0
T6	2862	1	0	0
T7	4379	2	0	0
T8	5827	8	0	0
T9	3157	1	0	0
T10	145783	128	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25475552	8396	0	0
T1	6969	2	0	0
T2	9864	2	0	0
T3	7557	1	0	0
T4	3576	1	0	0
T5	193174	84	0	0
T6	5724	1	0	0
T7	8761	2	0	0
T8	11656	8	0	0
T9	6315	1	0	0
T10	291550	128	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25475552	8396	0	0
T1	6969	2	0	0
T2	9864	2	0	0
T3	7557	1	0	0
T4	3576	1	0	0
T5	193174	84	0	0
T6	5724	1	0	0
T7	8761	2	0	0
T8	11656	8	0	0
T9	6315	1	0	0
T10	291550	128	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53074442	21229	0	0
T1	14518	6	0	0
T2	20553	6	0	0
T3	15747	9	0	0
T4	7451	1	0	0
T5	402430	222	0	0
T6	11926	8	0	0
T7	18252	2	0	0
T8	24282	8	0	0
T9	13157	1	0	0
T10	607358	360	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53074442	21229	0	0
T1	14518	6	0	0
T2	20553	6	0	0
T3	15747	9	0	0
T4	7451	1	0	0
T5	402430	222	0	0
T6	11926	8	0	0
T7	18252	2	0	0
T8	24282	8	0	0
T9	13157	1	0	0
T10	607358	360	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1608232	21229	0	0
T1	434	6	0	0
T2	615	6	0	0
T3	471	9	0	0
T4	223	1	0	0
T5	12316	222	0	0
T6	357	8	0	0
T7	545	2	0	0
T8	731	8	0	0
T9	394	1	0	0
T10	18621	360	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1608232	21229	0	0
T1	434	6	0	0
T2	615	6	0	0
T3	471	9	0	0
T4	223	1	0	0
T5	12316	222	0	0
T6	357	8	0	0
T7	545	2	0	0
T8	731	8	0	0
T9	394	1	0	0
T10	18621	360	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53074442	21229	0	0
T1	14518	6	0	0
T2	20553	6	0	0
T3	15747	9	0	0
T4	7451	1	0	0
T5	402430	222	0	0
T6	11926	8	0	0
T7	18252	2	0	0
T8	24282	8	0	0
T9	13157	1	0	0
T10	607358	360	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53074442	21229	0	0
T1	14518	6	0	0
T2	20553	6	0	0
T3	15747	9	0	0
T4	7451	1	0	0
T5	402430	222	0	0
T6	11926	8	0	0
T7	18252	2	0	0
T8	24282	8	0	0
T9	13157	1	0	0
T10	607358	360	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1608232	6770	0	0
T1	434	1	0	0
T2	615	1	0	0
T3	471	1	0	0
T4	223	1	0	0
T5	12316	51	0	0
T6	357	1	0	0
T7	545	15	0	0
T8	731	8	0	0
T9	394	1	0	0
T10	18621	63	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53074442	21229	0	0
T1	14518	6	0	0
T2	20553	6	0	0
T3	15747	9	0	0
T4	7451	1	0	0
T5	402430	222	0	0
T6	11926	8	0	0
T7	18252	2	0	0
T8	24282	8	0	0
T9	13157	1	0	0
T10	607358	360	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53074442	21229	0	0
T1	14518	6	0	0
T2	20553	6	0	0
T3	15747	9	0	0
T4	7451	1	0	0
T5	402430	222	0	0
T6	11926	8	0	0
T7	18252	2	0	0
T8	24282	8	0	0
T9	13157	1	0	0
T10	607358	360	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1608232	195	0	0
T5	12316	2	0	0
T6	357	0	0	0
T7	545	0	0	0
T8	731	0	0	0
T9	394	0	0	0
T10	18621	10	0	0
T11	25856	6	0	0
T12	342	0	0	0
T13	4748	1	0	0
T23	401	0	0	0
T40	0	1	0	0
T69	0	2	0	0
T82	0	1	0	0
T85	0	3	0	0
T117	0	1	0	0
T118	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1608232	8396	0	0
T1	434	2	0	0
T2	615	2	0	0
T3	471	1	0	0
T4	223	1	0	0
T5	12316	84	0	0
T6	357	1	0	0
T7	545	2	0	0
T8	731	8	0	0
T9	394	1	0	0
T10	18621	128	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11286985	21229	0	0
T1	3293	6	0	0
T2	4738	6	0	0
T3	3135	9	0	0
T4	1745	1	0	0
T5	77691	222	0	0
T6	2371	8	0	0
T7	4289	2	0	0
T8	5282	8	0	0
T9	3066	1	0	0
T10	116359	360	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11286985	21229	0	0
T1	3293	6	0	0
T2	4738	6	0	0
T3	3135	9	0	0
T4	1745	1	0	0
T5	77691	222	0	0
T6	2371	8	0	0
T7	4289	2	0	0
T8	5282	8	0	0
T9	3066	1	0	0
T10	116359	360	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11286985	21229	0	0
T1	3293	6	0	0
T2	4738	6	0	0
T3	3135	9	0	0
T4	1745	1	0	0
T5	77691	222	0	0
T6	2371	8	0	0
T7	4289	2	0	0
T8	5282	8	0	0
T9	3066	1	0	0
T10	116359	360	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11286985	21229	0	0
T1	3293	6	0	0
T2	4738	6	0	0
T3	3135	9	0	0
T4	1745	1	0	0
T5	77691	222	0	0
T6	2371	8	0	0
T7	4289	2	0	0
T8	5282	8	0	0
T9	3066	1	0	0
T10	116359	360	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12737431	21229	0	0
T1	3484	6	0	0
T2	4930	6	0	0
T3	3778	9	0	0
T4	1786	1	0	0
T5	96577	222	0	0
T6	2862	8	0	0
T7	4379	2	0	0
T8	5827	8	0	0
T9	3157	1	0	0
T10	145783	360	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12737431	21229	0	0
T1	3484	6	0	0
T2	4930	6	0	0
T3	3778	9	0	0
T4	1786	1	0	0
T5	96577	222	0	0
T6	2862	8	0	0
T7	4379	2	0	0
T8	5827	8	0	0
T9	3157	1	0	0
T10	145783	360	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11286985	21229	0	0
T1	3293	6	0	0
T2	4738	6	0	0
T3	3135	9	0	0
T4	1745	1	0	0
T5	77691	222	0	0
T6	2371	8	0	0
T7	4289	2	0	0
T8	5282	8	0	0
T9	3066	1	0	0
T10	116359	360	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11286985	21229	0	0
T1	3293	6	0	0
T2	4738	6	0	0
T3	3135	9	0	0
T4	1745	1	0	0
T5	77691	222	0	0
T6	2371	8	0	0
T7	4289	2	0	0
T8	5282	8	0	0
T9	3066	1	0	0
T10	116359	360	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11286985	21229	0	0
T1	3293	6	0	0
T2	4738	6	0	0
T3	3135	9	0	0
T4	1745	1	0	0
T5	77691	222	0	0
T6	2371	8	0	0
T7	4289	2	0	0
T8	5282	8	0	0
T9	3066	1	0	0
T10	116359	360	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11286985	21229	0	0
T1	3293	6	0	0
T2	4738	6	0	0
T3	3135	9	0	0
T4	1745	1	0	0
T5	77691	222	0	0
T6	2371	8	0	0
T7	4289	2	0	0
T8	5282	8	0	0
T9	3066	1	0	0
T10	116359	360	0	0