Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T5
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T9,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T9,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T5,T9
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T9,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T9,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T9,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T5,T9,T10
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12737431	13800	0	0
gen_assertions[0].RstEnOn_A	12737431	1167	0	0
gen_assertions[0].RstNOff_A	12737431	13800	0	0
gen_assertions[0].RstNOn_A	12737431	1167	0	0
gen_assertions[1].RstEnOff_A	50949654	12554	0	0
gen_assertions[1].RstEnOn_A	50949654	1138	0	0
gen_assertions[1].RstNOff_A	50949654	12554	0	0
gen_assertions[1].RstNOn_A	50949654	1138	0	0
gen_assertions[2].RstEnOff_A	25475299	12581	0	0
gen_assertions[2].RstEnOn_A	25475299	1117	0	0
gen_assertions[2].RstNOff_A	25475299	12581	0	0
gen_assertions[2].RstNOn_A	25475299	1117	0	0
gen_assertions[3].RstEnOff_A	25475552	12616	0	0
gen_assertions[3].RstEnOn_A	25475552	1147	0	0
gen_assertions[3].RstNOff_A	25475552	12616	0	0
gen_assertions[3].RstNOn_A	25475552	1147	0	0
gen_assertions[4].RstEnOff_A	1608232	21092	0	0
gen_assertions[4].RstEnOn_A	1608232	1231	0	0
gen_assertions[4].RstNOff_A	1608232	21092	0	0
gen_assertions[4].RstNOn_A	1608232	1231	0	0
gen_assertions[5].RstEnOff_A	12737431	14043	0	0
gen_assertions[5].RstEnOn_A	12737431	1259	0	0
gen_assertions[5].RstNOff_A	12737431	14043	0	0
gen_assertions[5].RstNOn_A	12737431	1259	0	0
gen_assertions[6].RstEnOff_A	12737431	14096	0	0
gen_assertions[6].RstEnOn_A	12737431	1305	0	0
gen_assertions[6].RstNOff_A	12737431	14096	0	0
gen_assertions[6].RstNOn_A	12737431	1305	0	0
gen_assertions[7].RstEnOff_A	12737431	14151	0	0
gen_assertions[7].RstEnOn_A	12737431	1359	0	0
gen_assertions[7].RstNOff_A	12737431	14151	0	0
gen_assertions[7].RstNOn_A	12737431	1359	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12737431	13800	0	0
T1	3484	4	0	0
T2	4930	5	0	0
T3	3778	8	0	0
T4	1786	0	0	0
T5	96577	158	0	0
T6	2862	7	0	0
T7	4379	0	0	0
T8	5827	0	0	0
T9	3157	1	0	0
T10	145783	246	0	0
T11	0	230	0	0
T12	0	5	0	0
T23	0	3	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12737431	1167	0	0
T2	4930	1	0	0
T3	3778	1	0	0
T4	1786	0	0	0
T5	96577	21	0	0
T6	2862	1	0	0
T7	4379	0	0	0
T8	5827	0	0	0
T9	3157	1	0	0
T10	145783	14	0	0
T11	204007	17	0	0
T12	0	1	0	0
T23	0	3	0	0
T25	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12737431	13800	0	0
T1	3484	4	0	0
T2	4930	5	0	0
T3	3778	8	0	0
T4	1786	0	0	0
T5	96577	158	0	0
T6	2862	7	0	0
T7	4379	0	0	0
T8	5827	0	0	0
T9	3157	1	0	0
T10	145783	246	0	0
T11	0	230	0	0
T12	0	5	0	0
T23	0	3	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12737431	1167	0	0
T2	4930	1	0	0
T3	3778	1	0	0
T4	1786	0	0	0
T5	96577	21	0	0
T6	2862	1	0	0
T7	4379	0	0	0
T8	5827	0	0	0
T9	3157	1	0	0
T10	145783	14	0	0
T11	204007	17	0	0
T12	0	1	0	0
T23	0	3	0	0
T25	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50949654	12554	0	0
T1	13940	4	0	0
T2	19731	4	0	0
T3	15115	7	0	0
T4	7153	0	0	0
T5	386353	138	0	0
T6	11449	5	0	0
T7	17522	0	0	0
T8	23308	0	0	0
T9	12630	5	0	0
T10	583047	219	0	0
T11	0	208	0	0
T12	0	4	0	0
T23	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50949654	1138	0	0
T5	386353	16	0	0
T6	11449	0	0	0
T7	17522	0	0	0
T8	23308	0	0	0
T9	12630	5	0	0
T10	583047	14	0	0
T11	815990	15	0	0
T12	11028	1	0	0
T13	149095	0	0	0
T23	12860	4	0	0
T37	0	7	0	0
T69	0	44	0	0
T70	0	2	0	0
T71	0	3	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50949654	12554	0	0
T1	13940	4	0	0
T2	19731	4	0	0
T3	15115	7	0	0
T4	7153	0	0	0
T5	386353	138	0	0
T6	11449	5	0	0
T7	17522	0	0	0
T8	23308	0	0	0
T9	12630	5	0	0
T10	583047	219	0	0
T11	0	208	0	0
T12	0	4	0	0
T23	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	50949654	1138	0	0
T5	386353	16	0	0
T6	11449	0	0	0
T7	17522	0	0	0
T8	23308	0	0	0
T9	12630	5	0	0
T10	583047	14	0	0
T11	815990	15	0	0
T12	11028	1	0	0
T13	149095	0	0	0
T23	12860	4	0	0
T37	0	7	0	0
T69	0	44	0	0
T70	0	2	0	0
T71	0	3	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25475299	12581	0	0
T1	6969	4	0	0
T2	9864	4	0	0
T3	7558	7	0	0
T4	3575	0	0	0
T5	193142	139	0	0
T6	5725	5	0	0
T7	8760	0	0	0
T8	11661	0	0	0
T9	6315	6	0	0
T10	291549	224	0	0
T11	0	211	0	0
T12	0	3	0	0
T23	0	3	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25475299	1117	0	0
T5	193142	17	0	0
T6	5725	0	0	0
T7	8760	0	0	0
T8	11661	0	0	0
T9	6315	6	0	0
T10	291549	19	0	0
T11	407996	16	0	0
T12	5516	0	0	0
T13	74551	0	0	0
T23	6429	3	0	0
T37	0	10	0	0
T49	0	7	0	0
T69	0	37	0	0
T70	0	4	0	0
T72	0	15	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25475299	12581	0	0
T1	6969	4	0	0
T2	9864	4	0	0
T3	7558	7	0	0
T4	3575	0	0	0
T5	193142	139	0	0
T6	5725	5	0	0
T7	8760	0	0	0
T8	11661	0	0	0
T9	6315	6	0	0
T10	291549	224	0	0
T11	0	211	0	0
T12	0	3	0	0
T23	0	3	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25475299	1117	0	0
T5	193142	17	0	0
T6	5725	0	0	0
T7	8760	0	0	0
T8	11661	0	0	0
T9	6315	6	0	0
T10	291549	19	0	0
T11	407996	16	0	0
T12	5516	0	0	0
T13	74551	0	0	0
T23	6429	3	0	0
T37	0	10	0	0
T49	0	7	0	0
T69	0	37	0	0
T70	0	4	0	0
T72	0	15	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25475552	12616	0	0
T1	6969	4	0	0
T2	9864	5	0	0
T3	7557	7	0	0
T4	3576	0	0	0
T5	193174	138	0	0
T6	5724	5	0	0
T7	8761	0	0	0
T8	11656	0	0	0
T9	6315	6	0	0
T10	291550	221	0	0
T11	0	211	0	0
T12	0	3	0	0
T23	0	5	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25475552	1147	0	0
T2	9864	1	0	0
T3	7557	0	0	0
T4	3576	0	0	0
T5	193174	16	0	0
T6	5724	0	0	0
T7	8761	0	0	0
T8	11656	0	0	0
T9	6315	6	0	0
T10	291550	16	0	0
T11	408005	16	0	0
T23	0	5	0	0
T37	0	7	0	0
T41	0	1	0	0
T69	0	42	0	0
T70	0	5	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25475552	12616	0	0
T1	6969	4	0	0
T2	9864	5	0	0
T3	7557	7	0	0
T4	3576	0	0	0
T5	193174	138	0	0
T6	5724	5	0	0
T7	8761	0	0	0
T8	11656	0	0	0
T9	6315	6	0	0
T10	291550	221	0	0
T11	0	211	0	0
T12	0	3	0	0
T23	0	5	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	25475552	1147	0	0
T2	9864	1	0	0
T3	7557	0	0	0
T4	3576	0	0	0
T5	193174	16	0	0
T6	5724	0	0	0
T7	8761	0	0	0
T8	11656	0	0	0
T9	6315	6	0	0
T10	291550	16	0	0
T11	408005	16	0	0
T23	0	5	0	0
T37	0	7	0	0
T41	0	1	0	0
T69	0	42	0	0
T70	0	5	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1608232	21092	0	0
T1	434	5	0	0
T2	615	6	0	0
T3	471	9	0	0
T4	223	1	0	0
T5	12316	234	0	0
T6	357	8	0	0
T7	545	2	0	0
T8	731	2	0	0
T9	394	9	0	0
T10	18621	367	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1608232	1231	0	0
T5	12316	20	0	0
T6	357	0	0	0
T7	545	0	0	0
T8	731	0	0	0
T9	394	8	0	0
T10	18621	16	0	0
T11	25856	14	0	0
T12	342	1	0	0
T13	4748	0	0	0
T23	401	7	0	0
T37	0	12	0	0
T49	0	8	0	0
T69	0	45	0	0
T70	0	6	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1608232	21092	0	0
T1	434	5	0	0
T2	615	6	0	0
T3	471	9	0	0
T4	223	1	0	0
T5	12316	234	0	0
T6	357	8	0	0
T7	545	2	0	0
T8	731	2	0	0
T9	394	9	0	0
T10	18621	367	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1608232	1231	0	0
T5	12316	20	0	0
T6	357	0	0	0
T7	545	0	0	0
T8	731	0	0	0
T9	394	8	0	0
T10	18621	16	0	0
T11	25856	14	0	0
T12	342	1	0	0
T13	4748	0	0	0
T23	401	7	0	0
T37	0	12	0	0
T49	0	8	0	0
T69	0	45	0	0
T70	0	6	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12737431	14043	0	0
T1	3484	4	0	0
T2	4930	4	0	0
T3	3778	8	0	0
T4	1786	0	0	0
T5	96577	157	0	0
T6	2862	7	0	0
T7	4379	0	0	0
T8	5827	0	0	0
T9	3157	9	0	0
T10	145783	249	0	0
T11	0	223	0	0
T12	0	4	0	0
T23	0	9	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12737431	1259	0	0
T5	96577	20	0	0
T6	2862	0	0	0
T7	4379	0	0	0
T8	5827	0	0	0
T9	3157	9	0	0
T10	145783	17	0	0
T11	204007	10	0	0
T12	2758	0	0	0
T13	37278	0	0	0
T23	3213	9	0	0
T37	0	12	0	0
T49	0	11	0	0
T69	0	36	0	0
T70	0	6	0	0
T73	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12737431	14043	0	0
T1	3484	4	0	0
T2	4930	4	0	0
T3	3778	8	0	0
T4	1786	0	0	0
T5	96577	157	0	0
T6	2862	7	0	0
T7	4379	0	0	0
T8	5827	0	0	0
T9	3157	9	0	0
T10	145783	249	0	0
T11	0	223	0	0
T12	0	4	0	0
T23	0	9	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12737431	1259	0	0
T5	96577	20	0	0
T6	2862	0	0	0
T7	4379	0	0	0
T8	5827	0	0	0
T9	3157	9	0	0
T10	145783	17	0	0
T11	204007	10	0	0
T12	2758	0	0	0
T13	37278	0	0	0
T23	3213	9	0	0
T37	0	12	0	0
T49	0	11	0	0
T69	0	36	0	0
T70	0	6	0	0
T73	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12737431	14096	0	0
T1	3484	4	0	0
T2	4930	4	0	0
T3	3778	8	0	0
T4	1786	0	0	0
T5	96577	153	0	0
T6	2862	7	0	0
T7	4379	0	0	0
T8	5827	0	0	0
T9	3157	10	0	0
T10	145783	250	0	0
T11	0	230	0	0
T12	0	4	0	0
T23	0	10	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12737431	1305	0	0
T5	96577	15	0	0
T6	2862	0	0	0
T7	4379	0	0	0
T8	5827	0	0	0
T9	3157	10	0	0
T10	145783	18	0	0
T11	204007	17	0	0
T12	2758	0	0	0
T13	37278	0	0	0
T23	3213	10	0	0
T25	0	1	0	0
T37	0	11	0	0
T41	0	1	0	0
T69	0	38	0	0
T70	0	8	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12737431	14096	0	0
T1	3484	4	0	0
T2	4930	4	0	0
T3	3778	8	0	0
T4	1786	0	0	0
T5	96577	153	0	0
T6	2862	7	0	0
T7	4379	0	0	0
T8	5827	0	0	0
T9	3157	10	0	0
T10	145783	250	0	0
T11	0	230	0	0
T12	0	4	0	0
T23	0	10	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12737431	1305	0	0
T5	96577	15	0	0
T6	2862	0	0	0
T7	4379	0	0	0
T8	5827	0	0	0
T9	3157	10	0	0
T10	145783	18	0	0
T11	204007	17	0	0
T12	2758	0	0	0
T13	37278	0	0	0
T23	3213	10	0	0
T25	0	1	0	0
T37	0	11	0	0
T41	0	1	0	0
T69	0	38	0	0
T70	0	8	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12737431	14151	0	0
T1	3484	4	0	0
T2	4930	4	0	0
T3	3778	8	0	0
T4	1786	0	0	0
T5	96577	155	0	0
T6	2862	7	0	0
T7	4379	0	0	0
T8	5827	0	0	0
T9	3157	11	0	0
T10	145783	253	0	0
T11	0	229	0	0
T12	0	4	0	0
T23	0	10	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12737431	1359	0	0
T5	96577	17	0	0
T6	2862	0	0	0
T7	4379	0	0	0
T8	5827	0	0	0
T9	3157	11	0	0
T10	145783	21	0	0
T11	204007	16	0	0
T12	2758	0	0	0
T13	37278	0	0	0
T23	3213	10	0	0
T37	0	14	0	0
T49	0	12	0	0
T69	0	44	0	0
T70	0	9	0	0
T72	0	15	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12737431	14151	0	0
T1	3484	4	0	0
T2	4930	4	0	0
T3	3778	8	0	0
T4	1786	0	0	0
T5	96577	155	0	0
T6	2862	7	0	0
T7	4379	0	0	0
T8	5827	0	0	0
T9	3157	11	0	0
T10	145783	253	0	0
T11	0	229	0	0
T12	0	4	0	0
T23	0	10	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12737431	1359	0	0
T5	96577	17	0	0
T6	2862	0	0	0
T7	4379	0	0	0
T8	5827	0	0	0
T9	3157	11	0	0
T10	145783	21	0	0
T11	204007	16	0	0
T12	2758	0	0	0
T13	37278	0	0	0
T23	3213	10	0	0
T37	0	14	0	0
T49	0	12	0	0
T69	0	44	0	0
T70	0	9	0	0
T72	0	15	0	0