Unified Coverage Report :: Module :: rstmgr_por

Module : rstmgr_por

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.74	91.67	91.67			88.89

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_por.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon	90.74	91.67	91.67			88.89

---

Module Instance : tb.dut.gen_rst_por_aon[0].gen_rst_por_aon_normal.u_rst_por_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.74	91.67	91.67			88.89

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.65	95.83	97.44			93.33	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_rst_clean_mux	100.00	100.00	100.00				100.00
u_rst_flop	100.00	100.00				100.00
u_rst_out_mux	100.00	100.00	100.00				100.00
u_rst_root_mux	100.00	100.00	100.00				100.00
u_rst_sync	100.00	100.00				100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_por

	Line No.	Total	Covered	Percent
TOTAL		12	11	91.67
ALWAYS	49	3	3	100.00
CONT_ASSIGN	68	1	1	100.00
CONT_ASSIGN	69	1	1	100.00
CONT_ASSIGN	74	1	1	100.00
ALWAYS	78	6	5	83.33

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_por.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_por.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
49	1	1
50	1	1
52	1	1
68	1	1
69	1	1
74	1	1
78	1	1
79	1	1
80	1	1
81	0	1
82	1	1
83	1	1
			MISSING_ELSE

---

Cond Coverage for Module : rstmgr_por

	Total	Covered	Percent
Conditions	12	11	91.67
Logical	12	11	91.67
Non-Logical	0	0
Event	0	0

 LINE       69
 EXPRESSION (rst_stable & ((!rst_no)))
             -----1----   -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       74
 EXPRESSION (((~rst_stable)) ? 1'b0 : ((cnt_en & (cnt == StretchCount[(CtrWidth - 1):0])) ? 1'b1 : rst_nq))
             -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       74
 SUB-EXPRESSION ((cnt_en & (cnt == StretchCount[(CtrWidth - 1):0])) ? 1'b1 : rst_nq)
                 -------------------------1------------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       74
 SUB-EXPRESSION (cnt_en & (cnt == StretchCount[(CtrWidth - 1):0]))
                 ---1--   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       74
 SUB-EXPRESSION (cnt == StretchCount[(CtrWidth - 1):0])
                -------------------1-------------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

Branch Coverage for Module : rstmgr_por

	Line No.	Total	Covered	Percent
Branches		9	8	88.89
TERNARY	74	3	3	100.00
IF	49	2	2	100.00
IF	78	4	3	75.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_por.sv' or '../src/lowrisc_opentitan_top_earlgrey_rstmgr_0.1/rtl/rstmgr_por.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	74	((~rst_stable)) ? 
-2-:	74	((cnt_en & (cnt == StretchCount[(CtrWidth - 1):0]))) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	49	if ((!rst_root_n))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	78	if ((!rst_clean_n))
-2-:	80	if ((!rst_stable))
-3-:	82	if (cnt_en)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Covered	T1,T2,T3