Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12026353	9782	0	0
alert_regwen_rd_A	12026353	4399	0	0
cpu_regwen_rd_A	12026353	4340	0	0
sw_rst_ctrl_n_0_rd_A	12026353	8723	0	0
sw_rst_ctrl_n_1_rd_A	12026353	9078	0	0
sw_rst_ctrl_n_2_rd_A	12026353	8787	0	0
sw_rst_ctrl_n_3_rd_A	12026353	9093	0	0
sw_rst_ctrl_n_4_rd_A	12026353	8682	0	0
sw_rst_ctrl_n_5_rd_A	12026353	8814	0	0
sw_rst_ctrl_n_6_rd_A	12026353	8868	0	0
sw_rst_ctrl_n_7_rd_A	12026353	9049	0	0
sw_rst_regwen_0_rd_A	12026353	4819	0	0
sw_rst_regwen_1_rd_A	12026353	4510	0	0
sw_rst_regwen_2_rd_A	12026353	4949	0	0
sw_rst_regwen_3_rd_A	12026353	4732	0	0
sw_rst_regwen_4_rd_A	12026353	4655	0	0
sw_rst_regwen_5_rd_A	12026353	4848	0	0
sw_rst_regwen_6_rd_A	12026353	4621	0	0
sw_rst_regwen_7_rd_A	12026353	4700	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12026353	9782	0	0
T56	21935	1	0	0
T57	2814	102	0	0
T58	4634	29	0	0
T59	15235	720	0	0
T60	4743	614	0	0
T74	11657	4	0	0
T75	3162	13	0	0
T76	20814	3	0	0
T77	3101	229	0	0
T100	9186	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12026353	4399	0	0
T15	3103	0	0	0
T42	25964	0	0	0
T46	5472	0	0	0
T47	2508	0	0	0
T61	5110	0	0	0
T62	356918	0	0	0
T68	4419	0	0	0
T69	211443	193	0	0
T71	2522	0	0	0
T81	43625	113	0	0
T84	0	49	0	0
T87	0	207	0	0
T88	0	184	0	0
T108	0	96	0	0
T109	0	83	0	0
T110	0	18	0	0
T111	0	55	0	0
T112	0	27	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12026353	4340	0	0
T15	3103	0	0	0
T42	25964	0	0	0
T46	5472	0	0	0
T47	2508	0	0	0
T61	5110	0	0	0
T62	356918	0	0	0
T68	4419	0	0	0
T69	211443	270	0	0
T71	2522	0	0	0
T81	43625	119	0	0
T84	0	54	0	0
T87	0	243	0	0
T88	0	216	0	0
T108	0	137	0	0
T109	0	85	0	0
T110	0	41	0	0
T111	0	52	0	0
T112	0	45	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12026353	8723	0	0
T3	3135	12	0	0
T4	1745	0	0	0
T5	77691	0	0	0
T6	2371	0	0	0
T7	4289	0	0	0
T8	5282	0	0	0
T9	3066	0	0	0
T10	116359	0	0	0
T11	178096	0	0	0
T12	2517	0	0	0
T25	0	6	0	0
T49	0	107	0	0
T69	0	758	0	0
T81	0	70	0	0
T84	0	131	0	0
T87	0	495	0	0
T113	0	4	0	0
T114	0	16	0	0
T115	0	2	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12026353	9078	0	0
T3	3135	26	0	0
T4	1745	0	0	0
T5	77691	0	0	0
T6	2371	0	0	0
T7	4289	0	0	0
T8	5282	0	0	0
T9	3066	0	0	0
T10	116359	0	0	0
T11	178096	0	0	0
T12	2517	0	0	0
T25	0	7	0	0
T49	0	133	0	0
T69	0	813	0	0
T81	0	127	0	0
T84	0	89	0	0
T113	0	14	0	0
T114	0	10	0	0
T115	0	4	0	0
T116	0	13	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12026353	8787	0	0
T3	3135	33	0	0
T4	1745	0	0	0
T5	77691	0	0	0
T6	2371	0	0	0
T7	4289	0	0	0
T8	5282	0	0	0
T9	3066	0	0	0
T10	116359	0	0	0
T11	178096	0	0	0
T12	2517	0	0	0
T25	0	9	0	0
T49	0	141	0	0
T69	0	853	0	0
T81	0	85	0	0
T84	0	114	0	0
T113	0	9	0	0
T114	0	26	0	0
T115	0	2	0	0
T116	0	12	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12026353	9093	0	0
T3	3135	35	0	0
T4	1745	0	0	0
T5	77691	0	0	0
T6	2371	0	0	0
T7	4289	0	0	0
T8	5282	0	0	0
T9	3066	0	0	0
T10	116359	0	0	0
T11	178096	0	0	0
T12	2517	0	0	0
T25	0	8	0	0
T49	0	84	0	0
T69	0	840	0	0
T81	0	67	0	0
T84	0	111	0	0
T113	0	6	0	0
T114	0	20	0	0
T115	0	8	0	0
T116	0	13	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12026353	8682	0	0
T3	3135	27	0	0
T4	1745	0	0	0
T5	77691	0	0	0
T6	2371	0	0	0
T7	4289	0	0	0
T8	5282	0	0	0
T9	3066	0	0	0
T10	116359	0	0	0
T11	178096	0	0	0
T12	2517	0	0	0
T25	0	6	0	0
T49	0	96	0	0
T69	0	887	0	0
T81	0	94	0	0
T84	0	105	0	0
T113	0	13	0	0
T114	0	28	0	0
T115	0	5	0	0
T116	0	2	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12026353	8814	0	0
T3	3135	29	0	0
T4	1745	0	0	0
T5	77691	0	0	0
T6	2371	0	0	0
T7	4289	0	0	0
T8	5282	0	0	0
T9	3066	0	0	0
T10	116359	0	0	0
T11	178096	0	0	0
T12	2517	0	0	0
T25	0	19	0	0
T49	0	139	0	0
T69	0	840	0	0
T81	0	108	0	0
T84	0	93	0	0
T113	0	12	0	0
T114	0	13	0	0
T115	0	3	0	0
T116	0	2	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12026353	8868	0	0
T3	3135	43	0	0
T4	1745	0	0	0
T5	77691	0	0	0
T6	2371	0	0	0
T7	4289	0	0	0
T8	5282	0	0	0
T9	3066	0	0	0
T10	116359	0	0	0
T11	178096	0	0	0
T12	2517	0	0	0
T25	0	5	0	0
T49	0	105	0	0
T69	0	895	0	0
T81	0	112	0	0
T84	0	98	0	0
T87	0	467	0	0
T113	0	14	0	0
T114	0	14	0	0
T116	0	8	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12026353	9049	0	0
T3	3135	22	0	0
T4	1745	0	0	0
T5	77691	0	0	0
T6	2371	0	0	0
T7	4289	0	0	0
T8	5282	0	0	0
T9	3066	0	0	0
T10	116359	0	0	0
T11	178096	0	0	0
T12	2517	0	0	0
T25	0	5	0	0
T49	0	104	0	0
T69	0	814	0	0
T81	0	85	0	0
T84	0	96	0	0
T113	0	7	0	0
T114	0	22	0	0
T115	0	5	0	0
T116	0	15	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12026353	4819	0	0
T14	3062	0	0	0
T25	5428	2	0	0
T35	1848	0	0	0
T36	3866	0	0	0
T37	3514	0	0	0
T38	2487	0	0	0
T39	2246	0	0	0
T40	29470	0	0	0
T41	2394	0	0	0
T49	0	22	0	0
T69	0	268	0	0
T70	2853	0	0	0
T81	0	87	0	0
T84	0	76	0	0
T87	0	183	0	0
T88	0	227	0	0
T113	0	17	0	0
T114	0	3	0	0
T116	0	6	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12026353	4510	0	0
T15	3103	0	0	0
T42	25964	0	0	0
T46	5472	0	0	0
T47	2508	0	0	0
T49	0	12	0	0
T61	5110	0	0	0
T62	356918	0	0	0
T68	4419	0	0	0
T69	211443	280	0	0
T71	2522	0	0	0
T81	43625	80	0	0
T84	0	81	0	0
T87	0	203	0	0
T88	0	213	0	0
T108	0	123	0	0
T113	0	2	0	0
T114	0	11	0	0
T116	0	2	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12026353	4949	0	0
T14	3062	0	0	0
T25	5428	13	0	0
T35	1848	0	0	0
T36	3866	0	0	0
T37	3514	0	0	0
T38	2487	0	0	0
T39	2246	0	0	0
T40	29470	0	0	0
T41	2394	0	0	0
T49	0	11	0	0
T69	0	253	0	0
T70	2853	0	0	0
T81	0	86	0	0
T84	0	82	0	0
T87	0	263	0	0
T88	0	213	0	0
T113	0	9	0	0
T114	0	6	0	0
T116	0	5	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12026353	4732	0	0
T14	3062	0	0	0
T25	5428	4	0	0
T35	1848	0	0	0
T36	3866	0	0	0
T37	3514	0	0	0
T38	2487	0	0	0
T39	2246	0	0	0
T40	29470	0	0	0
T41	2394	0	0	0
T49	0	9	0	0
T69	0	243	0	0
T70	2853	0	0	0
T81	0	112	0	0
T84	0	71	0	0
T87	0	254	0	0
T88	0	184	0	0
T108	0	90	0	0
T109	0	125	0	0
T113	0	4	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12026353	4655	0	0
T14	3062	0	0	0
T25	5428	1	0	0
T35	1848	0	0	0
T36	3866	0	0	0
T37	3514	0	0	0
T38	2487	0	0	0
T39	2246	0	0	0
T40	29470	0	0	0
T41	2394	0	0	0
T49	0	25	0	0
T69	0	222	0	0
T70	2853	0	0	0
T81	0	53	0	0
T84	0	59	0	0
T87	0	189	0	0
T88	0	212	0	0
T108	0	101	0	0
T113	0	3	0	0
T114	0	11	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12026353	4848	0	0
T15	3103	0	0	0
T42	25964	0	0	0
T46	5472	0	0	0
T47	2508	0	0	0
T49	0	5	0	0
T61	5110	0	0	0
T62	356918	0	0	0
T68	4419	0	0	0
T69	211443	233	0	0
T71	2522	0	0	0
T81	43625	92	0	0
T84	0	52	0	0
T87	0	210	0	0
T88	0	208	0	0
T108	0	125	0	0
T109	0	97	0	0
T113	0	11	0	0
T116	0	3	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12026353	4621	0	0
T14	3062	0	0	0
T25	5428	7	0	0
T35	1848	0	0	0
T36	3866	0	0	0
T37	3514	0	0	0
T38	2487	0	0	0
T39	2246	0	0	0
T40	29470	0	0	0
T41	2394	0	0	0
T49	0	25	0	0
T69	0	213	0	0
T70	2853	0	0	0
T81	0	76	0	0
T84	0	86	0	0
T87	0	242	0	0
T88	0	176	0	0
T108	0	149	0	0
T113	0	7	0	0
T114	0	6	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12026353	4700	0	0
T14	3062	0	0	0
T25	5428	11	0	0
T35	1848	0	0	0
T36	3866	0	0	0
T37	3514	0	0	0
T38	2487	0	0	0
T39	2246	0	0	0
T40	29470	0	0	0
T41	2394	0	0	0
T49	0	12	0	0
T69	0	223	0	0
T70	2853	0	0	0
T81	0	98	0	0
T84	0	77	0	0
T87	0	239	0	0
T88	0	236	0	0
T113	0	10	0	0
T114	0	5	0	0
T116	0	6	0	0