Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	580252	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

348830

1

T1

120

T2

308

T3

71

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	494753	1			T1	186		T2	467		T3	99
values[0x0]	217418	1			T1	101		T2	219		T3	53
values[0x1]	216911	1			T1	92		T2	202		T3	60

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	486854	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

442228

1

T1

153

T2

399

T3

95

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	3457	1			T6	12		T12	1		T23	7
valid_sources[0x01]	3935	1			T6	9		T11	1		T12	1
valid_sources[0x02]	6392	1			T6	16		T11	1		T12	4
valid_sources[0x03]	3496	1			T6	7		T11	1		T12	2
valid_sources[0x04]	3696	1			T3	3		T6	10		T7	6
valid_sources[0x05]	3312	1			T6	9		T11	3		T23	16
valid_sources[0x06]	4929	1			T1	2		T3	1		T6	13
valid_sources[0x07]	2723	1			T6	7		T11	1		T12	1
valid_sources[0x08]	3711	1			T3	2		T6	12		T8	113
valid_sources[0x09]	3140	1			T6	16		T11	4		T12	1
valid_sources[0x0a]	2946	1			T6	14		T12	1		T23	22
valid_sources[0x0b]	2858	1			T1	6		T3	1		T6	14
valid_sources[0x0c]	3005	1			T2	78		T3	2		T6	8
valid_sources[0x0d]	4343	1			T2	10		T3	2		T6	14
valid_sources[0x0e]	4078	1			T3	1		T6	12		T12	1
valid_sources[0x0f]	3211	1			T2	33		T3	1		T6	16
valid_sources[0x10]	3610	1			T3	1		T6	10		T11	1
valid_sources[0x11]	3588	1			T1	4		T2	28		T3	1
valid_sources[0x12]	4329	1			T1	4		T6	13		T11	3
valid_sources[0x13]	3306	1			T3	1		T6	14		T11	1
valid_sources[0x14]	3051	1			T6	5		T12	1		T23	28
valid_sources[0x15]	2988	1			T3	4		T6	13		T7	2
valid_sources[0x16]	3116	1			T3	1		T6	6		T11	2
valid_sources[0x17]	3925	1			T1	16		T3	2		T6	19
valid_sources[0x18]	3035	1			T3	1		T6	10		T12	2
valid_sources[0x19]	3375	1			T3	4		T6	5		T7	1
valid_sources[0x1a]	3298	1			T6	9		T11	5		T12	1
valid_sources[0x1b]	4350	1			T6	17		T7	3		T11	1
valid_sources[0x1c]	4651	1			T1	8		T3	1		T6	11
valid_sources[0x1d]	3333	1			T3	1		T6	13		T10	113
valid_sources[0x1e]	5216	1			T3	2		T6	8		T10	65
valid_sources[0x1f]	4783	1			T3	3		T6	7		T7	1
valid_sources[0x20]	3548	1			T6	14		T10	11		T11	1
valid_sources[0x21]	3321	1			T3	1		T6	15		T11	2
valid_sources[0x22]	3273	1			T6	19		T23	26		T24	78
valid_sources[0x23]	3661	1			T3	3		T6	16		T23	16
valid_sources[0x24]	3696	1			T6	18		T23	30		T24	79
valid_sources[0x25]	3531	1			T6	9		T11	6		T12	3
valid_sources[0x26]	3828	1			T3	2		T6	16		T7	2
valid_sources[0x27]	2795	1			T6	13		T7	4		T11	1
valid_sources[0x28]	3062	1			T6	14		T11	2		T23	23
valid_sources[0x29]	3282	1			T3	1		T6	16		T7	1
valid_sources[0x2a]	3365	1			T3	1		T6	5		T10	156
valid_sources[0x2b]	3796	1			T1	8		T6	12		T12	2
valid_sources[0x2c]	4306	1			T1	18		T3	1		T6	19
valid_sources[0x2d]	3099	1			T3	1		T6	6		T11	6
valid_sources[0x2e]	5598	1			T6	10		T12	1		T23	18
valid_sources[0x2f]	3287	1			T1	1		T6	15		T7	3
valid_sources[0x30]	4620	1			T3	1		T6	9		T11	1
valid_sources[0x31]	3319	1			T3	4		T6	14		T7	3
valid_sources[0x32]	3183	1			T1	1		T6	12		T11	2
valid_sources[0x33]	3426	1			T6	14		T12	2		T23	24
valid_sources[0x34]	2855	1			T1	15		T3	2		T6	10
valid_sources[0x35]	3347	1			T3	4		T6	12		T7	4
valid_sources[0x36]	3033	1			T6	3		T11	1		T12	1
valid_sources[0x37]	3157	1			T6	11		T8	55		T11	1
valid_sources[0x38]	3504	1			T6	13		T10	112		T11	2
valid_sources[0x39]	3407	1			T6	17		T10	198		T11	1
valid_sources[0x3a]	9565	1			T3	1		T6	10		T11	1
valid_sources[0x3b]	6972	1			T6	11		T7	3		T23	23
valid_sources[0x3c]	3241	1			T3	3		T6	14		T11	3
valid_sources[0x3d]	3211	1			T6	9		T23	29		T24	66
valid_sources[0x3e]	3535	1			T6	13		T8	198		T11	4
valid_sources[0x3f]	3084	1			T6	11		T7	3		T11	7
valid_sources[0x40]	4306	1			T3	1		T6	15		T11	1
valid_sources[0x41]	3030	1			T3	2		T6	16		T11	1
valid_sources[0x42]	3716	1			T1	31		T3	3		T6	15
valid_sources[0x43]	4859	1			T6	13		T11	3		T12	2
valid_sources[0x44]	3325	1			T6	14		T10	70		T23	15
valid_sources[0x45]	3219	1			T6	10		T11	2		T23	13
valid_sources[0x46]	3384	1			T6	13		T11	3		T23	18
valid_sources[0x47]	2822	1			T6	17		T23	16		T24	70
valid_sources[0x48]	3240	1			T6	14		T7	6		T11	2
valid_sources[0x49]	3872	1			T1	3		T3	1		T6	13
valid_sources[0x4a]	3509	1			T6	17		T11	1		T12	3
valid_sources[0x4b]	3770	1			T3	1		T6	15		T7	11
valid_sources[0x4c]	3335	1			T6	10		T23	20		T24	67
valid_sources[0x4d]	4801	1			T6	13		T7	5		T11	2
valid_sources[0x4e]	2807	1			T3	3		T6	14		T23	22
valid_sources[0x4f]	3445	1			T3	2		T6	13		T11	2
valid_sources[0x50]	3242	1			T6	15		T11	3		T23	12
valid_sources[0x51]	3485	1			T6	11		T11	6		T23	20
valid_sources[0x52]	3352	1			T6	10		T23	31		T24	75
valid_sources[0x53]	2966	1			T1	14		T3	2		T6	11
valid_sources[0x54]	3065	1			T3	3		T6	15		T11	3
valid_sources[0x55]	3062	1			T1	3		T3	1		T6	14
valid_sources[0x56]	3361	1			T6	12		T10	70		T12	1
valid_sources[0x57]	2925	1			T3	1		T6	11		T11	1
valid_sources[0x58]	3204	1			T3	1		T6	14		T11	1
valid_sources[0x59]	3178	1			T3	2		T6	11		T12	1
valid_sources[0x5a]	2527	1			T3	2		T6	13		T12	1
valid_sources[0x5b]	2814	1			T6	7		T12	1		T23	19
valid_sources[0x5c]	3840	1			T6	15		T11	1		T23	17
valid_sources[0x5d]	3238	1			T2	104		T3	1		T6	14
valid_sources[0x5e]	3385	1			T6	16		T8	113		T11	2
valid_sources[0x5f]	3464	1			T1	2		T3	1		T6	9
valid_sources[0x60]	3386	1			T3	2		T6	13		T11	2
valid_sources[0x61]	3018	1			T1	22		T6	14		T11	1
valid_sources[0x62]	3333	1			T6	12		T11	3		T12	1
valid_sources[0x63]	3294	1			T6	8		T7	5		T12	1
valid_sources[0x64]	3889	1			T2	30		T3	2		T6	7
valid_sources[0x65]	3812	1			T6	9		T7	7		T23	21
valid_sources[0x66]	3968	1			T6	7		T23	24		T24	64
valid_sources[0x67]	3078	1			T3	2		T6	17		T23	22
valid_sources[0x68]	3506	1			T3	1		T6	14		T11	1
valid_sources[0x69]	3695	1			T1	3		T6	18		T11	12
valid_sources[0x6a]	3476	1			T1	3		T6	22		T11	2
valid_sources[0x6b]	2829	1			T6	9		T11	9		T12	1
valid_sources[0x6c]	3022	1			T3	1		T6	20		T11	1
valid_sources[0x6d]	2973	1			T3	1		T6	8		T7	2
valid_sources[0x6e]	3622	1			T3	1		T6	11		T8	242
valid_sources[0x6f]	4436	1			T1	7		T2	65		T6	6
valid_sources[0x70]	9476	1			T3	1		T5	3200		T6	10
valid_sources[0x71]	4688	1			T6	13		T8	307		T12	1
valid_sources[0x72]	4263	1			T1	14		T6	10		T12	1
valid_sources[0x73]	4140	1			T3	3		T6	22		T10	231
valid_sources[0x74]	3968	1			T6	24		T7	13		T12	2
valid_sources[0x75]	3858	1			T3	1		T6	4		T11	1
valid_sources[0x76]	2801	1			T3	1		T6	15		T12	1
valid_sources[0x77]	2969	1			T3	1		T6	18		T23	20
valid_sources[0x78]	3318	1			T3	1		T6	10		T11	1
valid_sources[0x79]	3601	1			T3	1		T6	13		T11	1
valid_sources[0x7a]	3126	1			T3	1		T6	18		T11	4
valid_sources[0x7b]	3038	1			T3	1		T6	7		T12	1
valid_sources[0x7c]	2910	1			T1	14		T3	1		T6	10
valid_sources[0x7d]	3651	1			T2	59		T6	11		T12	1
valid_sources[0x7e]	4133	1			T3	4		T6	19		T11	1
valid_sources[0x7f]	6635	1			T6	19		T7	2		T11	1
valid_sources[0x80]	3179	1			T3	3		T6	9		T7	4

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

231958

1

T1

77

T2

219

T3

49

values[0x0]

all_enables

biggest_size

76187

1

T1

32

T2

62

T3

16

values[0x1]

all_enables

biggest_size

40685

1

T1

11

T2

27

T3

6