Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T7
0	1	Covered	T1,T8,T10
1	0	Covered	T8,T10,T23

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T1,T3,T7
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	51204452	8218	0	0
CascadeEffAonToRstPorAboveRise_A	51204452	8218	0	0
CascadeEffAonToRstPorIoAboveFall_A	49155059	8218	0	0
CascadeEffAonToRstPorIoAboveRise_A	49155059	8218	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	24578004	8218	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	24578004	8218	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	12288830	8218	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	12288830	8218	0	0
CascadeEffAonToRstPorUcbAboveFall_A	24578481	8218	0	0
CascadeEffAonToRstPorUcbAboveRise_A	24578481	8218	0	0
CascadeLcToLcAboveFall_A	51204452	20704	0	0
CascadeLcToLcAboveRise_A	51204452	20704	0	0
CascadeLcToLcAonAboveFall_A	1550951	20704	0	0
CascadeLcToLcAonAboveRise_A	1550951	20704	0	0
CascadeLcToLcShadowedAboveFall_A	51204452	20704	0	0
CascadeLcToLcShadowedAboveRise_A	51204452	20704	0	0
CascadePorToAonAboveFall_A	1550951	6614	0	0
CascadeSysToSysAboveFall_A	51204452	20704	0	0
CascadeSysToSysAboveRise_A	51204452	20704	0	0
ScanRstToAonRise_A	1550951	212	0	0
StablePorToAonRise_A	1550951	8218	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	10908564	20704	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	10908564	20704	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	10908564	20704	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	10908564	20704	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	12288830	20704	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	12288830	20704	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	10908564	20704	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	10908564	20704	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	10908564	20704	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	10908564	20704	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51204452	8218	0	0
T1	19892	2	0	0
T2	40103	1	0	0
T3	10782	2	0	0
T4	24332	8	0	0
T5	233558	27	0	0
T6	122358	27	0	0
T7	18349	2	0	0
T8	77090	16	0	0
T9	8484	2	0	0
T10	303432	30	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51204452	8218	0	0
T1	19892	2	0	0
T2	40103	1	0	0
T3	10782	2	0	0
T4	24332	8	0	0
T5	233558	27	0	0
T6	122358	27	0	0
T7	18349	2	0	0
T8	77090	16	0	0
T9	8484	2	0	0
T10	303432	30	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49155059	8218	0	0
T1	19089	2	0	0
T2	38496	1	0	0
T3	10354	2	0	0
T4	23339	8	0	0
T5	224250	27	0	0
T6	117461	27	0	0
T7	17614	2	0	0
T8	74006	16	0	0
T9	8145	2	0	0
T10	291292	30	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49155059	8218	0	0
T1	19089	2	0	0
T2	38496	1	0	0
T3	10354	2	0	0
T4	23339	8	0	0
T5	224250	27	0	0
T6	117461	27	0	0
T7	17614	2	0	0
T8	74006	16	0	0
T9	8145	2	0	0
T10	291292	30	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24578004	8218	0	0
T1	9546	2	0	0
T2	19248	1	0	0
T3	5174	2	0	0
T4	11683	8	0	0
T5	112110	27	0	0
T6	58735	27	0	0
T7	8806	2	0	0
T8	37011	16	0	0
T9	4072	2	0	0
T10	145650	30	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24578004	8218	0	0
T1	9546	2	0	0
T2	19248	1	0	0
T3	5174	2	0	0
T4	11683	8	0	0
T5	112110	27	0	0
T6	58735	27	0	0
T7	8806	2	0	0
T8	37011	16	0	0
T9	4072	2	0	0
T10	145650	30	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12288830	8218	0	0
T1	4771	2	0	0
T2	9623	1	0	0
T3	2586	2	0	0
T4	5839	8	0	0
T5	56062	27	0	0
T6	29354	27	0	0
T7	4401	2	0	0
T8	18504	16	0	0
T9	2035	2	0	0
T10	72827	30	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12288830	8218	0	0
T1	4771	2	0	0
T2	9623	1	0	0
T3	2586	2	0	0
T4	5839	8	0	0
T5	56062	27	0	0
T6	29354	27	0	0
T7	4401	2	0	0
T8	18504	16	0	0
T9	2035	2	0	0
T10	72827	30	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24578481	8218	0	0
T1	9548	2	0	0
T2	19248	1	0	0
T3	5175	2	0	0
T4	11674	8	0	0
T5	112106	27	0	0
T6	58723	27	0	0
T7	8807	2	0	0
T8	37002	16	0	0
T9	4072	2	0	0
T10	145650	30	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24578481	8218	0	0
T1	9548	2	0	0
T2	19248	1	0	0
T3	5175	2	0	0
T4	11674	8	0	0
T5	112106	27	0	0
T6	58723	27	0	0
T7	8807	2	0	0
T8	37002	16	0	0
T9	4072	2	0	0
T10	145650	30	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51204452	20704	0	0
T1	19892	6	0	0
T2	40103	1	0	0
T3	10782	6	0	0
T4	24332	8	0	0
T5	233558	102	0	0
T6	122358	102	0	0
T7	18349	6	0	0
T8	77090	45	0	0
T9	8484	2	0	0
T10	303432	116	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51204452	20704	0	0
T1	19892	6	0	0
T2	40103	1	0	0
T3	10782	6	0	0
T4	24332	8	0	0
T5	233558	102	0	0
T6	122358	102	0	0
T7	18349	6	0	0
T8	77090	45	0	0
T9	8484	2	0	0
T10	303432	116	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1550951	20704	0	0
T1	595	6	0	0
T2	1202	1	0	0
T3	322	6	0	0
T4	731	8	0	0
T5	7022	102	0	0
T6	3685	102	0	0
T7	548	6	0	0
T8	2345	45	0	0
T9	252	2	0	0
T10	9288	116	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1550951	20704	0	0
T1	595	6	0	0
T2	1202	1	0	0
T3	322	6	0	0
T4	731	8	0	0
T5	7022	102	0	0
T6	3685	102	0	0
T7	548	6	0	0
T8	2345	45	0	0
T9	252	2	0	0
T10	9288	116	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51204452	20704	0	0
T1	19892	6	0	0
T2	40103	1	0	0
T3	10782	6	0	0
T4	24332	8	0	0
T5	233558	102	0	0
T6	122358	102	0	0
T7	18349	6	0	0
T8	77090	45	0	0
T9	8484	2	0	0
T10	303432	116	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51204452	20704	0	0
T1	19892	6	0	0
T2	40103	1	0	0
T3	10782	6	0	0
T4	24332	8	0	0
T5	233558	102	0	0
T6	122358	102	0	0
T7	18349	6	0	0
T8	77090	45	0	0
T9	8484	2	0	0
T10	303432	116	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1550951	6614	0	0
T1	595	1	0	0
T2	1202	1	0	0
T3	322	1	0	0
T4	731	8	0	0
T5	7022	27	0	0
T6	3685	27	0	0
T7	548	1	0	0
T8	2345	12	0	0
T9	252	3	0	0
T10	9288	15	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51204452	20704	0	0
T1	19892	6	0	0
T2	40103	1	0	0
T3	10782	6	0	0
T4	24332	8	0	0
T5	233558	102	0	0
T6	122358	102	0	0
T7	18349	6	0	0
T8	77090	45	0	0
T9	8484	2	0	0
T10	303432	116	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	51204452	20704	0	0
T1	19892	6	0	0
T2	40103	1	0	0
T3	10782	6	0	0
T4	24332	8	0	0
T5	233558	102	0	0
T6	122358	102	0	0
T7	18349	6	0	0
T8	77090	45	0	0
T9	8484	2	0	0
T10	303432	116	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1550951	212	0	0
T10	9288	1	0	0
T11	528	0	0	0
T12	461	0	0	0
T22	733	0	0	0
T23	5591	2	0	0
T24	30396	8	0	0
T25	369	0	0	0
T26	452	0	0	0
T27	543	0	0	0
T77	0	1	0	0
T78	523	0	0	0
T83	0	7	0	0
T93	0	3	0	0
T95	0	1	0	0
T97	0	2	0	0
T130	0	1	0	0
T131	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1550951	8218	0	0
T1	595	2	0	0
T2	1202	1	0	0
T3	322	2	0	0
T4	731	8	0	0
T5	7022	27	0	0
T6	3685	27	0	0
T7	548	2	0	0
T8	2345	16	0	0
T9	252	2	0	0
T10	9288	30	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10908564	20704	0	0
T1	4626	6	0	0
T2	9605	1	0	0
T3	2392	6	0	0
T4	5485	8	0	0
T5	53089	102	0	0
T6	26004	102	0	0
T7	4112	6	0	0
T8	14646	45	0	0
T9	1920	2	0	0
T10	63172	116	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10908564	20704	0	0
T1	4626	6	0	0
T2	9605	1	0	0
T3	2392	6	0	0
T4	5485	8	0	0
T5	53089	102	0	0
T6	26004	102	0	0
T7	4112	6	0	0
T8	14646	45	0	0
T9	1920	2	0	0
T10	63172	116	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10908564	20704	0	0
T1	4626	6	0	0
T2	9605	1	0	0
T3	2392	6	0	0
T4	5485	8	0	0
T5	53089	102	0	0
T6	26004	102	0	0
T7	4112	6	0	0
T8	14646	45	0	0
T9	1920	2	0	0
T10	63172	116	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10908564	20704	0	0
T1	4626	6	0	0
T2	9605	1	0	0
T3	2392	6	0	0
T4	5485	8	0	0
T5	53089	102	0	0
T6	26004	102	0	0
T7	4112	6	0	0
T8	14646	45	0	0
T9	1920	2	0	0
T10	63172	116	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12288830	20704	0	0
T1	4771	6	0	0
T2	9623	1	0	0
T3	2586	6	0	0
T4	5839	8	0	0
T5	56062	102	0	0
T6	29354	102	0	0
T7	4401	6	0	0
T8	18504	45	0	0
T9	2035	2	0	0
T10	72827	116	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12288830	20704	0	0
T1	4771	6	0	0
T2	9623	1	0	0
T3	2586	6	0	0
T4	5839	8	0	0
T5	56062	102	0	0
T6	29354	102	0	0
T7	4401	6	0	0
T8	18504	45	0	0
T9	2035	2	0	0
T10	72827	116	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10908564	20704	0	0
T1	4626	6	0	0
T2	9605	1	0	0
T3	2392	6	0	0
T4	5485	8	0	0
T5	53089	102	0	0
T6	26004	102	0	0
T7	4112	6	0	0
T8	14646	45	0	0
T9	1920	2	0	0
T10	63172	116	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10908564	20704	0	0
T1	4626	6	0	0
T2	9605	1	0	0
T3	2392	6	0	0
T4	5485	8	0	0
T5	53089	102	0	0
T6	26004	102	0	0
T7	4112	6	0	0
T8	14646	45	0	0
T9	1920	2	0	0
T10	63172	116	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10908564	20704	0	0
T1	4626	6	0	0
T2	9605	1	0	0
T3	2392	6	0	0
T4	5485	8	0	0
T5	53089	102	0	0
T6	26004	102	0	0
T7	4112	6	0	0
T8	14646	45	0	0
T9	1920	2	0	0
T10	63172	116	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10908564	20704	0	0
T1	4626	6	0	0
T2	9605	1	0	0
T3	2392	6	0	0
T4	5485	8	0	0
T5	53089	102	0	0
T6	26004	102	0	0
T7	4112	6	0	0
T8	14646	45	0	0
T9	1920	2	0	0
T10	63172	116	0	0