Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T10,T11
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T10,T11
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T10,T11
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T10,T23
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T10,T23
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T10,T23
1	0	Covered	T1,T3,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T3,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	12288830	13294	0	0
gen_assertions[0].RstEnOn_A	12288830	989	0	0
gen_assertions[0].RstNOff_A	12288830	13294	0	0
gen_assertions[0].RstNOn_A	12288830	989	0	0
gen_assertions[1].RstEnOff_A	49155059	12037	0	0
gen_assertions[1].RstEnOn_A	49155059	966	0	0
gen_assertions[1].RstNOff_A	49155059	12037	0	0
gen_assertions[1].RstNOn_A	49155059	966	0	0
gen_assertions[2].RstEnOff_A	24578004	12085	0	0
gen_assertions[2].RstEnOn_A	24578004	958	0	0
gen_assertions[2].RstNOff_A	24578004	12085	0	0
gen_assertions[2].RstNOn_A	24578004	958	0	0
gen_assertions[3].RstEnOff_A	24578481	12142	0	0
gen_assertions[3].RstEnOn_A	24578481	1008	0	0
gen_assertions[3].RstNOff_A	24578481	12142	0	0
gen_assertions[3].RstNOn_A	24578481	1008	0	0
gen_assertions[4].RstEnOff_A	1550951	20401	0	0
gen_assertions[4].RstEnOn_A	1550951	1037	0	0
gen_assertions[4].RstNOff_A	1550951	20401	0	0
gen_assertions[4].RstNOn_A	1550951	1037	0	0
gen_assertions[5].RstEnOff_A	12288830	13553	0	0
gen_assertions[5].RstEnOn_A	12288830	1101	0	0
gen_assertions[5].RstNOff_A	12288830	13553	0	0
gen_assertions[5].RstNOn_A	12288830	1101	0	0
gen_assertions[6].RstEnOff_A	12288830	13597	0	0
gen_assertions[6].RstEnOn_A	12288830	1138	0	0
gen_assertions[6].RstNOff_A	12288830	13597	0	0
gen_assertions[6].RstNOn_A	12288830	1138	0	0
gen_assertions[7].RstEnOff_A	12288830	13641	0	0
gen_assertions[7].RstEnOn_A	12288830	1200	0	0
gen_assertions[7].RstNOff_A	12288830	13641	0	0
gen_assertions[7].RstNOn_A	12288830	1200	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12288830	13294	0	0
T1	4771	4	0	0
T2	9623	4	0	0
T3	2586	4	0	0
T4	5839	0	0	0
T5	56062	75	0	0
T6	29354	75	0	0
T7	4401	4	0	0
T8	18504	29	0	0
T9	2035	0	0	0
T10	72827	97	0	0
T11	0	19	0	0
T12	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12288830	989	0	0
T2	9623	4	0	0
T3	2586	0	0	0
T4	5839	0	0	0
T5	56062	0	0	0
T6	29354	0	0	0
T7	4401	0	0	0
T8	18504	0	0	0
T9	2035	0	0	0
T10	72827	12	0	0
T11	4241	8	0	0
T23	0	1	0	0
T24	0	21	0	0
T25	0	1	0	0
T26	0	7	0	0
T41	0	1	0	0
T42	0	8	0	0
T43	0	2	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12288830	13294	0	0
T1	4771	4	0	0
T2	9623	4	0	0
T3	2586	4	0	0
T4	5839	0	0	0
T5	56062	75	0	0
T6	29354	75	0	0
T7	4401	4	0	0
T8	18504	29	0	0
T9	2035	0	0	0
T10	72827	97	0	0
T11	0	19	0	0
T12	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12288830	989	0	0
T2	9623	4	0	0
T3	2586	0	0	0
T4	5839	0	0	0
T5	56062	0	0	0
T6	29354	0	0	0
T7	4401	0	0	0
T8	18504	0	0	0
T9	2035	0	0	0
T10	72827	12	0	0
T11	4241	8	0	0
T23	0	1	0	0
T24	0	21	0	0
T25	0	1	0	0
T26	0	7	0	0
T41	0	1	0	0
T42	0	8	0	0
T43	0	2	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49155059	12037	0	0
T1	19089	4	0	0
T2	38496	4	0	0
T3	10354	4	0	0
T4	23339	0	0	0
T5	224250	67	0	0
T6	117461	67	0	0
T7	17614	4	0	0
T8	74006	25	0	0
T9	8145	0	0	0
T10	291292	89	0	0
T11	0	17	0	0
T12	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49155059	966	0	0
T2	38496	4	0	0
T3	10354	0	0	0
T4	23339	0	0	0
T5	224250	0	0	0
T6	117461	0	0	0
T7	17614	0	0	0
T8	74006	0	0	0
T9	8145	0	0	0
T10	291292	10	0	0
T11	16968	4	0	0
T23	0	1	0	0
T24	0	27	0	0
T25	0	3	0	0
T26	0	6	0	0
T41	0	2	0	0
T42	0	7	0	0
T80	0	3	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49155059	12037	0	0
T1	19089	4	0	0
T2	38496	4	0	0
T3	10354	4	0	0
T4	23339	0	0	0
T5	224250	67	0	0
T6	117461	67	0	0
T7	17614	4	0	0
T8	74006	25	0	0
T9	8145	0	0	0
T10	291292	89	0	0
T11	0	17	0	0
T12	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	49155059	966	0	0
T2	38496	4	0	0
T3	10354	0	0	0
T4	23339	0	0	0
T5	224250	0	0	0
T6	117461	0	0	0
T7	17614	0	0	0
T8	74006	0	0	0
T9	8145	0	0	0
T10	291292	10	0	0
T11	16968	4	0	0
T23	0	1	0	0
T24	0	27	0	0
T25	0	3	0	0
T26	0	6	0	0
T41	0	2	0	0
T42	0	7	0	0
T80	0	3	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24578004	12085	0	0
T1	9546	4	0	0
T2	19248	6	0	0
T3	5174	4	0	0
T4	11683	0	0	0
T5	112110	67	0	0
T6	58735	67	0	0
T7	8806	4	0	0
T8	37011	25	0	0
T9	4072	0	0	0
T10	145650	89	0	0
T11	0	17	0	0
T12	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24578004	958	0	0
T2	19248	6	0	0
T3	5174	0	0	0
T4	11683	0	0	0
T5	112110	0	0	0
T6	58735	0	0	0
T7	8806	0	0	0
T8	37011	0	0	0
T9	4072	0	0	0
T10	145650	9	0	0
T11	8484	1	0	0
T23	0	1	0	0
T24	0	24	0	0
T25	0	3	0	0
T26	0	1	0	0
T41	0	3	0	0
T42	0	8	0	0
T81	0	1	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24578004	12085	0	0
T1	9546	4	0	0
T2	19248	6	0	0
T3	5174	4	0	0
T4	11683	0	0	0
T5	112110	67	0	0
T6	58735	67	0	0
T7	8806	4	0	0
T8	37011	25	0	0
T9	4072	0	0	0
T10	145650	89	0	0
T11	0	17	0	0
T12	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24578004	958	0	0
T2	19248	6	0	0
T3	5174	0	0	0
T4	11683	0	0	0
T5	112110	0	0	0
T6	58735	0	0	0
T7	8806	0	0	0
T8	37011	0	0	0
T9	4072	0	0	0
T10	145650	9	0	0
T11	8484	1	0	0
T23	0	1	0	0
T24	0	24	0	0
T25	0	3	0	0
T26	0	1	0	0
T41	0	3	0	0
T42	0	8	0	0
T81	0	1	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24578481	12142	0	0
T1	9548	4	0	0
T2	19248	5	0	0
T3	5175	4	0	0
T4	11674	0	0	0
T5	112106	67	0	0
T6	58723	67	0	0
T7	8807	4	0	0
T8	37002	25	0	0
T9	4072	0	0	0
T10	145650	91	0	0
T11	0	17	0	0
T12	0	4	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24578481	1008	0	0
T2	19248	5	0	0
T3	5175	0	0	0
T4	11674	0	0	0
T5	112106	0	0	0
T6	58723	0	0	0
T7	8807	0	0	0
T8	37002	0	0	0
T9	4072	0	0	0
T10	145650	11	0	0
T11	8483	0	0	0
T23	0	1	0	0
T24	0	26	0	0
T25	0	6	0	0
T41	0	4	0	0
T42	0	10	0	0
T80	0	5	0	0
T82	0	1	0	0
T83	0	8	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24578481	12142	0	0
T1	9548	4	0	0
T2	19248	5	0	0
T3	5175	4	0	0
T4	11674	0	0	0
T5	112106	67	0	0
T6	58723	67	0	0
T7	8807	4	0	0
T8	37002	25	0	0
T9	4072	0	0	0
T10	145650	91	0	0
T11	0	17	0	0
T12	0	4	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	24578481	1008	0	0
T2	19248	5	0	0
T3	5175	0	0	0
T4	11674	0	0	0
T5	112106	0	0	0
T6	58723	0	0	0
T7	8807	0	0	0
T8	37002	0	0	0
T9	4072	0	0	0
T10	145650	11	0	0
T11	8483	0	0	0
T23	0	1	0	0
T24	0	26	0	0
T25	0	6	0	0
T41	0	4	0	0
T42	0	10	0	0
T80	0	5	0	0
T82	0	1	0	0
T83	0	8	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1550951	20401	0	0
T1	595	6	0	0
T2	1202	9	0	0
T3	322	5	0	0
T4	731	2	0	0
T5	7022	98	0	0
T6	3685	76	0	0
T7	548	6	0	0
T8	2345	45	0	0
T9	252	2	0	0
T10	9288	126	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1550951	1037	0	0
T2	1202	8	0	0
T3	322	0	0	0
T4	731	0	0	0
T5	7022	0	0	0
T6	3685	0	0	0
T7	548	0	0	0
T8	2345	0	0	0
T9	252	0	0	0
T10	9288	13	0	0
T11	528	0	0	0
T23	0	2	0	0
T24	0	24	0	0
T25	0	6	0	0
T41	0	5	0	0
T42	0	10	0	0
T80	0	6	0	0
T81	0	1	0	0
T84	0	1	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1550951	20401	0	0
T1	595	6	0	0
T2	1202	9	0	0
T3	322	5	0	0
T4	731	2	0	0
T5	7022	98	0	0
T6	3685	76	0	0
T7	548	6	0	0
T8	2345	45	0	0
T9	252	2	0	0
T10	9288	126	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1550951	1037	0	0
T2	1202	8	0	0
T3	322	0	0	0
T4	731	0	0	0
T5	7022	0	0	0
T6	3685	0	0	0
T7	548	0	0	0
T8	2345	0	0	0
T9	252	0	0	0
T10	9288	13	0	0
T11	528	0	0	0
T23	0	2	0	0
T24	0	24	0	0
T25	0	6	0	0
T41	0	5	0	0
T42	0	10	0	0
T80	0	6	0	0
T81	0	1	0	0
T84	0	1	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12288830	13553	0	0
T1	4771	5	0	0
T2	9623	9	0	0
T3	2586	4	0	0
T4	5839	0	0	0
T5	56062	75	0	0
T6	29354	75	0	0
T7	4401	4	0	0
T8	18504	29	0	0
T9	2035	0	0	0
T10	72827	96	0	0
T11	0	19	0	0
T12	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12288830	1101	0	0
T1	4771	1	0	0
T2	9623	9	0	0
T3	2586	0	0	0
T4	5839	0	0	0
T5	56062	0	0	0
T6	29354	0	0	0
T7	4401	0	0	0
T8	18504	0	0	0
T9	2035	0	0	0
T10	72827	10	0	0
T23	0	2	0	0
T24	0	21	0	0
T25	0	8	0	0
T41	0	5	0	0
T42	0	12	0	0
T80	0	8	0	0
T84	0	1	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12288830	13553	0	0
T1	4771	5	0	0
T2	9623	9	0	0
T3	2586	4	0	0
T4	5839	0	0	0
T5	56062	75	0	0
T6	29354	75	0	0
T7	4401	4	0	0
T8	18504	29	0	0
T9	2035	0	0	0
T10	72827	96	0	0
T11	0	19	0	0
T12	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12288830	1101	0	0
T1	4771	1	0	0
T2	9623	9	0	0
T3	2586	0	0	0
T4	5839	0	0	0
T5	56062	0	0	0
T6	29354	0	0	0
T7	4401	0	0	0
T8	18504	0	0	0
T9	2035	0	0	0
T10	72827	10	0	0
T23	0	2	0	0
T24	0	21	0	0
T25	0	8	0	0
T41	0	5	0	0
T42	0	12	0	0
T80	0	8	0	0
T84	0	1	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12288830	13597	0	0
T1	4771	4	0	0
T2	9623	9	0	0
T3	2586	4	0	0
T4	5839	0	0	0
T5	56062	75	0	0
T6	29354	75	0	0
T7	4401	4	0	0
T8	18504	29	0	0
T9	2035	0	0	0
T10	72827	93	0	0
T11	0	19	0	0
T12	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12288830	1138	0	0
T2	9623	9	0	0
T3	2586	0	0	0
T4	5839	0	0	0
T5	56062	0	0	0
T6	29354	0	0	0
T7	4401	0	0	0
T8	18504	0	0	0
T9	2035	0	0	0
T10	72827	7	0	0
T11	4241	0	0	0
T23	0	2	0	0
T24	0	20	0	0
T25	0	7	0	0
T41	0	7	0	0
T42	0	13	0	0
T80	0	9	0	0
T82	0	1	0	0
T83	0	10	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12288830	13597	0	0
T1	4771	4	0	0
T2	9623	9	0	0
T3	2586	4	0	0
T4	5839	0	0	0
T5	56062	75	0	0
T6	29354	75	0	0
T7	4401	4	0	0
T8	18504	29	0	0
T9	2035	0	0	0
T10	72827	93	0	0
T11	0	19	0	0
T12	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12288830	1138	0	0
T2	9623	9	0	0
T3	2586	0	0	0
T4	5839	0	0	0
T5	56062	0	0	0
T6	29354	0	0	0
T7	4401	0	0	0
T8	18504	0	0	0
T9	2035	0	0	0
T10	72827	7	0	0
T11	4241	0	0	0
T23	0	2	0	0
T24	0	20	0	0
T25	0	7	0	0
T41	0	7	0	0
T42	0	13	0	0
T80	0	9	0	0
T82	0	1	0	0
T83	0	10	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12288830	13641	0	0
T1	4771	5	0	0
T2	9623	10	0	0
T3	2586	4	0	0
T4	5839	0	0	0
T5	56062	75	0	0
T6	29354	75	0	0
T7	4401	4	0	0
T8	18504	29	0	0
T9	2035	0	0	0
T10	72827	95	0	0
T11	0	19	0	0
T12	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12288830	1200	0	0
T1	4771	1	0	0
T2	9623	10	0	0
T3	2586	0	0	0
T4	5839	0	0	0
T5	56062	0	0	0
T6	29354	0	0	0
T7	4401	0	0	0
T8	18504	0	0	0
T9	2035	0	0	0
T10	72827	9	0	0
T23	0	1	0	0
T24	0	27	0	0
T25	0	10	0	0
T41	0	8	0	0
T42	0	14	0	0
T80	0	9	0	0
T81	0	1	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12288830	13641	0	0
T1	4771	5	0	0
T2	9623	10	0	0
T3	2586	4	0	0
T4	5839	0	0	0
T5	56062	75	0	0
T6	29354	75	0	0
T7	4401	4	0	0
T8	18504	29	0	0
T9	2035	0	0	0
T10	72827	95	0	0
T11	0	19	0	0
T12	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12288830	1200	0	0
T1	4771	1	0	0
T2	9623	10	0	0
T3	2586	0	0	0
T4	5839	0	0	0
T5	56062	0	0	0
T6	29354	0	0	0
T7	4401	0	0	0
T8	18504	0	0	0
T9	2035	0	0	0
T10	72827	9	0	0
T23	0	1	0	0
T24	0	27	0	0
T25	0	10	0	0
T41	0	8	0	0
T42	0	14	0	0
T80	0	9	0	0
T81	0	1	0	0