Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	11706797	7352	0	0
alert_regwen_rd_A	11706797	4503	0	0
cpu_regwen_rd_A	11706797	4576	0	0
sw_rst_ctrl_n_0_rd_A	11706797	8547	0	0
sw_rst_ctrl_n_1_rd_A	11706797	8775	0	0
sw_rst_ctrl_n_2_rd_A	11706797	8504	0	0
sw_rst_ctrl_n_3_rd_A	11706797	8878	0	0
sw_rst_ctrl_n_4_rd_A	11706797	8621	0	0
sw_rst_ctrl_n_5_rd_A	11706797	8607	0	0
sw_rst_ctrl_n_6_rd_A	11706797	8825	0	0
sw_rst_ctrl_n_7_rd_A	11706797	8625	0	0
sw_rst_regwen_0_rd_A	11706797	4996	0	0
sw_rst_regwen_1_rd_A	11706797	5125	0	0
sw_rst_regwen_2_rd_A	11706797	5042	0	0
sw_rst_regwen_3_rd_A	11706797	4858	0	0
sw_rst_regwen_4_rd_A	11706797	5044	0	0
sw_rst_regwen_5_rd_A	11706797	5023	0	0
sw_rst_regwen_6_rd_A	11706797	4790	0	0
sw_rst_regwen_7_rd_A	11706797	4864	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11706797	7352	0	0
T53	18792	1	0	0
T57	2514	224	0	0
T58	4587	25	0	0
T59	16534	442	0	0
T65	9395	2	0	0
T86	4566	114	0	0
T87	4672	19	0	0
T88	7676	387	0	0
T89	2840	13	0	0
T92	10456	1	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11706797	4503	0	0
T28	25971	0	0	0
T29	26181	0	0	0
T38	1551	0	0	0
T39	2558	0	0	0
T40	5449	0	0	0
T41	6337	0	0	0
T42	3622	0	0	0
T43	2412	0	0	0
T44	1284	0	0	0
T70	0	92	0	0
T77	33058	67	0	0
T97	0	13	0	0
T98	0	124	0	0
T100	0	96	0	0
T101	0	143	0	0
T102	0	101	0	0
T124	0	50	0	0
T125	0	247	0	0
T126	0	65	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11706797	4576	0	0
T28	25971	0	0	0
T29	26181	0	0	0
T38	1551	0	0	0
T39	2558	0	0	0
T40	5449	0	0	0
T41	6337	0	0	0
T42	3622	0	0	0
T43	2412	0	0	0
T44	1284	0	0	0
T70	0	77	0	0
T77	33058	58	0	0
T97	0	33	0	0
T98	0	95	0	0
T100	0	81	0	0
T101	0	216	0	0
T102	0	70	0	0
T124	0	44	0	0
T125	0	253	0	0
T126	0	58	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11706797	8547	0	0
T2	9605	120	0	0
T3	2392	0	0	0
T4	5485	0	0	0
T5	53089	0	0	0
T6	26004	0	0	0
T7	4112	0	0	0
T8	14646	0	0	0
T9	1920	0	0	0
T10	63172	0	0	0
T11	2746	0	0	0
T77	0	58	0	0
T80	0	150	0	0
T97	0	23	0	0
T98	0	322	0	0
T100	0	195	0	0
T124	0	32	0	0
T127	0	22	0	0
T128	0	12	0	0
T129	0	21	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11706797	8775	0	0
T2	9605	105	0	0
T3	2392	0	0	0
T4	5485	0	0	0
T5	53089	0	0	0
T6	26004	0	0	0
T7	4112	0	0	0
T8	14646	0	0	0
T9	1920	0	0	0
T10	63172	0	0	0
T11	2746	0	0	0
T77	0	54	0	0
T80	0	142	0	0
T97	0	26	0	0
T98	0	322	0	0
T100	0	158	0	0
T124	0	43	0	0
T127	0	22	0	0
T128	0	3	0	0
T129	0	11	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11706797	8504	0	0
T2	9605	127	0	0
T3	2392	0	0	0
T4	5485	0	0	0
T5	53089	0	0	0
T6	26004	0	0	0
T7	4112	0	0	0
T8	14646	0	0	0
T9	1920	0	0	0
T10	63172	0	0	0
T11	2746	0	0	0
T77	0	62	0	0
T80	0	100	0	0
T97	0	23	0	0
T98	0	347	0	0
T100	0	173	0	0
T124	0	41	0	0
T127	0	27	0	0
T128	0	5	0	0
T129	0	14	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11706797	8878	0	0
T2	9605	127	0	0
T3	2392	0	0	0
T4	5485	0	0	0
T5	53089	0	0	0
T6	26004	0	0	0
T7	4112	0	0	0
T8	14646	0	0	0
T9	1920	0	0	0
T10	63172	0	0	0
T11	2746	0	0	0
T77	0	33	0	0
T80	0	160	0	0
T97	0	38	0	0
T98	0	253	0	0
T100	0	170	0	0
T124	0	33	0	0
T127	0	26	0	0
T128	0	6	0	0
T129	0	13	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11706797	8621	0	0
T2	9605	86	0	0
T3	2392	0	0	0
T4	5485	0	0	0
T5	53089	0	0	0
T6	26004	0	0	0
T7	4112	0	0	0
T8	14646	0	0	0
T9	1920	0	0	0
T10	63172	0	0	0
T11	2746	0	0	0
T77	0	51	0	0
T80	0	160	0	0
T97	0	16	0	0
T98	0	328	0	0
T100	0	203	0	0
T124	0	56	0	0
T127	0	23	0	0
T128	0	8	0	0
T129	0	13	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11706797	8607	0	0
T2	9605	130	0	0
T3	2392	0	0	0
T4	5485	0	0	0
T5	53089	0	0	0
T6	26004	0	0	0
T7	4112	0	0	0
T8	14646	0	0	0
T9	1920	0	0	0
T10	63172	0	0	0
T11	2746	0	0	0
T77	0	53	0	0
T80	0	119	0	0
T97	0	32	0	0
T98	0	343	0	0
T100	0	192	0	0
T124	0	45	0	0
T127	0	19	0	0
T128	0	17	0	0
T129	0	12	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11706797	8825	0	0
T2	9605	76	0	0
T3	2392	0	0	0
T4	5485	0	0	0
T5	53089	0	0	0
T6	26004	0	0	0
T7	4112	0	0	0
T8	14646	0	0	0
T9	1920	0	0	0
T10	63172	0	0	0
T11	2746	0	0	0
T77	0	53	0	0
T80	0	151	0	0
T97	0	20	0	0
T98	0	340	0	0
T100	0	143	0	0
T124	0	62	0	0
T127	0	23	0	0
T128	0	9	0	0
T129	0	10	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11706797	8625	0	0
T2	9605	128	0	0
T3	2392	0	0	0
T4	5485	0	0	0
T5	53089	0	0	0
T6	26004	0	0	0
T7	4112	0	0	0
T8	14646	0	0	0
T9	1920	0	0	0
T10	63172	0	0	0
T11	2746	0	0	0
T77	0	66	0	0
T80	0	148	0	0
T97	0	29	0	0
T98	0	290	0	0
T100	0	170	0	0
T124	0	44	0	0
T127	0	28	0	0
T128	0	9	0	0
T129	0	18	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11706797	4996	0	0
T2	9605	16	0	0
T3	2392	0	0	0
T4	5485	0	0	0
T5	53089	0	0	0
T6	26004	0	0	0
T7	4112	0	0	0
T8	14646	0	0	0
T9	1920	0	0	0
T10	63172	0	0	0
T11	2746	0	0	0
T77	0	91	0	0
T80	0	35	0	0
T97	0	35	0	0
T98	0	111	0	0
T100	0	59	0	0
T101	0	196	0	0
T124	0	48	0	0
T128	0	4	0	0
T129	0	12	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11706797	5125	0	0
T2	9605	15	0	0
T3	2392	0	0	0
T4	5485	0	0	0
T5	53089	0	0	0
T6	26004	0	0	0
T7	4112	0	0	0
T8	14646	0	0	0
T9	1920	0	0	0
T10	63172	0	0	0
T11	2746	0	0	0
T77	0	59	0	0
T80	0	36	0	0
T97	0	7	0	0
T98	0	91	0	0
T100	0	56	0	0
T101	0	179	0	0
T124	0	46	0	0
T128	0	1	0	0
T129	0	4	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11706797	5042	0	0
T2	9605	40	0	0
T3	2392	0	0	0
T4	5485	0	0	0
T5	53089	0	0	0
T6	26004	0	0	0
T7	4112	0	0	0
T8	14646	0	0	0
T9	1920	0	0	0
T10	63172	0	0	0
T11	2746	0	0	0
T77	0	69	0	0
T80	0	24	0	0
T97	0	17	0	0
T98	0	96	0	0
T100	0	72	0	0
T101	0	243	0	0
T124	0	45	0	0
T128	0	5	0	0
T129	0	7	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11706797	4858	0	0
T2	9605	15	0	0
T3	2392	0	0	0
T4	5485	0	0	0
T5	53089	0	0	0
T6	26004	0	0	0
T7	4112	0	0	0
T8	14646	0	0	0
T9	1920	0	0	0
T10	63172	0	0	0
T11	2746	0	0	0
T77	0	68	0	0
T80	0	25	0	0
T97	0	17	0	0
T98	0	109	0	0
T100	0	74	0	0
T101	0	167	0	0
T124	0	56	0	0
T128	0	1	0	0
T129	0	3	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11706797	5044	0	0
T2	9605	24	0	0
T3	2392	0	0	0
T4	5485	0	0	0
T5	53089	0	0	0
T6	26004	0	0	0
T7	4112	0	0	0
T8	14646	0	0	0
T9	1920	0	0	0
T10	63172	0	0	0
T11	2746	0	0	0
T77	0	50	0	0
T80	0	38	0	0
T97	0	41	0	0
T98	0	116	0	0
T100	0	63	0	0
T101	0	200	0	0
T102	0	54	0	0
T124	0	48	0	0
T129	0	4	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11706797	5023	0	0
T2	9605	17	0	0
T3	2392	0	0	0
T4	5485	0	0	0
T5	53089	0	0	0
T6	26004	0	0	0
T7	4112	0	0	0
T8	14646	0	0	0
T9	1920	0	0	0
T10	63172	0	0	0
T11	2746	0	0	0
T77	0	58	0	0
T80	0	33	0	0
T97	0	26	0	0
T98	0	74	0	0
T100	0	51	0	0
T101	0	213	0	0
T124	0	45	0	0
T128	0	8	0	0
T129	0	8	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11706797	4790	0	0
T2	9605	27	0	0
T3	2392	0	0	0
T4	5485	0	0	0
T5	53089	0	0	0
T6	26004	0	0	0
T7	4112	0	0	0
T8	14646	0	0	0
T9	1920	0	0	0
T10	63172	0	0	0
T11	2746	0	0	0
T77	0	58	0	0
T80	0	32	0	0
T97	0	16	0	0
T98	0	84	0	0
T100	0	47	0	0
T101	0	179	0	0
T124	0	61	0	0
T128	0	7	0	0
T129	0	6	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11706797	4864	0	0
T2	9605	13	0	0
T3	2392	0	0	0
T4	5485	0	0	0
T5	53089	0	0	0
T6	26004	0	0	0
T7	4112	0	0	0
T8	14646	0	0	0
T9	1920	0	0	0
T10	63172	0	0	0
T11	2746	0	0	0
T77	0	55	0	0
T80	0	22	0	0
T97	0	18	0	0
T98	0	51	0	0
T100	0	65	0	0
T101	0	197	0	0
T124	0	48	0	0
T128	0	3	0	0
T129	0	7	0	0