Unified Coverage Report :: Group :: rstmgr_env_pkg::rstmgr_sw_rst_cg_wrap::sw_rst_cg

Group : rstmgr_env_pkg::rstmgr_sw_rst_cg_wrap::sw_rst_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_env_0.1/rstmgr_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sw_rst_ctrl_n[0]	100.00	1	100	1	64	64
sw_rst_ctrl_n[1]	100.00	1	100	1	64	64
sw_rst_ctrl_n[2]	100.00	1	100	1	64	64
sw_rst_ctrl_n[3]	100.00	1	100	1	64	64
sw_rst_ctrl_n[4]	100.00	1	100	1	64	64
sw_rst_ctrl_n[5]	100.00	1	100	1	64	64
sw_rst_ctrl_n[6]	100.00	1	100	1	64	64
sw_rst_ctrl_n[7]	100.00	1	100	1	64	64

---

Group Instance : sw_rst_ctrl_n[0]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[0]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[0]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[0]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[1]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[1]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[1]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[1]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[2]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[2]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[2]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[2]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[3]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[3]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[3]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[3]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[4]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[4]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[4]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[4]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[5]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[5]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[5]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[5]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[6]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[6]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[6]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[6]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

---

Group Instance : sw_rst_ctrl_n[7]

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance sw_rst_ctrl_n[7]

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	4	0	4	100.00

Variables for Group Instance sw_rst_ctrl_n[7]

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
enable	2	0	2	100.00	100	1	1	2
enable_cp	2	0	2	100.00	100	1	1	2
rst_n	2	0	2	100.00	100	1	1	2
rst_n_cp	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sw_rst_ctrl_n[7]

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sw_rst_cross	4	0	4	100.00	100	1	1	0

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1600

1

T3

32

T11

32

T60

32

auto[1]

4270

1

T1

8

T2

7

T3

11

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1600

1

T3

32

T11

32

T60

32

auto[1]

4270

1

T1

8

T2

7

T3

11

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1637

1

T2

1

T3

10

T4

1

auto[1]

4233

1

T1

8

T2

6

T3

33

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1637

1

T2

1

T3

10

T4

1

auto[1]

4233

1

T1

8

T2

6

T3

33

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

400

1

T3

8

T11

8

T60

8

auto[0]

auto[1]

1200

1

T3

24

T11

24

T60

24

auto[1]

auto[0]

1237

1

T2

1

T3

2

T4

1

auto[1]

auto[1]

3033

1

T1

8

T2

6

T3

9

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1484

1

T3

28

T4

3

T11

28

auto[1]

4198

1

T1

7

T2

5

T3

15

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1484

1

T3

28

T4

3

T11

28

auto[1]

4198

1

T1

7

T2

5

T3

15

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1635

1

T3

11

T4

1

T6

28

auto[1]

4047

1

T1

7

T2

5

T3

32

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1635

1

T3

11

T4

1

T6

28

auto[1]

4047

1

T1

7

T2

5

T3

32

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

394

1

T3

7

T4

1

T11

7

auto[0]

auto[1]

1090

1

T3

21

T4

2

T11

21

auto[1]

auto[0]

1241

1

T3

4

T6

28

T11

7

auto[1]

auto[1]

2957

1

T1

7

T2

5

T3

11

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1281

1

T3

24

T9

3

T11

24

auto[1]

4317

1

T1

7

T2

5

T3

19

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1281

1

T3

24

T9

3

T11

24

auto[1]

4317

1

T1

7

T2

5

T3

19

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1649

1

T3

13

T6

36

T9

2

auto[1]

3949

1

T1

7

T2

5

T3

30

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1649

1

T3

13

T6

36

T9

2

auto[1]

3949

1

T1

7

T2

5

T3

30

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

344

1

T3

6

T9

2

T11

6

auto[0]

auto[1]

937

1

T3

18

T9

1

T11

18

auto[1]

auto[0]

1305

1

T3

7

T6

36

T11

9

auto[1]

auto[1]

3012

1

T1

7

T2

5

T3

12

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1090

1

T3

20

T9

3

T11

20

auto[1]

4494

1

T1

7

T2

5

T3

23

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1090

1

T3

20

T9

3

T11

20

auto[1]

4494

1

T1

7

T2

5

T3

23

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1577

1

T3

11

T4

1

T6

26

auto[1]

4007

1

T1

7

T2

5

T3

32

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1577

1

T3

11

T4

1

T6

26

auto[1]

4007

1

T1

7

T2

5

T3

32

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

295

1

T3

5

T9

2

T11

5

auto[0]

auto[1]

795

1

T3

15

T9

1

T11

15

auto[1]

auto[0]

1282

1

T3

6

T4

1

T6

26

auto[1]

auto[1]

3212

1

T1

7

T2

5

T3

17

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

854

1

T3

16

T11

16

T12

3

auto[1]

4730

1

T1

7

T2

5

T3

27

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

854

1

T3

16

T11

16

T12

3

auto[1]

4730

1

T1

7

T2

5

T3

27

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1580

1

T3

11

T6

33

T11

13

auto[1]

4004

1

T1

7

T2

5

T3

32

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1580

1

T3

11

T6

33

T11

13

auto[1]

4004

1

T1

7

T2

5

T3

32

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

225

1

T3

4

T11

4

T12

2

auto[0]

auto[1]

629

1

T3

12

T11

12

T12

1

auto[1]

auto[0]

1355

1

T3

7

T6

33

T11

9

auto[1]

auto[1]

3375

1

T1

7

T2

5

T3

20

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

690

1

T3

12

T4

3

T9

3

auto[1]

4894

1

T1

7

T2

5

T3

31

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

690

1

T3

12

T4

3

T9

3

auto[1]

4894

1

T1

7

T2

5

T3

31

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1608

1

T3

14

T4

2

T6

30

auto[1]

3976

1

T1

7

T2

5

T3

29

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1608

1

T3

14

T4

2

T6

30

auto[1]

3976

1

T1

7

T2

5

T3

29

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

191

1

T3

3

T4

2

T9

1

auto[0]

auto[1]

499

1

T3

9

T4

1

T9

2

auto[1]

auto[0]

1417

1

T3

11

T6

30

T11

12

auto[1]

auto[1]

3477

1

T1

7

T2

5

T3

20

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

484

1

T3

8

T4

3

T11

8

auto[1]

5100

1

T1

7

T2

5

T3

35

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

484

1

T3

8

T4

3

T11

8

auto[1]

5100

1

T1

7

T2

5

T3

35

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1597

1

T3

10

T4

2

T6

35

auto[1]

3987

1

T1

7

T2

5

T3

33

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1597

1

T3

10

T4

2

T6

35

auto[1]

3987

1

T1

7

T2

5

T3

33

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

142

1

T3

2

T4

2

T11

2

auto[0]

auto[1]

342

1

T3

6

T4

1

T11

6

auto[1]

auto[0]

1455

1

T3

8

T6

35

T9

1

auto[1]

auto[1]

3645

1

T1

7

T2

5

T3

27

Summary for Variable enable

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

272

1

T3

4

T11

4

T60

4

auto[1]

5312

1

T1

7

T2

5

T3

39

---

Summary for Variable enable_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for enable_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

272

1

T3

4

T11

4

T60

4

auto[1]

5312

1

T1

7

T2

5

T3

39

---

Summary for Variable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1600

1

T3

11

T6

26

T9

1

auto[1]

3984

1

T1

7

T2

5

T3

32

---

Summary for Variable rst_n_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for rst_n_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1600

1

T3

11

T6

26

T9

1

auto[1]

3984

1

T1

7

T2

5

T3

32

---

Summary for Cross sw_rst_cross

Samples crossed: enable rst_n

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	4	0	4	100.00

Automatically Generated Cross Bins for sw_rst_cross

Bins

enable

rst_n

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

86

1

T3

1

T11

1

T60

1

auto[0]

auto[1]

186

1

T3

3

T11

3

T60

3

auto[1]

auto[0]

1514

1

T3

10

T6

26

T9

1

auto[1]

auto[1]

3798

1

T1

7

T2

5

T3

29