Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	642594	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

385466

1

T1

47

T2

33

T3

310

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	550207	1			T1	63		T2	45		T3	427
values[0x0]	238532	1			T1	34		T2	25		T3	201
values[0x1]	239321	1			T1	32		T2	23		T3	180

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	539169	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

488891

1

T1

64

T2

46

T3

392

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4002	1			T3	1		T7	1		T8	12
valid_sources[0x01]	3600	1			T2	1		T3	5		T8	9
valid_sources[0x02]	4518	1			T2	1		T3	2		T8	5
valid_sources[0x03]	3491	1			T2	1		T3	4		T8	7
valid_sources[0x04]	3161	1			T3	1		T7	8		T8	8
valid_sources[0x05]	3945	1			T2	1		T3	2		T8	11
valid_sources[0x06]	3144	1			T2	2		T3	6		T5	1
valid_sources[0x07]	4465	1			T3	1		T5	1		T7	2
valid_sources[0x08]	3679	1			T3	4		T4	5		T8	11
valid_sources[0x09]	4042	1			T2	1		T3	1		T4	10
valid_sources[0x0a]	3506	1			T3	3		T7	2		T8	12
valid_sources[0x0b]	7209	1			T3	7		T5	1		T6	789
valid_sources[0x0c]	4239	1			T8	15		T11	4		T12	1
valid_sources[0x0d]	5499	1			T1	1		T4	1		T5	1
valid_sources[0x0e]	4449	1			T3	3		T6	408		T8	14
valid_sources[0x0f]	3422	1			T3	2		T8	9		T9	3
valid_sources[0x10]	3943	1			T2	2		T3	5		T6	70
valid_sources[0x11]	4854	1			T3	5		T8	8		T11	5
valid_sources[0x12]	3341	1			T3	3		T8	3		T9	8
valid_sources[0x13]	3064	1			T1	5		T3	8		T8	20
valid_sources[0x14]	4273	1			T6	155		T7	3		T8	11
valid_sources[0x15]	4110	1			T3	4		T4	6		T8	3
valid_sources[0x16]	4356	1			T3	2		T4	5		T6	453
valid_sources[0x17]	3207	1			T1	2		T3	3		T8	9
valid_sources[0x18]	3502	1			T3	4		T4	14		T6	70
valid_sources[0x19]	3440	1			T3	2		T4	1		T8	7
valid_sources[0x1a]	3541	1			T2	1		T3	4		T8	23
valid_sources[0x1b]	3946	1			T1	2		T2	1		T3	3
valid_sources[0x1c]	3645	1			T3	3		T6	255		T8	19
valid_sources[0x1d]	3570	1			T1	5		T3	3		T4	3
valid_sources[0x1e]	3350	1			T1	1		T3	3		T8	12
valid_sources[0x1f]	3126	1			T3	3		T7	5		T8	16
valid_sources[0x20]	4227	1			T3	5		T8	2		T9	3
valid_sources[0x21]	3524	1			T1	5		T3	7		T8	18
valid_sources[0x22]	3488	1			T3	3		T8	10		T9	5
valid_sources[0x23]	3469	1			T2	1		T3	2		T8	11
valid_sources[0x24]	3293	1			T3	2		T8	9		T11	5
valid_sources[0x25]	4772	1			T3	10		T4	6		T8	15
valid_sources[0x26]	3463	1			T3	1		T8	31		T9	1
valid_sources[0x27]	3285	1			T3	2		T8	9		T11	3
valid_sources[0x28]	2837	1			T2	1		T3	3		T8	13
valid_sources[0x29]	4124	1			T8	12		T11	3		T12	3
valid_sources[0x2a]	4426	1			T3	3		T4	3		T8	9
valid_sources[0x2b]	4028	1			T3	1		T5	2		T8	14
valid_sources[0x2c]	3706	1			T3	1		T7	22		T8	9
valid_sources[0x2d]	4655	1			T3	2		T6	70		T8	11
valid_sources[0x2e]	4407	1			T3	3		T8	11		T9	3
valid_sources[0x2f]	6408	1			T3	5		T8	15		T9	2
valid_sources[0x30]	3185	1			T3	2		T8	11		T9	3
valid_sources[0x31]	3883	1			T2	2		T3	3		T7	2
valid_sources[0x32]	3597	1			T8	7		T11	1		T12	3
valid_sources[0x33]	3613	1			T3	6		T8	6		T9	1
valid_sources[0x34]	3186	1			T3	4		T8	19		T11	5
valid_sources[0x35]	3586	1			T2	1		T3	1		T8	19
valid_sources[0x36]	3586	1			T3	6		T8	17		T9	1
valid_sources[0x37]	3951	1			T2	1		T7	2		T8	18
valid_sources[0x38]	3870	1			T6	70		T8	19		T11	3
valid_sources[0x39]	6791	1			T2	3		T3	2		T8	23
valid_sources[0x3a]	4506	1			T1	4		T3	5		T8	20
valid_sources[0x3b]	3940	1			T1	2		T3	1		T6	240
valid_sources[0x3c]	3735	1			T1	3		T3	3		T4	1
valid_sources[0x3d]	3461	1			T2	1		T3	8		T8	15
valid_sources[0x3e]	4573	1			T6	70		T8	19		T9	1
valid_sources[0x3f]	4875	1			T3	5		T6	113		T8	8
valid_sources[0x40]	4724	1			T1	3		T3	6		T6	196
valid_sources[0x41]	4200	1			T3	1		T6	112		T8	13
valid_sources[0x42]	3068	1			T3	6		T6	70		T7	1
valid_sources[0x43]	5281	1			T3	4		T6	113		T8	8
valid_sources[0x44]	3398	1			T3	1		T6	70		T8	5
valid_sources[0x45]	4430	1			T2	1		T3	7		T6	112
valid_sources[0x46]	3708	1			T3	2		T8	10		T9	2
valid_sources[0x47]	3406	1			T1	1		T3	4		T4	7
valid_sources[0x48]	3966	1			T2	1		T6	238		T7	2
valid_sources[0x49]	4691	1			T2	1		T3	2		T4	1
valid_sources[0x4a]	3618	1			T3	3		T8	15		T11	7
valid_sources[0x4b]	3821	1			T2	1		T3	4		T4	2
valid_sources[0x4c]	3607	1			T3	4		T4	4		T8	19
valid_sources[0x4d]	4401	1			T3	1		T8	24		T9	2
valid_sources[0x4e]	3881	1			T6	156		T7	13		T8	11
valid_sources[0x4f]	3783	1			T3	4		T8	12		T9	3
valid_sources[0x50]	3356	1			T2	1		T6	182		T8	19
valid_sources[0x51]	3495	1			T3	2		T8	11		T9	1
valid_sources[0x52]	4453	1			T3	6		T7	2		T8	7
valid_sources[0x53]	3412	1			T3	4		T6	70		T8	16
valid_sources[0x54]	3284	1			T3	8		T8	11		T11	5
valid_sources[0x55]	3526	1			T3	2		T8	11		T11	2
valid_sources[0x56]	3616	1			T3	3		T4	1		T5	1
valid_sources[0x57]	4230	1			T3	3		T4	8		T8	7
valid_sources[0x58]	3263	1			T2	1		T3	1		T4	2
valid_sources[0x59]	3259	1			T2	1		T3	3		T4	2
valid_sources[0x5a]	4585	1			T8	13		T11	5		T12	2
valid_sources[0x5b]	3608	1			T8	12		T11	5		T12	1
valid_sources[0x5c]	3488	1			T3	3		T8	15		T11	4
valid_sources[0x5d]	2880	1			T3	1		T4	1		T8	22
valid_sources[0x5e]	6615	1			T3	1		T7	7		T8	14
valid_sources[0x5f]	4095	1			T2	1		T3	3		T8	7
valid_sources[0x60]	4924	1			T3	2		T7	11		T8	10
valid_sources[0x61]	3917	1			T1	5		T2	1		T3	3
valid_sources[0x62]	4245	1			T3	4		T4	5		T8	8
valid_sources[0x63]	2813	1			T2	1		T3	4		T8	6
valid_sources[0x64]	3399	1			T3	3		T4	2		T6	155
valid_sources[0x65]	2992	1			T2	4		T3	5		T6	113
valid_sources[0x66]	5828	1			T3	4		T6	12		T7	8
valid_sources[0x67]	3625	1			T3	6		T6	113		T8	11
valid_sources[0x68]	4979	1			T3	5		T6	283		T8	17
valid_sources[0x69]	4042	1			T4	6		T5	1		T6	70
valid_sources[0x6a]	3443	1			T2	1		T3	3		T6	70
valid_sources[0x6b]	7638	1			T1	4		T3	2		T6	199
valid_sources[0x6c]	3115	1			T3	3		T4	1		T8	13
valid_sources[0x6d]	4725	1			T3	10		T8	5		T11	4
valid_sources[0x6e]	3450	1			T2	1		T3	6		T4	17
valid_sources[0x6f]	3247	1			T3	3		T8	6		T11	2
valid_sources[0x70]	3147	1			T3	3		T4	4		T8	9
valid_sources[0x71]	3669	1			T2	1		T3	5		T8	6
valid_sources[0x72]	7022	1			T2	2		T3	4		T7	9
valid_sources[0x73]	3186	1			T3	3		T6	126		T8	19
valid_sources[0x74]	3291	1			T3	3		T8	11		T9	2
valid_sources[0x75]	3238	1			T2	1		T3	2		T8	10
valid_sources[0x76]	6946	1			T3	2		T8	12		T9	1
valid_sources[0x77]	4915	1			T3	3		T6	112		T8	9
valid_sources[0x78]	3464	1			T3	1		T8	5		T11	5
valid_sources[0x79]	3682	1			T3	4		T8	19		T11	7
valid_sources[0x7a]	3680	1			T3	2		T4	4		T8	17
valid_sources[0x7b]	3209	1			T3	5		T4	1		T8	7
valid_sources[0x7c]	4021	1			T3	2		T8	23		T9	1
valid_sources[0x7d]	3581	1			T2	1		T3	7		T8	17
valid_sources[0x7e]	3424	1			T3	3		T4	19		T6	70
valid_sources[0x7f]	3791	1			T3	1		T8	17		T11	7
valid_sources[0x80]	4931	1			T6	605		T8	12		T9	2

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

257680

1

T1

28

T2

20

T3

203

values[0x0]

all_enables

biggest_size

83326

1

T1

11

T2

10

T3

77

values[0x1]

all_enables

biggest_size

44460

1

T1

8

T2

3

T3

30