Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T4,T6,T7

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11735758	13588	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11735758	125268	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11735758	6898098	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11735758	200006	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11735758	13588	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11735758	125268	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11735758	6898098	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11735758	200006	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11735758	13588	0	0
T1	2301	7	0	0
T2	2669	5	0	0
T3	7221	0	0	0
T4	5946	4	0	0
T5	1314	0	0	0
T6	161877	168	0	0
T7	3328	4	0	0
T8	46916	33	0	0
T9	6157	4	0	0
T10	3709	0	0	0
T12	0	4	0	0
T13	0	75	0	0
T24	0	13	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11735758	125268	0	0
T1	2301	63	0	0
T2	2669	45	0	0
T3	7221	0	0	0
T4	5946	37	0	0
T5	1314	0	0	0
T6	161877	1546	0	0
T7	3328	37	0	0
T8	46916	301	0	0
T9	6157	37	0	0
T10	3709	0	0	0
T12	0	37	0	0
T13	0	704	0	0
T24	0	117	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11735758	6898098	0	0
T1	2301	1610	0	0
T2	2669	1965	0	0
T3	7221	6598	0	0
T4	5946	4957	0	0
T5	1314	738	0	0
T6	161877	115875	0	0
T7	3328	2399	0	0
T8	46916	34438	0	0
T9	6157	5165	0	0
T10	3709	638	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11735758	200006	0	0
T1	2301	113	0	0
T2	2669	76	0	0
T3	7221	0	0	0
T4	5946	60	0	0
T5	1314	0	0	0
T6	161877	2504	0	0
T7	3328	54	0	0
T8	46916	475	0	0
T9	6157	56	0	0
T10	3709	0	0	0
T12	0	69	0	0
T13	0	1139	0	0
T24	0	187	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11735758	13588	0	0
T1	2301	7	0	0
T2	2669	5	0	0
T3	7221	0	0	0
T4	5946	4	0	0
T5	1314	0	0	0
T6	161877	168	0	0
T7	3328	4	0	0
T8	46916	33	0	0
T9	6157	4	0	0
T10	3709	0	0	0
T12	0	4	0	0
T13	0	75	0	0
T24	0	13	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11735758	125268	0	0
T1	2301	63	0	0
T2	2669	45	0	0
T3	7221	0	0	0
T4	5946	37	0	0
T5	1314	0	0	0
T6	161877	1546	0	0
T7	3328	37	0	0
T8	46916	301	0	0
T9	6157	37	0	0
T10	3709	0	0	0
T12	0	37	0	0
T13	0	704	0	0
T24	0	117	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11735758	6898098	0	0
T1	2301	1610	0	0
T2	2669	1965	0	0
T3	7221	6598	0	0
T4	5946	4957	0	0
T5	1314	738	0	0
T6	161877	115875	0	0
T7	3328	2399	0	0
T8	46916	34438	0	0
T9	6157	5165	0	0
T10	3709	638	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11735758	200006	0	0
T1	2301	113	0	0
T2	2669	76	0	0
T3	7221	0	0	0
T4	5946	60	0	0
T5	1314	0	0	0
T6	161877	2504	0	0
T7	3328	54	0	0
T8	46916	475	0	0
T9	6157	56	0	0
T10	3709	0	0	0
T12	0	69	0	0
T13	0	1139	0	0
T24	0	187	0	0