Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T4,T6,T7
0	1	Covered	T6,T8,T25
1	0	Covered	T4,T6,T8

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T6,T8,T10
1	0	Covered	T4,T6,T7
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	55277797	9013	0	0
CascadeEffAonToRstPorAboveRise_A	55277797	9013	0	0
CascadeEffAonToRstPorIoAboveFall_A	53065581	9013	0	0
CascadeEffAonToRstPorIoAboveRise_A	53065581	9013	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26533460	9013	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26533460	9013	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13266535	9013	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13266535	9013	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26533318	9013	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26533318	9013	0	0
CascadeLcToLcAboveFall_A	55277797	22601	0	0
CascadeLcToLcAboveRise_A	55277797	22601	0	0
CascadeLcToLcAonAboveFall_A	1676357	22601	0	0
CascadeLcToLcAonAboveRise_A	1676357	22601	0	0
CascadeLcToLcShadowedAboveFall_A	55277797	22601	0	0
CascadeLcToLcShadowedAboveRise_A	55277797	22601	0	0
CascadePorToAonAboveFall_A	1676357	7007	0	0
CascadeSysToSysAboveFall_A	55277797	22601	0	0
CascadeSysToSysAboveRise_A	55277797	22601	0	0
ScanRstToAonRise_A	1676357	217	0	0
StablePorToAonRise_A	1676357	9013	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11735758	22601	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11735758	22601	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11735758	22601	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11735758	22601	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13266535	22601	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13266535	22601	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11735758	22601	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11735758	22601	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11735758	22601	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11735758	22601	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55277797	9013	0	0
T1	11540	1	0	0
T2	13192	1	0	0
T3	30271	1	0	0
T4	25583	2	0	0
T5	5854	1	0	0
T6	772997	97	0	0
T7	15078	2	0	0
T8	219456	27	0	0
T9	26258	2	0	0
T10	15836	2	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55277797	9013	0	0
T1	11540	1	0	0
T2	13192	1	0	0
T3	30271	1	0	0
T4	25583	2	0	0
T5	5854	1	0	0
T6	772997	97	0	0
T7	15078	2	0	0
T8	219456	27	0	0
T9	26258	2	0	0
T10	15836	2	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53065581	9013	0	0
T1	11077	1	0	0
T2	12666	1	0	0
T3	29060	1	0	0
T4	24566	2	0	0
T5	5621	1	0	0
T6	742089	97	0	0
T7	14474	2	0	0
T8	210665	27	0	0
T9	25206	2	0	0
T10	15202	2	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53065581	9013	0	0
T1	11077	1	0	0
T2	12666	1	0	0
T3	29060	1	0	0
T4	24566	2	0	0
T5	5621	1	0	0
T6	742089	97	0	0
T7	14474	2	0	0
T8	210665	27	0	0
T9	25206	2	0	0
T10	15202	2	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26533460	9013	0	0
T1	5538	1	0	0
T2	6332	1	0	0
T3	14529	1	0	0
T4	12278	2	0	0
T5	2809	1	0	0
T6	371060	97	0	0
T7	7237	2	0	0
T8	105345	27	0	0
T9	12605	2	0	0
T10	7601	2	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26533460	9013	0	0
T1	5538	1	0	0
T2	6332	1	0	0
T3	14529	1	0	0
T4	12278	2	0	0
T5	2809	1	0	0
T6	371060	97	0	0
T7	7237	2	0	0
T8	105345	27	0	0
T9	12605	2	0	0
T10	7601	2	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13266535	9013	0	0
T1	2769	1	0	0
T2	3165	1	0	0
T3	7264	1	0	0
T4	6140	2	0	0
T5	1405	1	0	0
T6	185534	97	0	0
T7	3618	2	0	0
T8	52668	27	0	0
T9	6301	2	0	0
T10	3800	2	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13266535	9013	0	0
T1	2769	1	0	0
T2	3165	1	0	0
T3	7264	1	0	0
T4	6140	2	0	0
T5	1405	1	0	0
T6	185534	97	0	0
T7	3618	2	0	0
T8	52668	27	0	0
T9	6301	2	0	0
T10	3800	2	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26533318	9013	0	0
T1	5537	1	0	0
T2	6332	1	0	0
T3	14529	1	0	0
T4	12280	2	0	0
T5	2809	1	0	0
T6	371053	97	0	0
T7	7239	2	0	0
T8	105343	27	0	0
T9	12603	2	0	0
T10	7600	2	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26533318	9013	0	0
T1	5537	1	0	0
T2	6332	1	0	0
T3	14529	1	0	0
T4	12280	2	0	0
T5	2809	1	0	0
T6	371053	97	0	0
T7	7239	2	0	0
T8	105343	27	0	0
T9	12603	2	0	0
T10	7600	2	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55277797	22601	0	0
T1	11540	8	0	0
T2	13192	6	0	0
T3	30271	1	0	0
T4	25583	6	0	0
T5	5854	1	0	0
T6	772997	265	0	0
T7	15078	6	0	0
T8	219456	60	0	0
T9	26258	6	0	0
T10	15836	2	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55277797	22601	0	0
T1	11540	8	0	0
T2	13192	6	0	0
T3	30271	1	0	0
T4	25583	6	0	0
T5	5854	1	0	0
T6	772997	265	0	0
T7	15078	6	0	0
T8	219456	60	0	0
T9	26258	6	0	0
T10	15836	2	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1676357	22601	0	0
T1	344	8	0	0
T2	393	6	0	0
T3	906	1	0	0
T4	766	6	0	0
T5	174	1	0	0
T6	23465	265	0	0
T7	451	6	0	0
T8	6619	60	0	0
T9	786	6	0	0
T10	474	2	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1676357	22601	0	0
T1	344	8	0	0
T2	393	6	0	0
T3	906	1	0	0
T4	766	6	0	0
T5	174	1	0	0
T6	23465	265	0	0
T7	451	6	0	0
T8	6619	60	0	0
T9	786	6	0	0
T10	474	2	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55277797	22601	0	0
T1	11540	8	0	0
T2	13192	6	0	0
T3	30271	1	0	0
T4	25583	6	0	0
T5	5854	1	0	0
T6	772997	265	0	0
T7	15078	6	0	0
T8	219456	60	0	0
T9	26258	6	0	0
T10	15836	2	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55277797	22601	0	0
T1	11540	8	0	0
T2	13192	6	0	0
T3	30271	1	0	0
T4	25583	6	0	0
T5	5854	1	0	0
T6	772997	265	0	0
T7	15078	6	0	0
T8	219456	60	0	0
T9	26258	6	0	0
T10	15836	2	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1676357	7007	0	0
T1	344	1	0	0
T2	393	1	0	0
T3	906	1	0	0
T4	766	1	0	0
T5	174	1	0	0
T6	23465	56	0	0
T7	451	1	0	0
T8	6619	16	0	0
T9	786	1	0	0
T10	474	12	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55277797	22601	0	0
T1	11540	8	0	0
T2	13192	6	0	0
T3	30271	1	0	0
T4	25583	6	0	0
T5	5854	1	0	0
T6	772997	265	0	0
T7	15078	6	0	0
T8	219456	60	0	0
T9	26258	6	0	0
T10	15836	2	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55277797	22601	0	0
T1	11540	8	0	0
T2	13192	6	0	0
T3	30271	1	0	0
T4	25583	6	0	0
T5	5854	1	0	0
T6	772997	265	0	0
T7	15078	6	0	0
T8	219456	60	0	0
T9	26258	6	0	0
T10	15836	2	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1676357	217	0	0
T6	23465	6	0	0
T7	451	0	0	0
T8	6619	1	0	0
T9	786	0	0	0
T10	474	0	0	0
T11	406	0	0	0
T12	580	0	0	0
T13	3669	0	0	0
T14	731	0	0	0
T24	399	0	0	0
T25	0	3	0	0
T28	0	1	0	0
T40	0	4	0	0
T48	0	3	0	0
T59	0	2	0	0
T82	0	2	0	0
T91	0	1	0	0
T92	0	1	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1676357	9013	0	0
T1	344	1	0	0
T2	393	1	0	0
T3	906	1	0	0
T4	766	2	0	0
T5	174	1	0	0
T6	23465	97	0	0
T7	451	2	0	0
T8	6619	27	0	0
T9	786	2	0	0
T10	474	2	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11735758	22601	0	0
T1	2301	8	0	0
T2	2669	6	0	0
T3	7221	1	0	0
T4	5946	6	0	0
T5	1314	1	0	0
T6	161877	265	0	0
T7	3328	6	0	0
T8	46916	60	0	0
T9	6157	6	0	0
T10	3709	2	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11735758	22601	0	0
T1	2301	8	0	0
T2	2669	6	0	0
T3	7221	1	0	0
T4	5946	6	0	0
T5	1314	1	0	0
T6	161877	265	0	0
T7	3328	6	0	0
T8	46916	60	0	0
T9	6157	6	0	0
T10	3709	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11735758	22601	0	0
T1	2301	8	0	0
T2	2669	6	0	0
T3	7221	1	0	0
T4	5946	6	0	0
T5	1314	1	0	0
T6	161877	265	0	0
T7	3328	6	0	0
T8	46916	60	0	0
T9	6157	6	0	0
T10	3709	2	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11735758	22601	0	0
T1	2301	8	0	0
T2	2669	6	0	0
T3	7221	1	0	0
T4	5946	6	0	0
T5	1314	1	0	0
T6	161877	265	0	0
T7	3328	6	0	0
T8	46916	60	0	0
T9	6157	6	0	0
T10	3709	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13266535	22601	0	0
T1	2769	8	0	0
T2	3165	6	0	0
T3	7264	1	0	0
T4	6140	6	0	0
T5	1405	1	0	0
T6	185534	265	0	0
T7	3618	6	0	0
T8	52668	60	0	0
T9	6301	6	0	0
T10	3800	2	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13266535	22601	0	0
T1	2769	8	0	0
T2	3165	6	0	0
T3	7264	1	0	0
T4	6140	6	0	0
T5	1405	1	0	0
T6	185534	265	0	0
T7	3618	6	0	0
T8	52668	60	0	0
T9	6301	6	0	0
T10	3800	2	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11735758	22601	0	0
T1	2301	8	0	0
T2	2669	6	0	0
T3	7221	1	0	0
T4	5946	6	0	0
T5	1314	1	0	0
T6	161877	265	0	0
T7	3328	6	0	0
T8	46916	60	0	0
T9	6157	6	0	0
T10	3709	2	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11735758	22601	0	0
T1	2301	8	0	0
T2	2669	6	0	0
T3	7221	1	0	0
T4	5946	6	0	0
T5	1314	1	0	0
T6	161877	265	0	0
T7	3328	6	0	0
T8	46916	60	0	0
T9	6157	6	0	0
T10	3709	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11735758	22601	0	0
T1	2301	8	0	0
T2	2669	6	0	0
T3	7221	1	0	0
T4	5946	6	0	0
T5	1314	1	0	0
T6	161877	265	0	0
T7	3328	6	0	0
T8	46916	60	0	0
T9	6157	6	0	0
T10	3709	2	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11735758	22601	0	0
T1	2301	8	0	0
T2	2669	6	0	0
T3	7221	1	0	0
T4	5946	6	0	0
T5	1314	1	0	0
T6	161877	265	0	0
T7	3328	6	0	0
T8	46916	60	0	0
T9	6157	6	0	0
T10	3709	2	0	0