Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T2,T3,T4
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T11
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T11
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T4,T6
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T11
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T11
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T9
1	0	Covered	T1,T2,T4

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T3,T6,T9
1	0	Covered	T1,T2,T4

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13266535	14402	0	0
gen_assertions[0].RstEnOn_A	13266535	965	0	0
gen_assertions[0].RstNOff_A	13266535	14402	0	0
gen_assertions[0].RstNOn_A	13266535	965	0	0
gen_assertions[1].RstEnOff_A	53065581	13144	0	0
gen_assertions[1].RstEnOn_A	53065581	962	0	0
gen_assertions[1].RstNOff_A	53065581	13144	0	0
gen_assertions[1].RstNOn_A	53065581	962	0	0
gen_assertions[2].RstEnOff_A	26533460	13230	0	0
gen_assertions[2].RstEnOn_A	26533460	1018	0	0
gen_assertions[2].RstNOff_A	26533460	13230	0	0
gen_assertions[2].RstNOn_A	26533460	1018	0	0
gen_assertions[3].RstEnOff_A	26533318	13233	0	0
gen_assertions[3].RstEnOn_A	26533318	1013	0	0
gen_assertions[3].RstNOff_A	26533318	13233	0	0
gen_assertions[3].RstNOn_A	26533318	1013	0	0
gen_assertions[4].RstEnOff_A	1676357	22258	0	0
gen_assertions[4].RstEnOn_A	1676357	1080	0	0
gen_assertions[4].RstNOff_A	1676357	22258	0	0
gen_assertions[4].RstNOn_A	1676357	1080	0	0
gen_assertions[5].RstEnOff_A	13266535	14691	0	0
gen_assertions[5].RstEnOn_A	13266535	1146	0	0
gen_assertions[5].RstNOff_A	13266535	14691	0	0
gen_assertions[5].RstNOn_A	13266535	1146	0	0
gen_assertions[6].RstEnOff_A	13266535	14718	0	0
gen_assertions[6].RstEnOn_A	13266535	1168	0	0
gen_assertions[6].RstNOff_A	13266535	14718	0	0
gen_assertions[6].RstNOn_A	13266535	1168	0	0
gen_assertions[7].RstEnOff_A	13266535	14782	0	0
gen_assertions[7].RstEnOn_A	13266535	1228	0	0
gen_assertions[7].RstNOff_A	13266535	14782	0	0
gen_assertions[7].RstNOn_A	13266535	1228	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13266535	14402	0	0
T1	2769	7	0	0
T2	3165	5	0	0
T3	7264	2	0	0
T4	6140	5	0	0
T5	1405	0	0	0
T6	185534	186	0	0
T7	3618	4	0	0
T8	52668	33	0	0
T9	6301	4	0	0
T10	3800	0	0	0
T11	0	5	0	0
T12	0	4	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13266535	965	0	0
T2	3165	1	0	0
T3	7264	2	0	0
T4	6140	1	0	0
T5	1405	0	0	0
T6	185534	20	0	0
T7	3618	0	0	0
T8	52668	0	0	0
T9	6301	0	0	0
T10	3800	0	0	0
T11	3265	5	0	0
T24	0	3	0	0
T25	0	8	0	0
T26	0	1	0	0
T40	0	30	0	0
T60	0	1	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13266535	14402	0	0
T1	2769	7	0	0
T2	3165	5	0	0
T3	7264	2	0	0
T4	6140	5	0	0
T5	1405	0	0	0
T6	185534	186	0	0
T7	3618	4	0	0
T8	52668	33	0	0
T9	6301	4	0	0
T10	3800	0	0	0
T11	0	5	0	0
T12	0	4	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13266535	965	0	0
T2	3165	1	0	0
T3	7264	2	0	0
T4	6140	1	0	0
T5	1405	0	0	0
T6	185534	20	0	0
T7	3618	0	0	0
T8	52668	0	0	0
T9	6301	0	0	0
T10	3800	0	0	0
T11	3265	5	0	0
T24	0	3	0	0
T25	0	8	0	0
T26	0	1	0	0
T40	0	30	0	0
T60	0	1	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53065581	13144	0	0
T1	11077	7	0	0
T2	12666	4	0	0
T3	29060	3	0	0
T4	24566	4	0	0
T5	5621	0	0	0
T6	742089	174	0	0
T7	14474	2	0	0
T8	210665	32	0	0
T9	25206	4	0	0
T10	15202	0	0	0
T11	0	6	0	0
T12	0	4	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53065581	962	0	0
T3	29060	3	0	0
T4	24566	0	0	0
T5	5621	0	0	0
T6	742089	20	0	0
T7	14474	0	0	0
T8	210665	0	0	0
T9	25206	0	0	0
T10	15202	0	0	0
T11	13061	6	0	0
T14	23318	0	0	0
T24	0	2	0	0
T25	0	12	0	0
T40	0	29	0	0
T48	0	29	0	0
T50	0	5	0	0
T51	0	9	0	0
T60	0	3	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53065581	13144	0	0
T1	11077	7	0	0
T2	12666	4	0	0
T3	29060	3	0	0
T4	24566	4	0	0
T5	5621	0	0	0
T6	742089	174	0	0
T7	14474	2	0	0
T8	210665	32	0	0
T9	25206	4	0	0
T10	15202	0	0	0
T11	0	6	0	0
T12	0	4	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53065581	962	0	0
T3	29060	3	0	0
T4	24566	0	0	0
T5	5621	0	0	0
T6	742089	20	0	0
T7	14474	0	0	0
T8	210665	0	0	0
T9	25206	0	0	0
T10	15202	0	0	0
T11	13061	6	0	0
T14	23318	0	0	0
T24	0	2	0	0
T25	0	12	0	0
T40	0	29	0	0
T48	0	29	0	0
T50	0	5	0	0
T51	0	9	0	0
T60	0	3	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26533460	13230	0	0
T1	5538	7	0	0
T2	6332	4	0	0
T3	14529	5	0	0
T4	12278	4	0	0
T5	2809	0	0	0
T6	371060	180	0	0
T7	7237	2	0	0
T8	105345	32	0	0
T9	12605	4	0	0
T10	7601	0	0	0
T11	0	6	0	0
T12	0	4	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26533460	1018	0	0
T3	14529	5	0	0
T4	12278	0	0	0
T5	2809	0	0	0
T6	371060	28	0	0
T7	7237	0	0	0
T8	105345	0	0	0
T9	12605	0	0	0
T10	7601	0	0	0
T11	6531	6	0	0
T14	11658	0	0	0
T25	0	9	0	0
T40	0	33	0	0
T48	0	34	0	0
T50	0	6	0	0
T51	0	11	0	0
T60	0	4	0	0
T82	0	22	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26533460	13230	0	0
T1	5538	7	0	0
T2	6332	4	0	0
T3	14529	5	0	0
T4	12278	4	0	0
T5	2809	0	0	0
T6	371060	180	0	0
T7	7237	2	0	0
T8	105345	32	0	0
T9	12605	4	0	0
T10	7601	0	0	0
T11	0	6	0	0
T12	0	4	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26533460	1018	0	0
T3	14529	5	0	0
T4	12278	0	0	0
T5	2809	0	0	0
T6	371060	28	0	0
T7	7237	0	0	0
T8	105345	0	0	0
T9	12605	0	0	0
T10	7601	0	0	0
T11	6531	6	0	0
T14	11658	0	0	0
T25	0	9	0	0
T40	0	33	0	0
T48	0	34	0	0
T50	0	6	0	0
T51	0	11	0	0
T60	0	4	0	0
T82	0	22	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26533318	13233	0	0
T1	5537	7	0	0
T2	6332	4	0	0
T3	14529	5	0	0
T4	12280	5	0	0
T5	2809	0	0	0
T6	371053	174	0	0
T7	7239	2	0	0
T8	105343	32	0	0
T9	12603	4	0	0
T10	7600	0	0	0
T11	0	7	0	0
T12	0	5	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26533318	1013	0	0
T3	14529	5	0	0
T4	12280	1	0	0
T5	2809	0	0	0
T6	371053	22	0	0
T7	7239	0	0	0
T8	105343	0	0	0
T9	12603	0	0	0
T10	7600	0	0	0
T11	6531	7	0	0
T12	0	1	0	0
T14	11656	0	0	0
T25	0	9	0	0
T40	0	32	0	0
T48	0	30	0	0
T50	0	5	0	0
T60	0	4	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26533318	13233	0	0
T1	5537	7	0	0
T2	6332	4	0	0
T3	14529	5	0	0
T4	12280	5	0	0
T5	2809	0	0	0
T6	371053	174	0	0
T7	7239	2	0	0
T8	105343	32	0	0
T9	12603	4	0	0
T10	7600	0	0	0
T11	0	7	0	0
T12	0	5	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26533318	1013	0	0
T3	14529	5	0	0
T4	12280	1	0	0
T5	2809	0	0	0
T6	371053	22	0	0
T7	7239	0	0	0
T8	105343	0	0	0
T9	12603	0	0	0
T10	7600	0	0	0
T11	6531	7	0	0
T12	0	1	0	0
T14	11656	0	0	0
T25	0	9	0	0
T40	0	32	0	0
T48	0	30	0	0
T50	0	5	0	0
T60	0	4	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1676357	22258	0	0
T1	344	8	0	0
T2	393	6	0	0
T3	906	8	0	0
T4	766	6	0	0
T5	174	1	0	0
T6	23465	284	0	0
T7	451	5	0	0
T8	6619	60	0	0
T9	786	6	0	0
T10	474	2	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1676357	1080	0	0
T3	906	7	0	0
T4	766	0	0	0
T5	174	0	0	0
T6	23465	26	0	0
T7	451	0	0	0
T8	6619	0	0	0
T9	786	0	0	0
T10	474	0	0	0
T11	406	7	0	0
T14	731	0	0	0
T25	0	11	0	0
T40	0	25	0	0
T48	0	36	0	0
T50	0	8	0	0
T51	0	12	0	0
T60	0	7	0	0
T82	0	25	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1676357	22258	0	0
T1	344	8	0	0
T2	393	6	0	0
T3	906	8	0	0
T4	766	6	0	0
T5	174	1	0	0
T6	23465	284	0	0
T7	451	5	0	0
T8	6619	60	0	0
T9	786	6	0	0
T10	474	2	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1676357	1080	0	0
T3	906	7	0	0
T4	766	0	0	0
T5	174	0	0	0
T6	23465	26	0	0
T7	451	0	0	0
T8	6619	0	0	0
T9	786	0	0	0
T10	474	0	0	0
T11	406	7	0	0
T14	731	0	0	0
T25	0	11	0	0
T40	0	25	0	0
T48	0	36	0	0
T50	0	8	0	0
T51	0	12	0	0
T60	0	7	0	0
T82	0	25	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13266535	14691	0	0
T1	2769	7	0	0
T2	3165	5	0	0
T3	7264	9	0	0
T4	6140	4	0	0
T5	1405	0	0	0
T6	185534	188	0	0
T7	3618	4	0	0
T8	52668	33	0	0
T9	6301	4	0	0
T10	3800	0	0	0
T11	0	9	0	0
T12	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13266535	1146	0	0
T3	7264	9	0	0
T4	6140	0	0	0
T5	1405	0	0	0
T6	185534	22	0	0
T7	3618	0	0	0
T8	52668	0	0	0
T9	6301	0	0	0
T10	3800	0	0	0
T11	3265	9	0	0
T14	5830	0	0	0
T25	0	11	0	0
T40	0	36	0	0
T48	0	32	0	0
T50	0	10	0	0
T51	0	13	0	0
T60	0	8	0	0
T82	0	25	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13266535	14691	0	0
T1	2769	7	0	0
T2	3165	5	0	0
T3	7264	9	0	0
T4	6140	4	0	0
T5	1405	0	0	0
T6	185534	188	0	0
T7	3618	4	0	0
T8	52668	33	0	0
T9	6301	4	0	0
T10	3800	0	0	0
T11	0	9	0	0
T12	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13266535	1146	0	0
T3	7264	9	0	0
T4	6140	0	0	0
T5	1405	0	0	0
T6	185534	22	0	0
T7	3618	0	0	0
T8	52668	0	0	0
T9	6301	0	0	0
T10	3800	0	0	0
T11	3265	9	0	0
T14	5830	0	0	0
T25	0	11	0	0
T40	0	36	0	0
T48	0	32	0	0
T50	0	10	0	0
T51	0	13	0	0
T60	0	8	0	0
T82	0	25	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13266535	14718	0	0
T1	2769	7	0	0
T2	3165	5	0	0
T3	7264	8	0	0
T4	6140	4	0	0
T5	1405	0	0	0
T6	185534	191	0	0
T7	3618	4	0	0
T8	52668	33	0	0
T9	6301	5	0	0
T10	3800	0	0	0
T11	0	11	0	0
T12	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13266535	1168	0	0
T3	7264	8	0	0
T4	6140	0	0	0
T5	1405	0	0	0
T6	185534	23	0	0
T7	3618	0	0	0
T8	52668	0	0	0
T9	6301	1	0	0
T10	3800	0	0	0
T11	3265	11	0	0
T14	5830	0	0	0
T25	0	10	0	0
T40	0	30	0	0
T48	0	25	0	0
T50	0	9	0	0
T51	0	14	0	0
T60	0	8	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13266535	14718	0	0
T1	2769	7	0	0
T2	3165	5	0	0
T3	7264	8	0	0
T4	6140	4	0	0
T5	1405	0	0	0
T6	185534	191	0	0
T7	3618	4	0	0
T8	52668	33	0	0
T9	6301	5	0	0
T10	3800	0	0	0
T11	0	11	0	0
T12	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13266535	1168	0	0
T3	7264	8	0	0
T4	6140	0	0	0
T5	1405	0	0	0
T6	185534	23	0	0
T7	3618	0	0	0
T8	52668	0	0	0
T9	6301	1	0	0
T10	3800	0	0	0
T11	3265	11	0	0
T14	5830	0	0	0
T25	0	10	0	0
T40	0	30	0	0
T48	0	25	0	0
T50	0	9	0	0
T51	0	14	0	0
T60	0	8	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13266535	14782	0	0
T1	2769	7	0	0
T2	3165	5	0	0
T3	7264	10	0	0
T4	6140	4	0	0
T5	1405	0	0	0
T6	185534	186	0	0
T7	3618	4	0	0
T8	52668	33	0	0
T9	6301	5	0	0
T10	3800	0	0	0
T11	0	11	0	0
T12	0	4	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13266535	1228	0	0
T3	7264	10	0	0
T4	6140	0	0	0
T5	1405	0	0	0
T6	185534	18	0	0
T7	3618	0	0	0
T8	52668	0	0	0
T9	6301	1	0	0
T10	3800	0	0	0
T11	3265	11	0	0
T14	5830	0	0	0
T25	0	11	0	0
T40	0	36	0	0
T48	0	29	0	0
T50	0	11	0	0
T51	0	12	0	0
T60	0	9	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13266535	14782	0	0
T1	2769	7	0	0
T2	3165	5	0	0
T3	7264	10	0	0
T4	6140	4	0	0
T5	1405	0	0	0
T6	185534	186	0	0
T7	3618	4	0	0
T8	52668	33	0	0
T9	6301	5	0	0
T10	3800	0	0	0
T11	0	11	0	0
T12	0	4	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13266535	1228	0	0
T3	7264	10	0	0
T4	6140	0	0	0
T5	1405	0	0	0
T6	185534	18	0	0
T7	3618	0	0	0
T8	52668	0	0	0
T9	6301	1	0	0
T10	3800	0	0	0
T11	3265	11	0	0
T14	5830	0	0	0
T25	0	11	0	0
T40	0	36	0	0
T48	0	29	0	0
T50	0	11	0	0
T51	0	12	0	0
T60	0	9	0	0