Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12539163	8801	0	0
alert_regwen_rd_A	12539163	4600	0	0
cpu_regwen_rd_A	12539163	4528	0	0
sw_rst_ctrl_n_0_rd_A	12539163	6945	0	0
sw_rst_ctrl_n_1_rd_A	12539163	6826	0	0
sw_rst_ctrl_n_2_rd_A	12539163	6953	0	0
sw_rst_ctrl_n_3_rd_A	12539163	7023	0	0
sw_rst_ctrl_n_4_rd_A	12539163	7284	0	0
sw_rst_ctrl_n_5_rd_A	12539163	7056	0	0
sw_rst_ctrl_n_6_rd_A	12539163	7043	0	0
sw_rst_ctrl_n_7_rd_A	12539163	7025	0	0
sw_rst_regwen_0_rd_A	12539163	4818	0	0
sw_rst_regwen_1_rd_A	12539163	4737	0	0
sw_rst_regwen_2_rd_A	12539163	4640	0	0
sw_rst_regwen_3_rd_A	12539163	4894	0	0
sw_rst_regwen_4_rd_A	12539163	4870	0	0
sw_rst_regwen_5_rd_A	12539163	4983	0	0
sw_rst_regwen_6_rd_A	12539163	4868	0	0
sw_rst_regwen_7_rd_A	12539163	4649	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539163	8801	0	0
T62	17862	2	0	0
T63	20664	4	0	0
T65	22013	4	0	0
T66	2671	147	0	0
T67	4092	596	0	0
T68	2529	3	0	0
T85	2657	8	0	0
T86	3612	101	0	0
T87	7039	197	0	0
T88	3110	121	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539163	4600	0	0
T8	46916	101	0	0
T9	6157	0	0	0
T10	3709	0	0	0
T11	3198	0	0	0
T12	4412	0	0	0
T13	26028	0	0	0
T14	5284	0	0	0
T24	2294	0	0	0
T25	184571	252	0	0
T26	1639	0	0	0
T59	0	13	0	0
T74	0	74	0	0
T92	0	79	0	0
T119	0	58	0	0
T120	0	30	0	0
T121	0	135	0	0
T122	0	128	0	0
T123	0	53	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539163	4528	0	0
T8	46916	57	0	0
T9	6157	0	0	0
T10	3709	0	0	0
T11	3198	0	0	0
T12	4412	0	0	0
T13	26028	0	0	0
T14	5284	0	0	0
T24	2294	0	0	0
T25	184571	278	0	0
T26	1639	0	0	0
T59	0	13	0	0
T74	0	81	0	0
T92	0	83	0	0
T119	0	52	0	0
T120	0	46	0	0
T121	0	124	0	0
T122	0	131	0	0
T123	0	41	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539163	6945	0	0
T2	2669	18	0	0
T3	7221	0	0	0
T4	5946	25	0	0
T5	1314	0	0	0
T6	161877	0	0	0
T7	3328	0	0	0
T8	46916	112	0	0
T9	6157	17	0	0
T10	3709	0	0	0
T11	3198	0	0	0
T25	0	407	0	0
T51	0	128	0	0
T59	0	20	0	0
T92	0	215	0	0
T124	0	18	0	0
T125	0	11	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539163	6826	0	0
T2	2669	17	0	0
T3	7221	0	0	0
T4	5946	12	0	0
T5	1314	0	0	0
T6	161877	0	0	0
T7	3328	0	0	0
T8	46916	80	0	0
T9	6157	8	0	0
T10	3709	0	0	0
T11	3198	0	0	0
T25	0	428	0	0
T51	0	120	0	0
T59	0	15	0	0
T92	0	256	0	0
T124	0	19	0	0
T125	0	22	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539163	6953	0	0
T2	2669	23	0	0
T3	7221	0	0	0
T4	5946	9	0	0
T5	1314	0	0	0
T6	161877	0	0	0
T7	3328	0	0	0
T8	46916	69	0	0
T9	6157	4	0	0
T10	3709	0	0	0
T11	3198	0	0	0
T25	0	397	0	0
T51	0	148	0	0
T59	0	19	0	0
T92	0	239	0	0
T124	0	6	0	0
T125	0	8	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539163	7023	0	0
T2	2669	16	0	0
T3	7221	0	0	0
T4	5946	13	0	0
T5	1314	0	0	0
T6	161877	0	0	0
T7	3328	0	0	0
T8	46916	72	0	0
T9	6157	9	0	0
T10	3709	0	0	0
T11	3198	0	0	0
T25	0	401	0	0
T51	0	144	0	0
T59	0	21	0	0
T92	0	284	0	0
T124	0	17	0	0
T125	0	15	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539163	7284	0	0
T2	2669	19	0	0
T3	7221	0	0	0
T4	5946	21	0	0
T5	1314	0	0	0
T6	161877	0	0	0
T7	3328	0	0	0
T8	46916	79	0	0
T9	6157	16	0	0
T10	3709	0	0	0
T11	3198	0	0	0
T25	0	420	0	0
T51	0	77	0	0
T59	0	38	0	0
T92	0	258	0	0
T124	0	20	0	0
T125	0	18	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539163	7056	0	0
T2	2669	17	0	0
T3	7221	0	0	0
T4	5946	20	0	0
T5	1314	0	0	0
T6	161877	0	0	0
T7	3328	0	0	0
T8	46916	91	0	0
T9	6157	19	0	0
T10	3709	0	0	0
T11	3198	0	0	0
T25	0	403	0	0
T51	0	173	0	0
T59	0	31	0	0
T92	0	233	0	0
T124	0	13	0	0
T125	0	11	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539163	7043	0	0
T2	2669	13	0	0
T3	7221	0	0	0
T4	5946	14	0	0
T5	1314	0	0	0
T6	161877	0	0	0
T7	3328	0	0	0
T8	46916	84	0	0
T9	6157	15	0	0
T10	3709	0	0	0
T11	3198	0	0	0
T25	0	388	0	0
T51	0	115	0	0
T59	0	21	0	0
T92	0	242	0	0
T124	0	16	0	0
T125	0	9	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539163	7025	0	0
T2	2669	20	0	0
T3	7221	0	0	0
T4	5946	3	0	0
T5	1314	0	0	0
T6	161877	0	0	0
T7	3328	0	0	0
T8	46916	93	0	0
T9	6157	18	0	0
T10	3709	0	0	0
T11	3198	0	0	0
T25	0	364	0	0
T51	0	101	0	0
T59	0	16	0	0
T92	0	219	0	0
T124	0	15	0	0
T125	0	4	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539163	4818	0	0
T4	5946	16	0	0
T5	1314	0	0	0
T6	161877	0	0	0
T7	3328	0	0	0
T8	46916	97	0	0
T9	6157	12	0	0
T10	3709	0	0	0
T11	3198	0	0	0
T12	4412	0	0	0
T14	5284	0	0	0
T25	0	302	0	0
T51	0	30	0	0
T59	0	34	0	0
T92	0	107	0	0
T124	0	4	0	0
T125	0	10	0	0
T126	0	28	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539163	4737	0	0
T4	5946	6	0	0
T5	1314	0	0	0
T6	161877	0	0	0
T7	3328	0	0	0
T8	46916	103	0	0
T9	6157	11	0	0
T10	3709	0	0	0
T11	3198	0	0	0
T12	4412	0	0	0
T14	5284	0	0	0
T25	0	284	0	0
T51	0	17	0	0
T59	0	6	0	0
T92	0	68	0	0
T124	0	6	0	0
T125	0	7	0	0
T126	0	45	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539163	4640	0	0
T4	5946	8	0	0
T5	1314	0	0	0
T6	161877	0	0	0
T7	3328	0	0	0
T8	46916	86	0	0
T9	6157	3	0	0
T10	3709	0	0	0
T11	3198	0	0	0
T12	4412	0	0	0
T14	5284	0	0	0
T25	0	225	0	0
T51	0	29	0	0
T59	0	32	0	0
T92	0	108	0	0
T124	0	8	0	0
T125	0	3	0	0
T126	0	30	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539163	4894	0	0
T4	5946	12	0	0
T5	1314	0	0	0
T6	161877	0	0	0
T7	3328	0	0	0
T8	46916	101	0	0
T9	6157	12	0	0
T10	3709	0	0	0
T11	3198	0	0	0
T12	4412	0	0	0
T14	5284	0	0	0
T25	0	232	0	0
T51	0	22	0	0
T59	0	27	0	0
T92	0	99	0	0
T124	0	16	0	0
T125	0	7	0	0
T126	0	33	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539163	4870	0	0
T4	5946	12	0	0
T5	1314	0	0	0
T6	161877	0	0	0
T7	3328	0	0	0
T8	46916	95	0	0
T9	6157	3	0	0
T10	3709	0	0	0
T11	3198	0	0	0
T12	4412	0	0	0
T14	5284	0	0	0
T25	0	293	0	0
T51	0	10	0	0
T59	0	39	0	0
T92	0	81	0	0
T124	0	1	0	0
T125	0	5	0	0
T126	0	18	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539163	4983	0	0
T4	5946	10	0	0
T5	1314	0	0	0
T6	161877	0	0	0
T7	3328	0	0	0
T8	46916	97	0	0
T9	6157	12	0	0
T10	3709	0	0	0
T11	3198	0	0	0
T12	4412	0	0	0
T14	5284	0	0	0
T25	0	248	0	0
T51	0	18	0	0
T59	0	39	0	0
T92	0	84	0	0
T124	0	8	0	0
T125	0	4	0	0
T126	0	18	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539163	4868	0	0
T4	5946	7	0	0
T5	1314	0	0	0
T6	161877	0	0	0
T7	3328	0	0	0
T8	46916	120	0	0
T9	6157	6	0	0
T10	3709	0	0	0
T11	3198	0	0	0
T12	4412	0	0	0
T14	5284	0	0	0
T25	0	254	0	0
T51	0	31	0	0
T59	0	16	0	0
T92	0	92	0	0
T124	0	6	0	0
T125	0	7	0	0
T126	0	23	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12539163	4649	0	0
T4	5946	5	0	0
T5	1314	0	0	0
T6	161877	0	0	0
T7	3328	0	0	0
T8	46916	79	0	0
T9	6157	11	0	0
T10	3709	0	0	0
T11	3198	0	0	0
T12	4412	0	0	0
T14	5284	0	0	0
T25	0	269	0	0
T51	0	11	0	0
T59	0	18	0	0
T92	0	101	0	0
T124	0	4	0	0
T125	0	7	0	0
T126	0	37	0	0