Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	620893	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

372525

1

T1

3036

T2

77

T4

86

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	529502	1			T1	4392		T2	99		T4	126
values[0x0]	231057	1			T1	1962		T2	53		T4	66
values[0x1]	232859	1			T1	1980		T2	60		T4	63

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	521399	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

472019

1

T1

3840

T2

101

T4

116

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4500	1			T1	78		T11	93		T12	3
valid_sources[0x01]	4150	1			T1	18		T6	5		T11	59
valid_sources[0x02]	3634	1			T1	18		T6	1		T11	73
valid_sources[0x03]	3819	1			T1	72		T11	73		T12	11
valid_sources[0x04]	4852	1			T1	22		T5	180		T11	58
valid_sources[0x05]	3838	1			T1	67		T5	70		T11	64
valid_sources[0x06]	3451	1			T1	10		T6	4		T11	79
valid_sources[0x07]	3744	1			T1	34		T7	1		T11	71
valid_sources[0x08]	4119	1			T1	32		T11	62		T12	6
valid_sources[0x09]	3480	1			T1	36		T10	10		T11	64
valid_sources[0x0a]	3389	1			T1	16		T11	90		T12	18
valid_sources[0x0b]	4705	1			T1	32		T11	76		T12	28
valid_sources[0x0c]	3497	1			T1	71		T6	3		T11	62
valid_sources[0x0d]	4528	1			T1	9		T6	1		T11	70
valid_sources[0x0e]	5480	1			T1	70		T11	79		T12	34
valid_sources[0x0f]	3069	1			T1	16		T11	71		T12	27
valid_sources[0x10]	3378	1			T1	36		T11	70		T12	11
valid_sources[0x11]	3236	1			T1	48		T6	2		T11	81
valid_sources[0x12]	7171	1			T1	83		T5	13		T11	70
valid_sources[0x13]	3629	1			T1	12		T11	75		T12	42
valid_sources[0x14]	3379	1			T1	50		T11	81		T12	41
valid_sources[0x15]	3684	1			T1	4		T5	326		T11	78
valid_sources[0x16]	4766	1			T1	39		T11	77		T12	26
valid_sources[0x17]	3702	1			T1	68		T11	75		T12	45
valid_sources[0x18]	3981	1			T1	35		T11	70		T12	17
valid_sources[0x19]	3452	1			T1	14		T6	2		T11	81
valid_sources[0x1a]	3344	1			T1	31		T11	91		T12	20
valid_sources[0x1b]	4767	1			T1	52		T2	32		T6	1
valid_sources[0x1c]	4354	1			T1	38		T11	85		T12	36
valid_sources[0x1d]	3070	1			T1	2		T11	78		T12	39
valid_sources[0x1e]	3592	1			T1	67		T11	73		T12	21
valid_sources[0x1f]	3380	1			T1	14		T11	72		T12	20
valid_sources[0x20]	3292	1			T1	21		T5	12		T11	82
valid_sources[0x21]	6278	1			T1	50		T11	82		T12	12
valid_sources[0x22]	4214	1			T11	78		T12	21		T14	1
valid_sources[0x23]	3183	1			T1	4		T6	1		T11	98
valid_sources[0x24]	6603	1			T1	8		T11	90		T12	2
valid_sources[0x25]	4152	1			T1	14		T5	2		T6	3
valid_sources[0x26]	3368	1			T1	47		T5	3		T11	83
valid_sources[0x27]	3623	1			T1	21		T11	90		T12	24
valid_sources[0x28]	3623	1			T1	15		T11	80		T12	50
valid_sources[0x29]	3276	1			T1	36		T6	5		T11	90
valid_sources[0x2a]	3468	1			T1	39		T11	74		T12	7
valid_sources[0x2b]	6751	1			T1	44		T5	112		T6	1
valid_sources[0x2c]	3717	1			T1	15		T6	3		T11	80
valid_sources[0x2d]	3419	1			T1	36		T6	7		T11	68
valid_sources[0x2e]	3519	1			T1	5		T11	76		T12	43
valid_sources[0x2f]	3592	1			T1	3		T11	78		T12	19
valid_sources[0x30]	3671	1			T1	4		T6	6		T11	95
valid_sources[0x31]	3548	1			T1	43		T6	13		T11	87
valid_sources[0x32]	3743	1			T1	53		T11	101		T14	7
valid_sources[0x33]	3443	1			T1	47		T2	85		T6	2
valid_sources[0x34]	3419	1			T1	31		T11	70		T12	19
valid_sources[0x35]	3709	1			T1	17		T11	86		T12	106
valid_sources[0x36]	3128	1			T1	23		T11	80		T12	15
valid_sources[0x37]	3494	1			T1	27		T11	82		T12	38
valid_sources[0x38]	5260	1			T1	22		T11	92		T12	24
valid_sources[0x39]	4171	1			T1	7		T11	95		T12	52
valid_sources[0x3a]	3500	1			T1	9		T11	88		T12	3
valid_sources[0x3b]	3018	1			T1	47		T6	1		T11	76
valid_sources[0x3c]	3535	1			T1	7		T6	2		T11	83
valid_sources[0x3d]	4106	1			T1	57		T5	143		T11	71
valid_sources[0x3e]	3577	1			T1	27		T6	1		T11	74
valid_sources[0x3f]	5181	1			T1	74		T10	5		T11	75
valid_sources[0x40]	3709	1			T1	27		T7	1		T11	102
valid_sources[0x41]	3431	1			T1	54		T6	5		T11	71
valid_sources[0x42]	3230	1			T1	28		T11	74		T12	3
valid_sources[0x43]	3120	1			T1	35		T11	80		T14	7
valid_sources[0x44]	3767	1			T1	88		T11	69		T12	18
valid_sources[0x45]	4385	1			T1	46		T11	81		T12	19
valid_sources[0x46]	4101	1			T1	37		T6	5		T11	74
valid_sources[0x47]	4042	1			T1	22		T6	2		T11	60
valid_sources[0x48]	3118	1			T1	9		T6	3		T11	100
valid_sources[0x49]	3462	1			T1	32		T11	73		T12	29
valid_sources[0x4a]	4171	1			T1	25		T11	79		T12	59
valid_sources[0x4b]	3405	1			T1	39		T11	68		T12	24
valid_sources[0x4c]	4790	1			T11	81		T12	36		T14	2
valid_sources[0x4d]	3737	1			T1	30		T6	1		T11	86
valid_sources[0x4e]	3415	1			T1	1		T11	66		T12	21
valid_sources[0x4f]	5823	1			T1	30		T10	10		T11	82
valid_sources[0x50]	3523	1			T1	34		T11	80		T12	7
valid_sources[0x51]	3489	1			T1	7		T6	4		T11	76
valid_sources[0x52]	4507	1			T1	26		T2	6		T6	5
valid_sources[0x53]	3674	1			T1	2		T6	3		T9	1
valid_sources[0x54]	4106	1			T1	29		T11	84		T12	19
valid_sources[0x55]	7961	1			T1	49		T11	59		T12	21
valid_sources[0x56]	4154	1			T1	100		T11	77		T12	14
valid_sources[0x57]	4276	1			T6	3		T11	75		T12	30
valid_sources[0x58]	3289	1			T1	36		T11	72		T12	32
valid_sources[0x59]	3437	1			T1	21		T11	94		T12	49
valid_sources[0x5a]	3197	1			T1	33		T11	80		T12	10
valid_sources[0x5b]	3176	1			T1	21		T11	96		T12	57
valid_sources[0x5c]	3135	1			T1	7		T11	77		T12	7
valid_sources[0x5d]	3110	1			T1	31		T11	80		T12	23
valid_sources[0x5e]	4106	1			T1	16		T11	70		T12	32
valid_sources[0x5f]	4294	1			T1	23		T5	239		T11	65
valid_sources[0x60]	3840	1			T1	16		T11	65		T12	40
valid_sources[0x61]	3482	1			T1	87		T11	85		T12	36
valid_sources[0x62]	4195	1			T1	83		T6	4		T11	67
valid_sources[0x63]	3487	1			T1	22		T6	7		T11	83
valid_sources[0x64]	3184	1			T1	22		T11	76		T12	34
valid_sources[0x65]	3192	1			T1	23		T11	78		T12	10
valid_sources[0x66]	3897	1			T1	45		T6	1		T11	94
valid_sources[0x67]	3891	1			T1	33		T11	80		T12	33
valid_sources[0x68]	3340	1			T1	10		T6	4		T11	75
valid_sources[0x69]	3217	1			T1	29		T11	87		T12	36
valid_sources[0x6a]	2933	1			T1	22		T11	84		T12	4
valid_sources[0x6b]	6484	1			T1	2		T6	2		T11	68
valid_sources[0x6c]	7291	1			T1	17		T6	2		T11	86
valid_sources[0x6d]	3332	1			T1	40		T11	96		T12	42
valid_sources[0x6e]	3020	1			T1	47		T11	67		T12	16
valid_sources[0x6f]	6734	1			T1	75		T11	72		T12	19
valid_sources[0x70]	4649	1			T1	2		T6	7		T11	78
valid_sources[0x71]	3660	1			T1	44		T11	66		T12	16
valid_sources[0x72]	3728	1			T1	15		T5	2		T6	1
valid_sources[0x73]	5111	1			T1	53		T11	75		T12	34
valid_sources[0x74]	4083	1			T1	31		T11	74		T12	18
valid_sources[0x75]	2993	1			T1	60		T6	17		T11	89
valid_sources[0x76]	3613	1			T11	64		T12	15		T14	4
valid_sources[0x77]	3027	1			T1	11		T11	70		T12	21
valid_sources[0x78]	3146	1			T1	47		T11	59		T12	55
valid_sources[0x79]	4125	1			T1	52		T11	76		T12	13
valid_sources[0x7a]	3110	1			T1	27		T6	1		T7	1
valid_sources[0x7b]	4256	1			T1	14		T11	89		T12	36
valid_sources[0x7c]	4629	1			T1	55		T7	1		T9	1
valid_sources[0x7d]	4187	1			T1	1		T5	5		T11	73
valid_sources[0x7e]	3365	1			T1	24		T11	78		T12	17
valid_sources[0x7f]	4633	1			T1	12		T11	85		T12	36
valid_sources[0x80]	6697	1			T1	74		T10	1		T11	77

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

248325

1

T1

2082

T2

51

T4

55

values[0x0]

all_enables

biggest_size

80739

1

T1

627

T2

12

T4

24

values[0x1]

all_enables

biggest_size

43461

1

T1

327

T2

14

T4

7