Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	12028194	13198	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	12028194	121737	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	12028194	7027440	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	12028194	194048	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	12028194	13198	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	12028194	121737	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	12028194	7027440	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	12028194	194048	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028194	13198	0	0
T1	94121	104	0	0
T2	3466	4	0	0
T3	5495	0	0	0
T4	4508	14	0	0
T5	16391	39	0	0
T6	2551	16	0	0
T7	1372	0	0	0
T8	5477	0	0	0
T9	1225	0	0	0
T10	1525	2	0	0
T11	0	258	0	0
T12	0	76	0	0
T15	0	4	0	0
T27	0	34	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028194	121737	0	0
T1	94121	963	0	0
T2	3466	37	0	0
T3	5495	0	0	0
T4	4508	126	0	0
T5	16391	356	0	0
T6	2551	144	0	0
T7	1372	0	0	0
T8	5477	0	0	0
T9	1225	0	0	0
T10	1525	18	0	0
T11	0	2342	0	0
T12	0	702	0	0
T15	0	38	0	0
T27	0	312	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028194	7027440	0	0
T1	94121	73110	0	0
T2	3466	2459	0	0
T3	5495	589	0	0
T4	4508	3733	0	0
T5	16391	8048	0	0
T6	2551	1705	0	0
T7	1372	776	0	0
T8	5477	570	0	0
T9	1225	611	0	0
T10	1525	852	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028194	194048	0	0
T1	94121	1484	0	0
T2	3466	55	0	0
T3	5495	0	0	0
T4	4508	206	0	0
T5	16391	579	0	0
T6	2551	249	0	0
T7	1372	0	0	0
T8	5477	0	0	0
T9	1225	0	0	0
T10	1525	35	0	0
T11	0	3719	0	0
T12	0	1092	0	0
T15	0	65	0	0
T27	0	504	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028194	13198	0	0
T1	94121	104	0	0
T2	3466	4	0	0
T3	5495	0	0	0
T4	4508	14	0	0
T5	16391	39	0	0
T6	2551	16	0	0
T7	1372	0	0	0
T8	5477	0	0	0
T9	1225	0	0	0
T10	1525	2	0	0
T11	0	258	0	0
T12	0	76	0	0
T15	0	4	0	0
T27	0	34	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028194	121737	0	0
T1	94121	963	0	0
T2	3466	37	0	0
T3	5495	0	0	0
T4	4508	126	0	0
T5	16391	356	0	0
T6	2551	144	0	0
T7	1372	0	0	0
T8	5477	0	0	0
T9	1225	0	0	0
T10	1525	18	0	0
T11	0	2342	0	0
T12	0	702	0	0
T15	0	38	0	0
T27	0	312	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028194	7027440	0	0
T1	94121	73110	0	0
T2	3466	2459	0	0
T3	5495	589	0	0
T4	4508	3733	0	0
T5	16391	8048	0	0
T6	2551	1705	0	0
T7	1372	776	0	0
T8	5477	570	0	0
T9	1225	611	0	0
T10	1525	852	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028194	194048	0	0
T1	94121	1484	0	0
T2	3466	55	0	0
T3	5495	0	0	0
T4	4508	206	0	0
T5	16391	579	0	0
T6	2551	249	0	0
T7	1372	0	0	0
T8	5477	0	0	0
T9	1225	0	0	0
T10	1525	35	0	0
T11	0	3719	0	0
T12	0	1092	0	0
T15	0	65	0	0
T27	0	504	0	0