Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T5
0	1	Covered	T1,T2,T5
1	0	Covered	T1,T5,T11

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T3,T5
1	0	Covered	T1,T2,T5
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	56298923	9176	0	0
CascadeEffAonToRstPorAboveRise_A	56298923	9176	0	0
CascadeEffAonToRstPorIoAboveFall_A	54045513	9176	0	0
CascadeEffAonToRstPorIoAboveRise_A	54045513	9176	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	27024105	9176	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	27024105	9176	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13511509	9176	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13511509	9176	0	0
CascadeEffAonToRstPorUcbAboveFall_A	27023710	9176	0	0
CascadeEffAonToRstPorUcbAboveRise_A	27023710	9176	0	0
CascadeLcToLcAboveFall_A	56298923	22374	0	0
CascadeLcToLcAboveRise_A	56298923	22374	0	0
CascadeLcToLcAonAboveFall_A	1705869	22374	0	0
CascadeLcToLcAonAboveRise_A	1705869	22374	0	0
CascadeLcToLcShadowedAboveFall_A	56298923	22374	0	0
CascadeLcToLcShadowedAboveRise_A	56298923	22374	0	0
CascadePorToAonAboveFall_A	1705869	7303	0	0
CascadeSysToSysAboveFall_A	56298923	22374	0	0
CascadeSysToSysAboveRise_A	56298923	22374	0	0
ScanRstToAonRise_A	1705869	209	0	0
StablePorToAonRise_A	1705869	9176	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	12028194	22374	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	12028194	22374	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	12028194	22374	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	12028194	22374	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13511509	22374	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13511509	22374	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	12028194	22374	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	12028194	22374	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	12028194	22374	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	12028194	22374	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56298923	9176	0	0
T1	434685	46	0	0
T2	14856	2	0	0
T3	24367	8	0	0
T4	22439	1	0	0
T5	89503	18	0	0
T6	15331	1	0	0
T7	5998	1	0	0
T8	24294	8	0	0
T9	5286	1	0	0
T10	7090	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56298923	9176	0	0
T1	434685	46	0	0
T2	14856	2	0	0
T3	24367	8	0	0
T4	22439	1	0	0
T5	89503	18	0	0
T6	15331	1	0	0
T7	5998	1	0	0
T8	24294	8	0	0
T9	5286	1	0	0
T10	7090	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54045513	9176	0	0
T1	417289	46	0	0
T2	14254	2	0	0
T3	23393	8	0	0
T4	21541	1	0	0
T5	85955	18	0	0
T6	14716	1	0	0
T7	5757	1	0	0
T8	23319	8	0	0
T9	5075	1	0	0
T10	6807	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54045513	9176	0	0
T1	417289	46	0	0
T2	14254	2	0	0
T3	23393	8	0	0
T4	21541	1	0	0
T5	85955	18	0	0
T6	14716	1	0	0
T7	5757	1	0	0
T8	23319	8	0	0
T9	5075	1	0	0
T10	6807	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27024105	9176	0	0
T1	208663	46	0	0
T2	7129	2	0	0
T3	11694	8	0	0
T4	10769	1	0	0
T5	42975	18	0	0
T6	7358	1	0	0
T7	2877	1	0	0
T8	11661	8	0	0
T9	2536	1	0	0
T10	3402	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27024105	9176	0	0
T1	208663	46	0	0
T2	7129	2	0	0
T3	11694	8	0	0
T4	10769	1	0	0
T5	42975	18	0	0
T6	7358	1	0	0
T7	2877	1	0	0
T8	11661	8	0	0
T9	2536	1	0	0
T10	3402	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13511509	9176	0	0
T1	104334	46	0	0
T2	3563	2	0	0
T3	5848	8	0	0
T4	5383	1	0	0
T5	21483	18	0	0
T6	3677	1	0	0
T7	1438	1	0	0
T8	5831	8	0	0
T9	1268	1	0	0
T10	1701	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13511509	9176	0	0
T1	104334	46	0	0
T2	3563	2	0	0
T3	5848	8	0	0
T4	5383	1	0	0
T5	21483	18	0	0
T6	3677	1	0	0
T7	1438	1	0	0
T8	5831	8	0	0
T9	1268	1	0	0
T10	1701	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27023710	9176	0	0
T1	208667	46	0	0
T2	7131	2	0	0
T3	11694	8	0	0
T4	10770	1	0	0
T5	42967	18	0	0
T6	7358	1	0	0
T7	2877	1	0	0
T8	11665	8	0	0
T9	2537	1	0	0
T10	3403	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27023710	9176	0	0
T1	208667	46	0	0
T2	7131	2	0	0
T3	11694	8	0	0
T4	10770	1	0	0
T5	42967	18	0	0
T6	7358	1	0	0
T7	2877	1	0	0
T8	11665	8	0	0
T9	2537	1	0	0
T10	3403	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56298923	22374	0	0
T1	434685	150	0	0
T2	14856	6	0	0
T3	24367	8	0	0
T4	22439	15	0	0
T5	89503	57	0	0
T6	15331	17	0	0
T7	5998	1	0	0
T8	24294	8	0	0
T9	5286	1	0	0
T10	7090	3	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56298923	22374	0	0
T1	434685	150	0	0
T2	14856	6	0	0
T3	24367	8	0	0
T4	22439	15	0	0
T5	89503	57	0	0
T6	15331	17	0	0
T7	5998	1	0	0
T8	24294	8	0	0
T9	5286	1	0	0
T10	7090	3	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705869	22374	0	0
T1	13242	150	0	0
T2	444	6	0	0
T3	733	8	0	0
T4	672	15	0	0
T5	2747	57	0	0
T6	458	17	0	0
T7	179	1	0	0
T8	731	8	0	0
T9	158	1	0	0
T10	212	3	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705869	22374	0	0
T1	13242	150	0	0
T2	444	6	0	0
T3	733	8	0	0
T4	672	15	0	0
T5	2747	57	0	0
T6	458	17	0	0
T7	179	1	0	0
T8	731	8	0	0
T9	158	1	0	0
T10	212	3	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56298923	22374	0	0
T1	434685	150	0	0
T2	14856	6	0	0
T3	24367	8	0	0
T4	22439	15	0	0
T5	89503	57	0	0
T6	15331	17	0	0
T7	5998	1	0	0
T8	24294	8	0	0
T9	5286	1	0	0
T10	7090	3	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56298923	22374	0	0
T1	434685	150	0	0
T2	14856	6	0	0
T3	24367	8	0	0
T4	22439	15	0	0
T5	89503	57	0	0
T6	15331	17	0	0
T7	5998	1	0	0
T8	24294	8	0	0
T9	5286	1	0	0
T10	7090	3	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705869	7303	0	0
T1	13242	21	0	0
T2	444	1	0	0
T3	733	8	0	0
T4	672	1	0	0
T5	2747	9	0	0
T6	458	1	0	0
T7	179	1	0	0
T8	731	8	0	0
T9	158	1	0	0
T10	212	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56298923	22374	0	0
T1	434685	150	0	0
T2	14856	6	0	0
T3	24367	8	0	0
T4	22439	15	0	0
T5	89503	57	0	0
T6	15331	17	0	0
T7	5998	1	0	0
T8	24294	8	0	0
T9	5286	1	0	0
T10	7090	3	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	56298923	22374	0	0
T1	434685	150	0	0
T2	14856	6	0	0
T3	24367	8	0	0
T4	22439	15	0	0
T5	89503	57	0	0
T6	15331	17	0	0
T7	5998	1	0	0
T8	24294	8	0	0
T9	5286	1	0	0
T10	7090	3	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705869	209	0	0
T1	13242	1	0	0
T2	444	1	0	0
T3	733	0	0	0
T4	672	0	0	0
T5	2747	0	0	0
T6	458	0	0	0
T7	179	0	0	0
T8	731	0	0	0
T9	158	0	0	0
T10	212	0	0	0
T11	0	2	0	0
T12	0	1	0	0
T27	0	1	0	0
T29	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T104	0	1	0	0
T108	0	3	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705869	9176	0	0
T1	13242	46	0	0
T2	444	2	0	0
T3	733	8	0	0
T4	672	1	0	0
T5	2747	18	0	0
T6	458	1	0	0
T7	179	1	0	0
T8	731	8	0	0
T9	158	1	0	0
T10	212	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028194	22374	0	0
T1	94121	150	0	0
T2	3466	6	0	0
T3	5495	8	0	0
T4	4508	15	0	0
T5	16391	57	0	0
T6	2551	17	0	0
T7	1372	1	0	0
T8	5477	8	0	0
T9	1225	1	0	0
T10	1525	3	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028194	22374	0	0
T1	94121	150	0	0
T2	3466	6	0	0
T3	5495	8	0	0
T4	4508	15	0	0
T5	16391	57	0	0
T6	2551	17	0	0
T7	1372	1	0	0
T8	5477	8	0	0
T9	1225	1	0	0
T10	1525	3	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028194	22374	0	0
T1	94121	150	0	0
T2	3466	6	0	0
T3	5495	8	0	0
T4	4508	15	0	0
T5	16391	57	0	0
T6	2551	17	0	0
T7	1372	1	0	0
T8	5477	8	0	0
T9	1225	1	0	0
T10	1525	3	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028194	22374	0	0
T1	94121	150	0	0
T2	3466	6	0	0
T3	5495	8	0	0
T4	4508	15	0	0
T5	16391	57	0	0
T6	2551	17	0	0
T7	1372	1	0	0
T8	5477	8	0	0
T9	1225	1	0	0
T10	1525	3	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13511509	22374	0	0
T1	104334	150	0	0
T2	3563	6	0	0
T3	5848	8	0	0
T4	5383	15	0	0
T5	21483	57	0	0
T6	3677	17	0	0
T7	1438	1	0	0
T8	5831	8	0	0
T9	1268	1	0	0
T10	1701	3	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13511509	22374	0	0
T1	104334	150	0	0
T2	3563	6	0	0
T3	5848	8	0	0
T4	5383	15	0	0
T5	21483	57	0	0
T6	3677	17	0	0
T7	1438	1	0	0
T8	5831	8	0	0
T9	1268	1	0	0
T10	1701	3	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028194	22374	0	0
T1	94121	150	0	0
T2	3466	6	0	0
T3	5495	8	0	0
T4	4508	15	0	0
T5	16391	57	0	0
T6	2551	17	0	0
T7	1372	1	0	0
T8	5477	8	0	0
T9	1225	1	0	0
T10	1525	3	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028194	22374	0	0
T1	94121	150	0	0
T2	3466	6	0	0
T3	5495	8	0	0
T4	4508	15	0	0
T5	16391	57	0	0
T6	2551	17	0	0
T7	1372	1	0	0
T8	5477	8	0	0
T9	1225	1	0	0
T10	1525	3	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028194	22374	0	0
T1	94121	150	0	0
T2	3466	6	0	0
T3	5495	8	0	0
T4	4508	15	0	0
T5	16391	57	0	0
T6	2551	17	0	0
T7	1372	1	0	0
T8	5477	8	0	0
T9	1225	1	0	0
T10	1525	3	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12028194	22374	0	0
T1	94121	150	0	0
T2	3466	6	0	0
T3	5495	8	0	0
T4	4508	15	0	0
T5	16391	57	0	0
T6	2551	17	0	0
T7	1372	1	0	0
T8	5477	8	0	0
T9	1225	1	0	0
T10	1525	3	0	0