Unified Coverage Report :: Module :: rstmgr_sw_rst_sva_if

Module : rstmgr_sw_rst_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_sw_rst_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_sw_rst_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_sw_rst_sva_if

	Line No.	Total	Covered	Percent
TOTAL		8	8	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00
ALWAYS	21	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_sw_rst_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
21	8	8

---

Cond Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Covered	Percent
Conditions	24	24	100.00
Logical	24	24	100.00
Non-Logical	0	0
Event	0	0

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[0])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T4,T6
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[1])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T6,T10
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[2])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[3])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[4])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[5])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[6])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T2,T3

 LINE       21
 EXPRESSION (((!parent_rst_n)) || ((!ctrl_ns[7])))
             --------1--------    -------2-------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T11,T12
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_sw_rst_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	32	32	100.00	32	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	32	32	100.00	32	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions[0].RstEnOff_A	13511509	14118	0	0
gen_assertions[0].RstEnOn_A	13511509	1109	0	0
gen_assertions[0].RstNOff_A	13511509	14118	0	0
gen_assertions[0].RstNOn_A	13511509	1109	0	0
gen_assertions[1].RstEnOff_A	54045513	12810	0	0
gen_assertions[1].RstEnOn_A	54045513	1094	0	0
gen_assertions[1].RstNOff_A	54045513	12810	0	0
gen_assertions[1].RstNOn_A	54045513	1094	0	0
gen_assertions[2].RstEnOff_A	27024105	12829	0	0
gen_assertions[2].RstEnOn_A	27024105	1046	0	0
gen_assertions[2].RstNOff_A	27024105	12829	0	0
gen_assertions[2].RstNOn_A	27024105	1046	0	0
gen_assertions[3].RstEnOff_A	27023710	12921	0	0
gen_assertions[3].RstEnOn_A	27023710	1128	0	0
gen_assertions[3].RstNOff_A	27023710	12921	0	0
gen_assertions[3].RstNOn_A	27023710	1128	0	0
gen_assertions[4].RstEnOff_A	1705869	22265	0	0
gen_assertions[4].RstEnOn_A	1705869	1163	0	0
gen_assertions[4].RstNOff_A	1705869	22265	0	0
gen_assertions[4].RstNOn_A	1705869	1163	0	0
gen_assertions[5].RstEnOff_A	13511509	14370	0	0
gen_assertions[5].RstEnOn_A	13511509	1214	0	0
gen_assertions[5].RstNOff_A	13511509	14370	0	0
gen_assertions[5].RstNOn_A	13511509	1214	0	0
gen_assertions[6].RstEnOff_A	13511509	14433	0	0
gen_assertions[6].RstEnOn_A	13511509	1277	0	0
gen_assertions[6].RstNOff_A	13511509	14433	0	0
gen_assertions[6].RstNOn_A	13511509	1277	0	0
gen_assertions[7].RstEnOff_A	13511509	14438	0	0
gen_assertions[7].RstEnOn_A	13511509	1275	0	0
gen_assertions[7].RstNOff_A	13511509	14438	0	0
gen_assertions[7].RstNOn_A	13511509	1275	0	0

gen_assertions[0].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13511509	14118	0	0
T1	104334	123	0	0
T2	3563	4	0	0
T3	5848	0	0	0
T4	5383	14	0	0
T5	21483	39	0	0
T6	3677	16	0	0
T7	1438	0	0	0
T8	5831	0	0	0
T9	1268	0	0	0
T10	1701	2	0	0
T11	0	272	0	0
T12	0	88	0	0
T14	0	1	0	0
T15	0	5	0	0

gen_assertions[0].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13511509	1109	0	0
T1	104334	21	0	0
T2	3563	0	0	0
T3	5848	0	0	0
T4	5383	1	0	0
T5	21483	0	0	0
T6	3677	6	0	0
T7	1438	0	0	0
T8	5831	0	0	0
T9	1268	0	0	0
T10	1701	1	0	0
T11	0	15	0	0
T12	0	13	0	0
T14	0	1	0	0
T15	0	1	0	0
T29	0	20	0	0
T106	0	3	0	0

gen_assertions[0].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13511509	14118	0	0
T1	104334	123	0	0
T2	3563	4	0	0
T3	5848	0	0	0
T4	5383	14	0	0
T5	21483	39	0	0
T6	3677	16	0	0
T7	1438	0	0	0
T8	5831	0	0	0
T9	1268	0	0	0
T10	1701	2	0	0
T11	0	272	0	0
T12	0	88	0	0
T14	0	1	0	0
T15	0	5	0	0

gen_assertions[0].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13511509	1109	0	0
T1	104334	21	0	0
T2	3563	0	0	0
T3	5848	0	0	0
T4	5383	1	0	0
T5	21483	0	0	0
T6	3677	6	0	0
T7	1438	0	0	0
T8	5831	0	0	0
T9	1268	0	0	0
T10	1701	1	0	0
T11	0	15	0	0
T12	0	13	0	0
T14	0	1	0	0
T15	0	1	0	0
T29	0	20	0	0
T106	0	3	0	0

gen_assertions[1].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54045513	12810	0	0
T1	417289	117	0	0
T2	14254	3	0	0
T3	23393	0	0	0
T4	21541	14	0	0
T5	85955	36	0	0
T6	14716	15	0	0
T7	5757	0	0	0
T8	23319	0	0	0
T9	5075	0	0	0
T10	6807	2	0	0
T11	0	251	0	0
T12	0	81	0	0
T14	0	2	0	0
T15	0	3	0	0

gen_assertions[1].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54045513	1094	0	0
T1	417289	25	0	0
T2	14254	0	0	0
T3	23393	0	0	0
T4	21541	0	0	0
T5	85955	0	0	0
T6	14716	5	0	0
T7	5757	0	0	0
T8	23319	0	0	0
T9	5075	0	0	0
T10	6807	1	0	0
T11	0	16	0	0
T12	0	15	0	0
T14	0	2	0	0
T29	0	22	0	0
T69	0	3	0	0
T106	0	2	0	0
T107	0	4	0	0

gen_assertions[1].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54045513	12810	0	0
T1	417289	117	0	0
T2	14254	3	0	0
T3	23393	0	0	0
T4	21541	14	0	0
T5	85955	36	0	0
T6	14716	15	0	0
T7	5757	0	0	0
T8	23319	0	0	0
T9	5075	0	0	0
T10	6807	2	0	0
T11	0	251	0	0
T12	0	81	0	0
T14	0	2	0	0
T15	0	3	0	0

gen_assertions[1].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	54045513	1094	0	0
T1	417289	25	0	0
T2	14254	0	0	0
T3	23393	0	0	0
T4	21541	0	0	0
T5	85955	0	0	0
T6	14716	5	0	0
T7	5757	0	0	0
T8	23319	0	0	0
T9	5075	0	0	0
T10	6807	1	0	0
T11	0	16	0	0
T12	0	15	0	0
T14	0	2	0	0
T29	0	22	0	0
T69	0	3	0	0
T106	0	2	0	0
T107	0	4	0	0

gen_assertions[2].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27024105	12829	0	0
T1	208663	113	0	0
T2	7129	3	0	0
T3	11694	0	0	0
T4	10769	14	0	0
T5	42975	36	0	0
T6	7358	15	0	0
T7	2877	0	0	0
T8	11661	0	0	0
T9	2536	0	0	0
T10	3402	2	0	0
T11	0	251	0	0
T12	0	80	0	0
T14	0	3	0	0
T15	0	3	0	0

gen_assertions[2].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27024105	1046	0	0
T1	208663	21	0	0
T2	7129	0	0	0
T3	11694	0	0	0
T4	10769	0	0	0
T5	42975	0	0	0
T6	7358	0	0	0
T7	2877	0	0	0
T8	11661	0	0	0
T9	2536	0	0	0
T10	3402	0	0	0
T11	0	16	0	0
T12	0	15	0	0
T14	0	3	0	0
T29	0	15	0	0
T58	0	3	0	0
T68	0	1	0	0
T69	0	8	0	0
T108	0	6	0	0
T109	0	7	0	0

gen_assertions[2].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27024105	12829	0	0
T1	208663	113	0	0
T2	7129	3	0	0
T3	11694	0	0	0
T4	10769	14	0	0
T5	42975	36	0	0
T6	7358	15	0	0
T7	2877	0	0	0
T8	11661	0	0	0
T9	2536	0	0	0
T10	3402	2	0	0
T11	0	251	0	0
T12	0	80	0	0
T14	0	3	0	0
T15	0	3	0	0

gen_assertions[2].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27024105	1046	0	0
T1	208663	21	0	0
T2	7129	0	0	0
T3	11694	0	0	0
T4	10769	0	0	0
T5	42975	0	0	0
T6	7358	0	0	0
T7	2877	0	0	0
T8	11661	0	0	0
T9	2536	0	0	0
T10	3402	0	0	0
T11	0	16	0	0
T12	0	15	0	0
T14	0	3	0	0
T29	0	15	0	0
T58	0	3	0	0
T68	0	1	0	0
T69	0	8	0	0
T108	0	6	0	0
T109	0	7	0	0

gen_assertions[3].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27023710	12921	0	0
T1	208667	112	0	0
T2	7131	3	0	0
T3	11694	0	0	0
T4	10770	14	0	0
T5	42967	36	0	0
T6	7358	15	0	0
T7	2877	0	0	0
T8	11665	0	0	0
T9	2537	0	0	0
T10	3403	2	0	0
T11	0	252	0	0
T12	0	75	0	0
T14	0	4	0	0
T15	0	3	0	0

gen_assertions[3].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27023710	1128	0	0
T1	208667	20	0	0
T2	7131	0	0	0
T3	11694	0	0	0
T4	10770	0	0	0
T5	42967	0	0	0
T6	7358	0	0	0
T7	2877	0	0	0
T8	11665	0	0	0
T9	2537	0	0	0
T10	3403	0	0	0
T11	0	18	0	0
T12	0	9	0	0
T14	0	4	0	0
T29	0	18	0	0
T58	0	3	0	0
T68	0	1	0	0
T69	0	7	0	0
T108	0	8	0	0
T109	0	7	0	0

gen_assertions[3].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27023710	12921	0	0
T1	208667	112	0	0
T2	7131	3	0	0
T3	11694	0	0	0
T4	10770	14	0	0
T5	42967	36	0	0
T6	7358	15	0	0
T7	2877	0	0	0
T8	11665	0	0	0
T9	2537	0	0	0
T10	3403	2	0	0
T11	0	252	0	0
T12	0	75	0	0
T14	0	4	0	0
T15	0	3	0	0

gen_assertions[3].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	27023710	1128	0	0
T1	208667	20	0	0
T2	7131	0	0	0
T3	11694	0	0	0
T4	10770	0	0	0
T5	42967	0	0	0
T6	7358	0	0	0
T7	2877	0	0	0
T8	11665	0	0	0
T9	2537	0	0	0
T10	3403	0	0	0
T11	0	18	0	0
T12	0	9	0	0
T14	0	4	0	0
T29	0	18	0	0
T58	0	3	0	0
T68	0	1	0	0
T69	0	7	0	0
T108	0	8	0	0
T109	0	7	0	0

gen_assertions[4].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705869	22265	0	0
T1	13242	171	0	0
T2	444	6	0	0
T3	733	3	0	0
T4	672	15	0	0
T5	2747	57	0	0
T6	458	16	0	0
T7	179	1	0	0
T8	731	3	0	0
T9	158	1	0	0
T10	212	2	0	0

gen_assertions[4].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705869	1163	0	0
T1	13242	25	0	0
T2	444	0	0	0
T3	733	0	0	0
T4	672	0	0	0
T5	2747	0	0	0
T6	458	0	0	0
T7	179	0	0	0
T8	731	0	0	0
T9	158	0	0	0
T10	212	0	0	0
T11	0	16	0	0
T12	0	14	0	0
T14	0	4	0	0
T15	0	1	0	0
T29	0	23	0	0
T58	0	4	0	0
T69	0	10	0	0
T108	0	9	0	0
T109	0	6	0	0

gen_assertions[4].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705869	22265	0	0
T1	13242	171	0	0
T2	444	6	0	0
T3	733	3	0	0
T4	672	15	0	0
T5	2747	57	0	0
T6	458	16	0	0
T7	179	1	0	0
T8	731	3	0	0
T9	158	1	0	0
T10	212	2	0	0

gen_assertions[4].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1705869	1163	0	0
T1	13242	25	0	0
T2	444	0	0	0
T3	733	0	0	0
T4	672	0	0	0
T5	2747	0	0	0
T6	458	0	0	0
T7	179	0	0	0
T8	731	0	0	0
T9	158	0	0	0
T10	212	0	0	0
T11	0	16	0	0
T12	0	14	0	0
T14	0	4	0	0
T15	0	1	0	0
T29	0	23	0	0
T58	0	4	0	0
T69	0	10	0	0
T108	0	9	0	0
T109	0	6	0	0

gen_assertions[5].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13511509	14370	0	0
T1	104334	125	0	0
T2	3563	4	0	0
T3	5848	0	0	0
T4	5383	14	0	0
T5	21483	39	0	0
T6	3677	16	0	0
T7	1438	0	0	0
T8	5831	0	0	0
T9	1268	0	0	0
T10	1701	2	0	0
T11	0	273	0	0
T12	0	87	0	0
T14	0	6	0	0
T15	0	4	0	0

gen_assertions[5].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13511509	1214	0	0
T1	104334	22	0	0
T2	3563	0	0	0
T3	5848	0	0	0
T4	5383	0	0	0
T5	21483	0	0	0
T6	3677	0	0	0
T7	1438	0	0	0
T8	5831	0	0	0
T9	1268	0	0	0
T10	1701	0	0	0
T11	0	16	0	0
T12	0	11	0	0
T14	0	6	0	0
T29	0	18	0	0
T58	0	5	0	0
T69	0	9	0	0
T108	0	7	0	0
T109	0	11	0	0
T110	0	7	0	0

gen_assertions[5].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13511509	14370	0	0
T1	104334	125	0	0
T2	3563	4	0	0
T3	5848	0	0	0
T4	5383	14	0	0
T5	21483	39	0	0
T6	3677	16	0	0
T7	1438	0	0	0
T8	5831	0	0	0
T9	1268	0	0	0
T10	1701	2	0	0
T11	0	273	0	0
T12	0	87	0	0
T14	0	6	0	0
T15	0	4	0	0

gen_assertions[5].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13511509	1214	0	0
T1	104334	22	0	0
T2	3563	0	0	0
T3	5848	0	0	0
T4	5383	0	0	0
T5	21483	0	0	0
T6	3677	0	0	0
T7	1438	0	0	0
T8	5831	0	0	0
T9	1268	0	0	0
T10	1701	0	0	0
T11	0	16	0	0
T12	0	11	0	0
T14	0	6	0	0
T29	0	18	0	0
T58	0	5	0	0
T69	0	9	0	0
T108	0	7	0	0
T109	0	11	0	0
T110	0	7	0	0

gen_assertions[6].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13511509	14433	0	0
T1	104334	126	0	0
T2	3563	4	0	0
T3	5848	0	0	0
T4	5383	14	0	0
T5	21483	39	0	0
T6	3677	16	0	0
T7	1438	0	0	0
T8	5831	0	0	0
T9	1268	0	0	0
T10	1701	2	0	0
T11	0	272	0	0
T12	0	87	0	0
T14	0	6	0	0
T15	0	4	0	0

gen_assertions[6].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13511509	1277	0	0
T1	104334	24	0	0
T2	3563	0	0	0
T3	5848	0	0	0
T4	5383	0	0	0
T5	21483	0	0	0
T6	3677	0	0	0
T7	1438	0	0	0
T8	5831	0	0	0
T9	1268	0	0	0
T10	1701	0	0	0
T11	0	14	0	0
T12	0	12	0	0
T14	0	6	0	0
T29	0	20	0	0
T58	0	7	0	0
T68	0	1	0	0
T69	0	10	0	0
T108	0	6	0	0
T109	0	11	0	0

gen_assertions[6].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13511509	14433	0	0
T1	104334	126	0	0
T2	3563	4	0	0
T3	5848	0	0	0
T4	5383	14	0	0
T5	21483	39	0	0
T6	3677	16	0	0
T7	1438	0	0	0
T8	5831	0	0	0
T9	1268	0	0	0
T10	1701	2	0	0
T11	0	272	0	0
T12	0	87	0	0
T14	0	6	0	0
T15	0	4	0	0

gen_assertions[6].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13511509	1277	0	0
T1	104334	24	0	0
T2	3563	0	0	0
T3	5848	0	0	0
T4	5383	0	0	0
T5	21483	0	0	0
T6	3677	0	0	0
T7	1438	0	0	0
T8	5831	0	0	0
T9	1268	0	0	0
T10	1701	0	0	0
T11	0	14	0	0
T12	0	12	0	0
T14	0	6	0	0
T29	0	20	0	0
T58	0	7	0	0
T68	0	1	0	0
T69	0	10	0	0
T108	0	6	0	0
T109	0	11	0	0

gen_assertions[7].RstEnOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13511509	14438	0	0
T1	104334	125	0	0
T2	3563	4	0	0
T3	5848	0	0	0
T4	5383	14	0	0
T5	21483	39	0	0
T6	3677	16	0	0
T7	1438	0	0	0
T8	5831	0	0	0
T9	1268	0	0	0
T10	1701	2	0	0
T11	0	270	0	0
T12	0	85	0	0
T14	0	8	0	0
T15	0	5	0	0

gen_assertions[7].RstEnOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13511509	1275	0	0
T1	104334	22	0	0
T2	3563	0	0	0
T3	5848	0	0	0
T4	5383	0	0	0
T5	21483	0	0	0
T6	3677	0	0	0
T7	1438	0	0	0
T8	5831	0	0	0
T9	1268	0	0	0
T10	1701	0	0	0
T11	0	13	0	0
T12	0	9	0	0
T14	0	8	0	0
T15	0	1	0	0
T29	0	18	0	0
T58	0	8	0	0
T69	0	12	0	0
T108	0	6	0	0
T109	0	10	0	0

gen_assertions[7].RstNOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13511509	14438	0	0
T1	104334	125	0	0
T2	3563	4	0	0
T3	5848	0	0	0
T4	5383	14	0	0
T5	21483	39	0	0
T6	3677	16	0	0
T7	1438	0	0	0
T8	5831	0	0	0
T9	1268	0	0	0
T10	1701	2	0	0
T11	0	270	0	0
T12	0	85	0	0
T14	0	8	0	0
T15	0	5	0	0

gen_assertions[7].RstNOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13511509	1275	0	0
T1	104334	22	0	0
T2	3563	0	0	0
T3	5848	0	0	0
T4	5383	0	0	0
T5	21483	0	0	0
T6	3677	0	0	0
T7	1438	0	0	0
T8	5831	0	0	0
T9	1268	0	0	0
T10	1701	0	0	0
T11	0	13	0	0
T12	0	9	0	0
T14	0	8	0	0
T15	0	1	0	0
T29	0	18	0	0
T58	0	8	0	0
T69	0	12	0	0
T108	0	6	0	0
T109	0	10	0	0