Unified Coverage Report :: Module :: rstmgr_csr_assert_fpv

Module : rstmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_rstmgr_csr_assert_0/rstmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.rstmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : rstmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	12753494	9055	0	0
alert_regwen_rd_A	12753494	4369	0	0
cpu_regwen_rd_A	12753494	4324	0	0
sw_rst_ctrl_n_0_rd_A	12753494	9819	0	0
sw_rst_ctrl_n_1_rd_A	12753494	9582	0	0
sw_rst_ctrl_n_2_rd_A	12753494	9584	0	0
sw_rst_ctrl_n_3_rd_A	12753494	9939	0	0
sw_rst_ctrl_n_4_rd_A	12753494	9764	0	0
sw_rst_ctrl_n_5_rd_A	12753494	9810	0	0
sw_rst_ctrl_n_6_rd_A	12753494	10056	0	0
sw_rst_ctrl_n_7_rd_A	12753494	10161	0	0
sw_rst_regwen_0_rd_A	12753494	4903	0	0
sw_rst_regwen_1_rd_A	12753494	5032	0	0
sw_rst_regwen_2_rd_A	12753494	4978	0	0
sw_rst_regwen_3_rd_A	12753494	5049	0	0
sw_rst_regwen_4_rd_A	12753494	4867	0	0
sw_rst_regwen_5_rd_A	12753494	5062	0	0
sw_rst_regwen_6_rd_A	12753494	5258	0	0
sw_rst_regwen_7_rd_A	12753494	5121	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12753494	9055	0	0
T70	4457	160	0	0
T73	2319	6	0	0
T74	8072	344	0	0
T76	3378	436	0	0
T88	12056	714	0	0
T89	9684	2	0	0
T90	10621	3	0	0
T94	2732	231	0	0
T98	4598	96	0	0
T113	2467	2	0	0

alert_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12753494	4369	0	0
T11	266937	208	0	0
T12	74650	0	0	0
T13	2566	0	0	0
T14	6232	0	0	0
T15	2443	0	0	0
T25	1713	0	0	0
T26	5083	0	0	0
T27	38279	83	0	0
T28	1840	0	0	0
T79	1595	0	0	0
T103	0	24	0	0
T108	0	278	0	0
T115	0	450	0	0
T128	0	56	0	0
T129	0	11	0	0
T130	0	24	0	0
T131	0	35	0	0
T132	0	41	0	0

cpu_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12753494	4324	0	0
T11	266937	259	0	0
T12	74650	0	0	0
T13	2566	0	0	0
T14	6232	0	0	0
T15	2443	0	0	0
T25	1713	0	0	0
T26	5083	0	0	0
T27	38279	59	0	0
T28	1840	0	0	0
T79	1595	0	0	0
T103	0	21	0	0
T108	0	253	0	0
T115	0	414	0	0
T128	0	58	0	0
T129	0	3	0	0
T130	0	32	0	0
T131	0	46	0	0
T132	0	26	0	0

sw_rst_ctrl_n_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12753494	9819	0	0
T4	4508	57	0	0
T5	16391	0	0	0
T6	2551	0	0	0
T7	1372	0	0	0
T8	5477	0	0	0
T9	1225	0	0	0
T10	1525	0	0	0
T11	266937	325	0	0
T12	74650	0	0	0
T27	0	64	0	0
T58	0	118	0	0
T60	0	55	0	0
T68	0	12	0	0
T79	1595	0	0	0
T84	0	12	0	0
T103	0	34	0	0
T108	0	343	0	0
T109	0	96	0	0

sw_rst_ctrl_n_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12753494	9582	0	0
T4	4508	58	0	0
T5	16391	0	0	0
T6	2551	0	0	0
T7	1372	0	0	0
T8	5477	0	0	0
T9	1225	0	0	0
T10	1525	0	0	0
T11	266937	377	0	0
T12	74650	0	0	0
T27	0	73	0	0
T58	0	139	0	0
T60	0	61	0	0
T68	0	7	0	0
T79	1595	0	0	0
T84	0	9	0	0
T103	0	30	0	0
T108	0	387	0	0
T109	0	94	0	0

sw_rst_ctrl_n_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12753494	9584	0	0
T4	4508	59	0	0
T5	16391	0	0	0
T6	2551	0	0	0
T7	1372	0	0	0
T8	5477	0	0	0
T9	1225	0	0	0
T10	1525	0	0	0
T11	266937	311	0	0
T12	74650	0	0	0
T27	0	86	0	0
T58	0	128	0	0
T60	0	51	0	0
T68	0	18	0	0
T79	1595	0	0	0
T84	0	9	0	0
T103	0	22	0	0
T108	0	368	0	0
T109	0	99	0	0

sw_rst_ctrl_n_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12753494	9939	0	0
T4	4508	48	0	0
T5	16391	0	0	0
T6	2551	0	0	0
T7	1372	0	0	0
T8	5477	0	0	0
T9	1225	0	0	0
T10	1525	0	0	0
T11	266937	370	0	0
T12	74650	0	0	0
T27	0	83	0	0
T58	0	127	0	0
T60	0	70	0	0
T68	0	11	0	0
T79	1595	0	0	0
T84	0	2	0	0
T103	0	39	0	0
T108	0	416	0	0
T109	0	101	0	0

sw_rst_ctrl_n_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12753494	9764	0	0
T4	4508	26	0	0
T5	16391	0	0	0
T6	2551	0	0	0
T7	1372	0	0	0
T8	5477	0	0	0
T9	1225	0	0	0
T10	1525	0	0	0
T11	266937	354	0	0
T12	74650	0	0	0
T27	0	47	0	0
T58	0	140	0	0
T60	0	88	0	0
T68	0	24	0	0
T79	1595	0	0	0
T84	0	3	0	0
T103	0	40	0	0
T108	0	405	0	0
T109	0	106	0	0

sw_rst_ctrl_n_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12753494	9810	0	0
T4	4508	51	0	0
T5	16391	0	0	0
T6	2551	0	0	0
T7	1372	0	0	0
T8	5477	0	0	0
T9	1225	0	0	0
T10	1525	0	0	0
T11	266937	294	0	0
T12	74650	0	0	0
T27	0	47	0	0
T58	0	131	0	0
T60	0	73	0	0
T68	0	20	0	0
T79	1595	0	0	0
T84	0	14	0	0
T103	0	34	0	0
T108	0	300	0	0
T109	0	87	0	0

sw_rst_ctrl_n_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12753494	10056	0	0
T4	4508	44	0	0
T5	16391	0	0	0
T6	2551	0	0	0
T7	1372	0	0	0
T8	5477	0	0	0
T9	1225	0	0	0
T10	1525	0	0	0
T11	266937	343	0	0
T12	74650	0	0	0
T27	0	56	0	0
T58	0	136	0	0
T60	0	54	0	0
T68	0	12	0	0
T79	1595	0	0	0
T84	0	15	0	0
T103	0	30	0	0
T108	0	331	0	0
T109	0	88	0	0

sw_rst_ctrl_n_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12753494	10161	0	0
T4	4508	38	0	0
T5	16391	0	0	0
T6	2551	0	0	0
T7	1372	0	0	0
T8	5477	0	0	0
T9	1225	0	0	0
T10	1525	0	0	0
T11	266937	345	0	0
T12	74650	0	0	0
T27	0	96	0	0
T58	0	121	0	0
T60	0	48	0	0
T68	0	19	0	0
T79	1595	0	0	0
T84	0	13	0	0
T103	0	47	0	0
T108	0	354	0	0
T109	0	111	0	0

sw_rst_regwen_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12753494	4903	0	0
T11	266937	215	0	0
T12	74650	0	0	0
T13	2566	0	0	0
T14	6232	0	0	0
T15	2443	0	0	0
T25	1713	0	0	0
T26	5083	0	0	0
T27	38279	78	0	0
T28	1840	0	0	0
T58	0	34	0	0
T68	0	1	0	0
T79	1595	0	0	0
T84	0	9	0	0
T86	0	45	0	0
T87	0	2	0	0
T103	0	40	0	0
T108	0	260	0	0
T109	0	25	0	0

sw_rst_regwen_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12753494	5032	0	0
T11	266937	258	0	0
T12	74650	0	0	0
T13	2566	0	0	0
T14	6232	0	0	0
T15	2443	0	0	0
T25	1713	0	0	0
T26	5083	0	0	0
T27	38279	61	0	0
T28	1840	0	0	0
T58	0	20	0	0
T68	0	8	0	0
T79	1595	0	0	0
T84	0	11	0	0
T86	0	28	0	0
T103	0	21	0	0
T108	0	296	0	0
T109	0	29	0	0
T133	0	25	0	0

sw_rst_regwen_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12753494	4978	0	0
T11	266937	240	0	0
T12	74650	0	0	0
T13	2566	0	0	0
T14	6232	0	0	0
T15	2443	0	0	0
T25	1713	0	0	0
T26	5083	0	0	0
T27	38279	86	0	0
T28	1840	0	0	0
T58	0	28	0	0
T68	0	10	0	0
T79	1595	0	0	0
T84	0	6	0	0
T86	0	24	0	0
T87	0	12	0	0
T103	0	27	0	0
T108	0	280	0	0
T109	0	16	0	0

sw_rst_regwen_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12753494	5049	0	0
T11	266937	232	0	0
T12	74650	0	0	0
T13	2566	0	0	0
T14	6232	0	0	0
T15	2443	0	0	0
T25	1713	0	0	0
T26	5083	0	0	0
T27	38279	75	0	0
T28	1840	0	0	0
T58	0	31	0	0
T68	0	6	0	0
T79	1595	0	0	0
T84	0	8	0	0
T86	0	35	0	0
T103	0	28	0	0
T108	0	278	0	0
T109	0	28	0	0
T133	0	24	0	0

sw_rst_regwen_4_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12753494	4867	0	0
T11	266937	288	0	0
T12	74650	0	0	0
T13	2566	0	0	0
T14	6232	0	0	0
T15	2443	0	0	0
T25	1713	0	0	0
T26	5083	0	0	0
T27	38279	80	0	0
T28	1840	0	0	0
T58	0	31	0	0
T68	0	1	0	0
T79	1595	0	0	0
T86	0	49	0	0
T87	0	3	0	0
T103	0	28	0	0
T108	0	281	0	0
T109	0	15	0	0
T133	0	34	0	0

sw_rst_regwen_5_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12753494	5062	0	0
T11	266937	248	0	0
T12	74650	0	0	0
T13	2566	0	0	0
T14	6232	0	0	0
T15	2443	0	0	0
T25	1713	0	0	0
T26	5083	0	0	0
T27	38279	61	0	0
T28	1840	0	0	0
T58	0	20	0	0
T68	0	1	0	0
T79	1595	0	0	0
T84	0	5	0	0
T86	0	39	0	0
T87	0	8	0	0
T103	0	24	0	0
T108	0	305	0	0
T109	0	15	0	0

sw_rst_regwen_6_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12753494	5258	0	0
T11	266937	251	0	0
T12	74650	0	0	0
T13	2566	0	0	0
T14	6232	0	0	0
T15	2443	0	0	0
T25	1713	0	0	0
T26	5083	0	0	0
T27	38279	51	0	0
T28	1840	0	0	0
T58	0	40	0	0
T68	0	4	0	0
T79	1595	0	0	0
T84	0	6	0	0
T86	0	24	0	0
T87	0	6	0	0
T103	0	34	0	0
T108	0	311	0	0
T109	0	16	0	0

sw_rst_regwen_7_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	12753494	5121	0	0
T11	266937	257	0	0
T12	74650	0	0	0
T13	2566	0	0	0
T14	6232	0	0	0
T15	2443	0	0	0
T25	1713	0	0	0
T26	5083	0	0	0
T27	38279	71	0	0
T28	1840	0	0	0
T58	0	35	0	0
T68	0	4	0	0
T79	1595	0	0	0
T84	0	13	0	0
T86	0	40	0	0
T87	0	8	0	0
T103	0	26	0	0
T108	0	313	0	0
T109	0	24	0	0