Unified Coverage Report :: Module :: prim_rst_sync

Module : prim_rst_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync	100.00	100.00
tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync	100.00	100.00

---

Module Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_por_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_shadowed

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_io

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_io_div2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_lc_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_lc_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_d0_sys

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00					u_daon_sys_io_div4

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_device

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_host0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_spi_host1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_usb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_d0_usb_aon

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c0

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c1

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_d0_i2c2

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
g_scan_mux.u_scan_mux	100.00	100.00	100.00				100.00
u_sync	100.00	100.00				100.00

Line Coverage for Module : prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_daon_por.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_daon_por_io.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_daon_por_io_div2.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_daon_por_io_div4.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_daon_por_usb.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_daon_lc.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_d0_lc.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_daon_lc_shadowed.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_d0_lc_shadowed.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_daon_lc_aon.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_daon_lc_io.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_d0_lc_io.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_daon_lc_io_div2.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_d0_lc_io_div2.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_daon_lc_usb.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_d0_lc_usb.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_d0_sys.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_daon_sys_io_div4.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_d0_spi_device.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_d0_spi_host0.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_d0_spi_host1.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_d0_usb.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_d0_usb_aon.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_d0_i2c0.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_d0_i2c1.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1

Line Coverage for Instance : tb.dut.u_d0_i2c2.gen_rst_chk.u_prim_rst_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	35	1	1	100.00
CONT_ASSIGN	36	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' or '../src/lowrisc_prim_rst_sync_0/rtl/prim_rst_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
35	1	1
36	1	1