Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_rstmgr_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	639839	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

383219

1

T1

7153

T2

866

T3

1048

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	547077	1			T1	10470		T2	1351		T3	1558
values[0x0]	237594	1			T1	4386		T2	559		T3	647
values[0x1]	238387	1			T1	4279		T2	511		T3	574

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	536722	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

486336

1

T1

9075

T2

1105

T3

1344

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	4051	1			T1	85		T2	9		T3	8
valid_sources[0x01]	4416	1			T1	81		T2	5		T3	9
valid_sources[0x02]	3531	1			T1	74		T2	19		T3	9
valid_sources[0x03]	3684	1			T1	65		T2	4		T3	9
valid_sources[0x04]	3718	1			T1	75		T2	23		T3	11
valid_sources[0x05]	4105	1			T1	87		T2	15		T3	9
valid_sources[0x06]	4342	1			T1	80		T2	27		T3	9
valid_sources[0x07]	3346	1			T1	75		T2	22		T3	10
valid_sources[0x08]	4350	1			T1	82		T3	8		T4	1
valid_sources[0x09]	3457	1			T1	61		T2	7		T3	18
valid_sources[0x0a]	9939	1			T1	76		T2	8		T3	6
valid_sources[0x0b]	3494	1			T1	68		T2	1		T3	14
valid_sources[0x0c]	3208	1			T1	81		T2	8		T3	11
valid_sources[0x0d]	3154	1			T1	81		T2	5		T3	10
valid_sources[0x0e]	7458	1			T1	68		T2	20		T3	9
valid_sources[0x0f]	3405	1			T1	80		T2	7		T3	10
valid_sources[0x10]	4224	1			T1	84		T2	2		T3	6
valid_sources[0x11]	4076	1			T1	79		T2	3		T3	17
valid_sources[0x12]	3390	1			T1	58		T2	6		T3	5
valid_sources[0x13]	4021	1			T1	77		T2	11		T3	11
valid_sources[0x14]	6285	1			T1	65		T2	19		T3	11
valid_sources[0x15]	7351	1			T1	68		T2	10		T3	11
valid_sources[0x16]	3295	1			T1	92		T3	5		T5	9
valid_sources[0x17]	4529	1			T1	73		T2	3		T3	17
valid_sources[0x18]	6268	1			T1	65		T2	6		T3	15
valid_sources[0x19]	3083	1			T1	67		T2	20		T3	8
valid_sources[0x1a]	3585	1			T1	70		T2	17		T3	9
valid_sources[0x1b]	3444	1			T1	78		T2	14		T3	10
valid_sources[0x1c]	3812	1			T1	80		T2	19		T3	10
valid_sources[0x1d]	3848	1			T1	74		T2	1		T3	10
valid_sources[0x1e]	3990	1			T1	68		T2	18		T3	11
valid_sources[0x1f]	3728	1			T1	74		T2	21		T3	6
valid_sources[0x20]	3825	1			T1	77		T2	10		T3	10
valid_sources[0x21]	3663	1			T1	73		T2	12		T3	7
valid_sources[0x22]	3384	1			T1	69		T3	4		T5	24
valid_sources[0x23]	6712	1			T1	71		T2	2		T3	9
valid_sources[0x24]	3649	1			T1	75		T2	15		T3	9
valid_sources[0x25]	3887	1			T1	101		T2	3		T3	12
valid_sources[0x26]	3627	1			T1	79		T2	3		T3	7
valid_sources[0x27]	3740	1			T1	66		T2	19		T3	15
valid_sources[0x28]	4037	1			T1	63		T2	4		T3	8
valid_sources[0x29]	3274	1			T1	90		T2	5		T3	15
valid_sources[0x2a]	3656	1			T1	75		T2	8		T3	17
valid_sources[0x2b]	4003	1			T1	74		T2	15		T3	6
valid_sources[0x2c]	3629	1			T1	63		T2	31		T3	16
valid_sources[0x2d]	3760	1			T1	65		T2	12		T3	9
valid_sources[0x2e]	4646	1			T1	83		T2	6		T3	14
valid_sources[0x2f]	3578	1			T1	90		T2	8		T3	11
valid_sources[0x30]	4110	1			T1	57		T2	11		T3	9
valid_sources[0x31]	3321	1			T1	83		T2	13		T3	11
valid_sources[0x32]	4030	1			T1	85		T2	11		T3	13
valid_sources[0x33]	4504	1			T1	76		T2	22		T3	9
valid_sources[0x34]	3810	1			T1	69		T2	9		T3	10
valid_sources[0x35]	3536	1			T1	72		T2	9		T3	14
valid_sources[0x36]	5418	1			T1	73		T2	19		T3	14
valid_sources[0x37]	3453	1			T1	63		T2	4		T3	13
valid_sources[0x38]	3466	1			T1	74		T3	11		T5	9
valid_sources[0x39]	4370	1			T1	76		T2	1		T3	8
valid_sources[0x3a]	3345	1			T1	60		T2	5		T3	9
valid_sources[0x3b]	3855	1			T1	70		T2	16		T3	12
valid_sources[0x3c]	3789	1			T1	87		T2	12		T3	16
valid_sources[0x3d]	5216	1			T1	77		T3	15		T5	24
valid_sources[0x3e]	3069	1			T1	87		T2	6		T3	12
valid_sources[0x3f]	3192	1			T1	63		T2	17		T3	19
valid_sources[0x40]	3381	1			T1	57		T2	6		T3	8
valid_sources[0x41]	3562	1			T1	72		T2	14		T3	15
valid_sources[0x42]	3761	1			T1	69		T2	15		T3	7
valid_sources[0x43]	3610	1			T1	77		T2	8		T3	15
valid_sources[0x44]	4005	1			T1	63		T2	4		T3	2
valid_sources[0x45]	3292	1			T1	57		T2	10		T3	3
valid_sources[0x46]	3205	1			T1	79		T2	31		T3	9
valid_sources[0x47]	4090	1			T1	81		T2	8		T3	8
valid_sources[0x48]	3412	1			T1	67		T2	10		T3	8
valid_sources[0x49]	4609	1			T1	80		T2	12		T3	6
valid_sources[0x4a]	3412	1			T1	95		T2	15		T3	7
valid_sources[0x4b]	3235	1			T1	77		T3	12		T4	1
valid_sources[0x4c]	5521	1			T1	73		T2	7		T3	15
valid_sources[0x4d]	3317	1			T1	82		T2	5		T3	13
valid_sources[0x4e]	3263	1			T1	86		T2	3		T3	4
valid_sources[0x4f]	3178	1			T1	81		T2	10		T3	7
valid_sources[0x50]	3929	1			T1	85		T2	18		T3	10
valid_sources[0x51]	3696	1			T1	67		T2	9		T3	11
valid_sources[0x52]	3517	1			T1	82		T2	7		T3	17
valid_sources[0x53]	3525	1			T1	66		T2	6		T3	20
valid_sources[0x54]	3698	1			T1	78		T2	5		T3	16
valid_sources[0x55]	4044	1			T1	92		T2	11		T3	20
valid_sources[0x56]	2814	1			T1	85		T2	13		T3	9
valid_sources[0x57]	4365	1			T1	80		T2	4		T3	16
valid_sources[0x58]	4285	1			T1	73		T3	14		T5	15
valid_sources[0x59]	3621	1			T1	88		T2	9		T3	5
valid_sources[0x5a]	3113	1			T1	67		T2	14		T3	7
valid_sources[0x5b]	3147	1			T1	79		T2	3		T3	10
valid_sources[0x5c]	4069	1			T1	78		T2	4		T3	9
valid_sources[0x5d]	4382	1			T1	49		T2	5		T3	13
valid_sources[0x5e]	3370	1			T1	81		T2	5		T3	14
valid_sources[0x5f]	4316	1			T1	42		T2	4		T3	15
valid_sources[0x60]	3887	1			T1	88		T2	6		T3	14
valid_sources[0x61]	3189	1			T1	56		T2	6		T3	19
valid_sources[0x62]	3145	1			T1	73		T2	21		T3	20
valid_sources[0x63]	3812	1			T1	78		T2	2		T3	7
valid_sources[0x64]	6542	1			T1	58		T2	5		T3	9
valid_sources[0x65]	5226	1			T1	85		T2	9		T3	11
valid_sources[0x66]	3095	1			T1	69		T2	2		T3	18
valid_sources[0x67]	3362	1			T1	75		T2	3		T3	15
valid_sources[0x68]	3079	1			T1	46		T2	11		T3	17
valid_sources[0x69]	4730	1			T1	73		T2	5		T3	13
valid_sources[0x6a]	3947	1			T1	79		T2	8		T3	9
valid_sources[0x6b]	3571	1			T1	93		T2	4		T3	15
valid_sources[0x6c]	3481	1			T1	72		T2	1		T3	7
valid_sources[0x6d]	3966	1			T1	73		T2	15		T3	5
valid_sources[0x6e]	3517	1			T1	87		T2	6		T3	7
valid_sources[0x6f]	3432	1			T1	90		T2	18		T3	10
valid_sources[0x70]	4238	1			T1	71		T2	9		T3	10
valid_sources[0x71]	3713	1			T1	69		T2	2		T3	10
valid_sources[0x72]	3845	1			T1	74		T2	7		T3	17
valid_sources[0x73]	3252	1			T1	69		T2	6		T3	13
valid_sources[0x74]	4920	1			T1	79		T2	2		T3	9
valid_sources[0x75]	3862	1			T1	82		T2	20		T3	7
valid_sources[0x76]	3184	1			T1	81		T2	5		T3	6
valid_sources[0x77]	3814	1			T1	61		T2	11		T3	10
valid_sources[0x78]	3748	1			T1	102		T2	2		T3	12
valid_sources[0x79]	4565	1			T1	81		T2	4		T3	12
valid_sources[0x7a]	3919	1			T1	74		T2	12		T3	10
valid_sources[0x7b]	3130	1			T1	70		T3	8		T5	47
valid_sources[0x7c]	4069	1			T1	96		T2	8		T3	8
valid_sources[0x7d]	3904	1			T1	76		T3	11		T5	31
valid_sources[0x7e]	5279	1			T1	65		T2	1		T3	11
valid_sources[0x7f]	3266	1			T1	75		T2	4		T3	10
valid_sources[0x80]	2962	1			T1	97		T2	4		T3	15

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

255835

1

T1

4944

T2

601

T3

715

values[0x0]

all_enables

biggest_size

83116

1

T1

1491

T2

183

T3

224

values[0x1]

all_enables

biggest_size

44268

1

T1

718

T2

82

T3

109