Unified Coverage Report :: Module :: pwrmgr_rstmgr_sva_if

Module : pwrmgr_rstmgr_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_rstmgr_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.pwrmgr_rstmgr_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr_rstmgr_sva_if

	Line No.	Total	Covered	Percent
TOTAL		1	1	100.00
ALWAYS	33	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' or '../src/lowrisc_dv_pwrmgr_rstmgr_sva_if_0.1/pwrmgr_rstmgr_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
33	1	1

---

Cond Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Covered	Percent
Conditions	2	2	100.00
Logical	2	2	100.00
Non-Logical	0	0
Event	0	0

 LINE       33
 EXPRESSION (((!rst_slow_ni)) || disable_sva)
             --------1-------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T1,T2,T3

---

Assert Coverage for Module : pwrmgr_rstmgr_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	8	8	100.00	8	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	8	8	100.00	8	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
gen_assertions_per_power_domains[0].LcHandshakeOff_A	11876583	13574	0	0
gen_assertions_per_power_domains[0].LcHandshakeOn_A	11876583	125159	0	0
gen_assertions_per_power_domains[0].SysHandshakeOff_A	11876583	7049072	0	0
gen_assertions_per_power_domains[0].SysHandshakeOn_A	11876583	200402	0	0
gen_assertions_per_power_domains[1].LcHandshakeOff_A	11876583	13574	0	0
gen_assertions_per_power_domains[1].LcHandshakeOn_A	11876583	125159	0	0
gen_assertions_per_power_domains[1].SysHandshakeOff_A	11876583	7049072	0	0
gen_assertions_per_power_domains[1].SysHandshakeOn_A	11876583	200402	0	0

gen_assertions_per_power_domains[0].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876583	13574	0	0
T1	270175	245	0	0
T2	25686	32	0	0
T3	16515	36	0	0
T4	3507	4	0	0
T5	52954	61	0	0
T6	2344	0	0	0
T7	4375	19	0	0
T8	5663	0	0	0
T9	3371	10	0	0
T10	1712	4	0	0
T11	0	75	0	0
T22	0	1	0	0

gen_assertions_per_power_domains[0].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876583	125159	0	0
T1	270175	2229	0	0
T2	25686	288	0	0
T3	16515	324	0	0
T4	3507	38	0	0
T5	52954	565	0	0
T6	2344	0	0	0
T7	4375	171	0	0
T8	5663	0	0	0
T9	3371	90	0	0
T10	1712	36	0	0
T11	0	702	0	0
T22	0	9	0	0

gen_assertions_per_power_domains[0].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876583	7049072	0	0
T1	270175	215745	0	0
T2	25686	18772	0	0
T3	16515	7723	0	0
T4	3507	2558	0	0
T5	52954	40731	0	0
T6	2344	774	0	0
T7	4375	3459	0	0
T8	5663	571	0	0
T9	3371	2628	0	0
T10	1712	1079	0	0

gen_assertions_per_power_domains[0].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876583	200402	0	0
T1	270175	3593	0	0
T2	25686	455	0	0
T3	16515	532	0	0
T4	3507	49	0	0
T5	52954	894	0	0
T6	2344	0	0	0
T7	4375	292	0	0
T8	5663	0	0	0
T9	3371	146	0	0
T10	1712	62	0	0
T11	0	1137	0	0
T22	0	19	0	0

gen_assertions_per_power_domains[1].LcHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876583	13574	0	0
T1	270175	245	0	0
T2	25686	32	0	0
T3	16515	36	0	0
T4	3507	4	0	0
T5	52954	61	0	0
T6	2344	0	0	0
T7	4375	19	0	0
T8	5663	0	0	0
T9	3371	10	0	0
T10	1712	4	0	0
T11	0	75	0	0
T22	0	1	0	0

gen_assertions_per_power_domains[1].LcHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876583	125159	0	0
T1	270175	2229	0	0
T2	25686	288	0	0
T3	16515	324	0	0
T4	3507	38	0	0
T5	52954	565	0	0
T6	2344	0	0	0
T7	4375	171	0	0
T8	5663	0	0	0
T9	3371	90	0	0
T10	1712	36	0	0
T11	0	702	0	0
T22	0	9	0	0

gen_assertions_per_power_domains[1].SysHandshakeOff_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876583	7049072	0	0
T1	270175	215745	0	0
T2	25686	18772	0	0
T3	16515	7723	0	0
T4	3507	2558	0	0
T5	52954	40731	0	0
T6	2344	774	0	0
T7	4375	3459	0	0
T8	5663	571	0	0
T9	3371	2628	0	0
T10	1712	1079	0	0

gen_assertions_per_power_domains[1].SysHandshakeOn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876583	200402	0	0
T1	270175	3593	0	0
T2	25686	455	0	0
T3	16515	532	0	0
T4	3507	49	0	0
T5	52954	894	0	0
T6	2344	0	0	0
T7	4375	292	0	0
T8	5663	0	0	0
T9	3371	146	0	0
T10	1712	62	0	0
T11	0	1137	0	0
T22	0	19	0	0