Unified Coverage Report :: Module :: rstmgr_cascading_sva_if

Module : rstmgr_cascading_sva_if

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.rstmgr_cascading_sva_if	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.rstmgr_cascading_sva_if

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.55	100.00	98.21	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : rstmgr_cascading_sva_if

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	100	1	1	100.00
ALWAYS	103	1	1	100.00
ALWAYS	107	1	1	100.00
ALWAYS	127	1	1	100.00
ALWAYS	138	1	1	100.00
ALWAYS	141	1	1	100.00
ALWAYS	144	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' or '../src/lowrisc_dv_rstmgr_sva_ifs_0.1/rstmgr_cascading_sva_if.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
100	1	1
103	1	1
107	1	1
127	1	1
138	1	1
141	1	1
144	1	1

---

Cond Coverage for Module : rstmgr_cascading_sva_if

	Total	Covered	Percent
Conditions	6	6	100.00
Logical	6	6	100.00
Non-Logical	0	0
Event	0	0

 LINE       103
 EXPRESSION (((!scanmode)) || scan_rst_ni)
             ------1------    -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3

 LINE       107
 EXPRESSION (por_n_i[rstmgr_pkg::DomainAonSel] && ((!scanmode)))
             ----------------1----------------    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : rstmgr_cascading_sva_if

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	31	31	100.00	31	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	31	31	100.00	31	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CascadeEffAonToRstPorAboveFall_A	55772996	8900	0	0
CascadeEffAonToRstPorAboveRise_A	55772996	8900	0	0
CascadeEffAonToRstPorIoAboveFall_A	53540381	8900	0	0
CascadeEffAonToRstPorIoAboveRise_A	53540381	8900	0	0
CascadeEffAonToRstPorIoDiv2AboveFall_A	26771067	8900	0	0
CascadeEffAonToRstPorIoDiv2AboveRise_A	26771067	8900	0	0
CascadeEffAonToRstPorIoDiv4AboveFall_A	13385131	8900	0	0
CascadeEffAonToRstPorIoDiv4AboveRise_A	13385131	8900	0	0
CascadeEffAonToRstPorUcbAboveFall_A	26771131	8900	0	0
CascadeEffAonToRstPorUcbAboveRise_A	26771131	8900	0	0
CascadeLcToLcAboveFall_A	55772996	22474	0	0
CascadeLcToLcAboveRise_A	55772996	22474	0	0
CascadeLcToLcAonAboveFall_A	1690295	22474	0	0
CascadeLcToLcAonAboveRise_A	1690295	22474	0	0
CascadeLcToLcShadowedAboveFall_A	55772996	22474	0	0
CascadeLcToLcShadowedAboveRise_A	55772996	22474	0	0
CascadePorToAonAboveFall_A	1690295	7006	0	0
CascadeSysToSysAboveFall_A	55772996	22474	0	0
CascadeSysToSysAboveRise_A	55772996	22474	0	0
ScanRstToAonRise_A	1690295	236	0	0
StablePorToAonRise_A	1690295	8900	0	0
g_power_domains[0].CascadeLcToSysAboveFall_A	11876583	22474	0	0
g_power_domains[0].CascadeLcToSysAboveRise_A	11876583	22474	0	0
g_power_domains[0].CascadeLocalRstToLcAboveFall_A	11876583	22474	0	0
g_power_domains[0].CascadeLocalRstToLcAboveRise_A	11876583	22474	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A	13385131	22474	0	0
g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A	13385131	22474	0	0
g_power_domains[1].CascadeLcToSysAboveFall_A	11876583	22474	0	0
g_power_domains[1].CascadeLcToSysAboveRise_A	11876583	22474	0	0
g_power_domains[1].CascadeLocalRstToLcAboveFall_A	11876583	22474	0	0
g_power_domains[1].CascadeLocalRstToLcAboveRise_A	11876583	22474	0	0

CascadeEffAonToRstPorAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55772996	8900	0	0
T1	125900	116	0	0
T2	125269	16	0	0
T3	87712	19	0	0
T4	15619	2	0	0
T5	248331	26	0	0
T6	10244	2	0	0
T7	23133	1	0	0
T8	24268	8	0	0
T9	17641	1	0	0
T10	8504	1	0	0

CascadeEffAonToRstPorAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55772996	8900	0	0
T1	125900	116	0	0
T2	125269	16	0	0
T3	87712	19	0	0
T4	15619	2	0	0
T5	248331	26	0	0
T6	10244	2	0	0
T7	23133	1	0	0
T8	24268	8	0	0
T9	17641	1	0	0
T10	8504	1	0	0

CascadeEffAonToRstPorIoAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53540381	8900	0	0
T1	120864	116	0	0
T2	120249	16	0	0
T3	84199	19	0	0
T4	14996	2	0	0
T5	238366	26	0	0
T6	9835	2	0	0
T7	22205	1	0	0
T8	23296	8	0	0
T9	16934	1	0	0
T10	8164	1	0	0

CascadeEffAonToRstPorIoAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	53540381	8900	0	0
T1	120864	116	0	0
T2	120249	16	0	0
T3	84199	19	0	0
T4	14996	2	0	0
T5	238366	26	0	0
T6	9835	2	0	0
T7	22205	1	0	0
T8	23296	8	0	0
T9	16934	1	0	0
T10	8164	1	0	0

CascadeEffAonToRstPorIoDiv2AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26771067	8900	0	0
T1	604362	116	0	0
T2	60122	16	0	0
T3	42098	19	0	0
T4	7500	2	0	0
T5	119187	26	0	0
T6	4916	2	0	0
T7	11104	1	0	0
T8	11649	8	0	0
T9	8467	1	0	0
T10	4082	1	0	0

CascadeEffAonToRstPorIoDiv2AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26771067	8900	0	0
T1	604362	116	0	0
T2	60122	16	0	0
T3	42098	19	0	0
T4	7500	2	0	0
T5	119187	26	0	0
T6	4916	2	0	0
T7	11104	1	0	0
T8	11649	8	0	0
T9	8467	1	0	0
T10	4082	1	0	0

CascadeEffAonToRstPorIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13385131	8900	0	0
T1	302151	116	0	0
T2	30065	16	0	0
T3	21045	19	0	0
T4	3748	2	0	0
T5	59596	26	0	0
T6	2458	2	0	0
T7	5551	1	0	0
T8	5822	8	0	0
T9	4233	1	0	0
T10	2040	1	0	0

CascadeEffAonToRstPorIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13385131	8900	0	0
T1	302151	116	0	0
T2	30065	16	0	0
T3	21045	19	0	0
T4	3748	2	0	0
T5	59596	26	0	0
T6	2458	2	0	0
T7	5551	1	0	0
T8	5822	8	0	0
T9	4233	1	0	0
T10	2040	1	0	0

CascadeEffAonToRstPorUcbAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26771131	8900	0	0
T1	604339	116	0	0
T2	60123	16	0	0
T3	42094	19	0	0
T4	7500	2	0	0
T5	119210	26	0	0
T6	4916	2	0	0
T7	11104	1	0	0
T8	11649	8	0	0
T9	8466	1	0	0
T10	4082	1	0	0

CascadeEffAonToRstPorUcbAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	26771131	8900	0	0
T1	604339	116	0	0
T2	60123	16	0	0
T3	42094	19	0	0
T4	7500	2	0	0
T5	119210	26	0	0
T6	4916	2	0	0
T7	11104	1	0	0
T8	11649	8	0	0
T9	8466	1	0	0
T10	4082	1	0	0

CascadeLcToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55772996	22474	0	0
T1	125900	361	0	0
T2	125269	48	0	0
T3	87712	55	0	0
T4	15619	6	0	0
T5	248331	87	0	0
T6	10244	2	0	0
T7	23133	20	0	0
T8	24268	8	0	0
T9	17641	11	0	0
T10	8504	5	0	0

CascadeLcToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55772996	22474	0	0
T1	125900	361	0	0
T2	125269	48	0	0
T3	87712	55	0	0
T4	15619	6	0	0
T5	248331	87	0	0
T6	10244	2	0	0
T7	23133	20	0	0
T8	24268	8	0	0
T9	17641	11	0	0
T10	8504	5	0	0

CascadeLcToLcAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1690295	22474	0	0
T1	38178	361	0	0
T2	3812	48	0	0
T3	2695	55	0	0
T4	467	6	0	0
T5	7494	87	0	0
T6	306	2	0	0
T7	692	20	0	0
T8	729	8	0	0
T9	528	11	0	0
T10	254	5	0	0

CascadeLcToLcAonAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1690295	22474	0	0
T1	38178	361	0	0
T2	3812	48	0	0
T3	2695	55	0	0
T4	467	6	0	0
T5	7494	87	0	0
T6	306	2	0	0
T7	692	20	0	0
T8	729	8	0	0
T9	528	11	0	0
T10	254	5	0	0

CascadeLcToLcShadowedAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55772996	22474	0	0
T1	125900	361	0	0
T2	125269	48	0	0
T3	87712	55	0	0
T4	15619	6	0	0
T5	248331	87	0	0
T6	10244	2	0	0
T7	23133	20	0	0
T8	24268	8	0	0
T9	17641	11	0	0
T10	8504	5	0	0

CascadeLcToLcShadowedAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55772996	22474	0	0
T1	125900	361	0	0
T2	125269	48	0	0
T3	87712	55	0	0
T4	15619	6	0	0
T5	248331	87	0	0
T6	10244	2	0	0
T7	23133	20	0	0
T8	24268	8	0	0
T9	17641	11	0	0
T10	8504	5	0	0

CascadePorToAonAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1690295	7006	0	0
T1	38178	64	0	0
T2	3812	7	0	0
T3	2695	11	0	0
T4	467	1	0	0
T5	7494	13	0	0
T6	306	5	0	0
T7	692	1	0	0
T8	729	8	0	0
T9	528	1	0	0
T10	254	1	0	0

CascadeSysToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55772996	22474	0	0
T1	125900	361	0	0
T2	125269	48	0	0
T3	87712	55	0	0
T4	15619	6	0	0
T5	248331	87	0	0
T6	10244	2	0	0
T7	23133	20	0	0
T8	24268	8	0	0
T9	17641	11	0	0
T10	8504	5	0	0

CascadeSysToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	55772996	22474	0	0
T1	125900	361	0	0
T2	125269	48	0	0
T3	87712	55	0	0
T4	15619	6	0	0
T5	248331	87	0	0
T6	10244	2	0	0
T7	23133	20	0	0
T8	24268	8	0	0
T9	17641	11	0	0
T10	8504	5	0	0

ScanRstToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1690295	236	0	0
T1	38178	7	0	0
T2	3812	1	0	0
T3	2695	0	0	0
T4	467	1	0	0
T5	7494	0	0	0
T6	306	0	0	0
T7	692	0	0	0
T8	729	0	0	0
T9	528	0	0	0
T10	254	0	0	0
T33	0	4	0	0
T34	0	14	0	0
T35	0	3	0	0
T66	0	5	0	0
T70	0	1	0	0
T73	0	5	0	0
T76	0	3	0	0

StablePorToAonRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1690295	8900	0	0
T1	38178	116	0	0
T2	3812	16	0	0
T3	2695	19	0	0
T4	467	2	0	0
T5	7494	26	0	0
T6	306	2	0	0
T7	692	1	0	0
T8	729	8	0	0
T9	528	1	0	0
T10	254	1	0	0

g_power_domains[0].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876583	22474	0	0
T1	270175	361	0	0
T2	25686	48	0	0
T3	16515	55	0	0
T4	3507	6	0	0
T5	52954	87	0	0
T6	2344	2	0	0
T7	4375	20	0	0
T8	5663	8	0	0
T9	3371	11	0	0
T10	1712	5	0	0

g_power_domains[0].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876583	22474	0	0
T1	270175	361	0	0
T2	25686	48	0	0
T3	16515	55	0	0
T4	3507	6	0	0
T5	52954	87	0	0
T6	2344	2	0	0
T7	4375	20	0	0
T8	5663	8	0	0
T9	3371	11	0	0
T10	1712	5	0	0

g_power_domains[0].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876583	22474	0	0
T1	270175	361	0	0
T2	25686	48	0	0
T3	16515	55	0	0
T4	3507	6	0	0
T5	52954	87	0	0
T6	2344	2	0	0
T7	4375	20	0	0
T8	5663	8	0	0
T9	3371	11	0	0
T10	1712	5	0	0

g_power_domains[0].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876583	22474	0	0
T1	270175	361	0	0
T2	25686	48	0	0
T3	16515	55	0	0
T4	3507	6	0	0
T5	52954	87	0	0
T6	2344	2	0	0
T7	4375	20	0	0
T8	5663	8	0	0
T9	3371	11	0	0
T10	1712	5	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13385131	22474	0	0
T1	302151	361	0	0
T2	30065	48	0	0
T3	21045	55	0	0
T4	3748	6	0	0
T5	59596	87	0	0
T6	2458	2	0	0
T7	5551	20	0	0
T8	5822	8	0	0
T9	4233	11	0	0
T10	2040	5	0	0

g_power_domains[0].gen_sys_io_div4_chk.CascadeSysToSysIoDiv4AboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	13385131	22474	0	0
T1	302151	361	0	0
T2	30065	48	0	0
T3	21045	55	0	0
T4	3748	6	0	0
T5	59596	87	0	0
T6	2458	2	0	0
T7	5551	20	0	0
T8	5822	8	0	0
T9	4233	11	0	0
T10	2040	5	0	0

g_power_domains[1].CascadeLcToSysAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876583	22474	0	0
T1	270175	361	0	0
T2	25686	48	0	0
T3	16515	55	0	0
T4	3507	6	0	0
T5	52954	87	0	0
T6	2344	2	0	0
T7	4375	20	0	0
T8	5663	8	0	0
T9	3371	11	0	0
T10	1712	5	0	0

g_power_domains[1].CascadeLcToSysAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876583	22474	0	0
T1	270175	361	0	0
T2	25686	48	0	0
T3	16515	55	0	0
T4	3507	6	0	0
T5	52954	87	0	0
T6	2344	2	0	0
T7	4375	20	0	0
T8	5663	8	0	0
T9	3371	11	0	0
T10	1712	5	0	0

g_power_domains[1].CascadeLocalRstToLcAboveFall_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876583	22474	0	0
T1	270175	361	0	0
T2	25686	48	0	0
T3	16515	55	0	0
T4	3507	6	0	0
T5	52954	87	0	0
T6	2344	2	0	0
T7	4375	20	0	0
T8	5663	8	0	0
T9	3371	11	0	0
T10	1712	5	0	0

g_power_domains[1].CascadeLocalRstToLcAboveRise_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	11876583	22474	0	0
T1	270175	361	0	0
T2	25686	48	0	0
T3	16515	55	0	0
T4	3507	6	0	0
T5	52954	87	0	0
T6	2344	2	0	0
T7	4375	20	0	0
T8	5663	8	0	0
T9	3371	11	0	0
T10	1712	5	0	0